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soc: atmel: same5x: Disable cache

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The sam0 CMCC configure Cortex-M cache controller. However, it is not
clear how the cache management should be performed. It is nor clear if
instructions like SCB_EnableICache can be used. In this case, if cache
management should be made only by CMCC it may require a dedicated
implementation.

Besides above, the CPU_CORTEX_M4 do not define cache by default which
can signal a bad configuration in tree since the SOC_SERIES_SAME54 do
not define which caches should be available.

This force cache controller disable to avoid issues.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke 2023-08-03 13:00:02 +02:00 • committed by Carles Cufí
commit ee15b1ff05
1 changed files with 8 additions and 2 deletions
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10
soc/arm/atmel_sam0/common/soc_samd5x.c
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@ -117,8 +117,14 @@ void z_arm_platform_init(void)
dfll_div = 1;
}
/* enable the Cortex M Cache Controller */
CMCC->CTRL.bit.CEN = 1;
/*
* Force Cortex M Cache Controller disabled
*
* It is not clear if regular Cortex-M instructions can be used to
* perform cache maintenance or this is a proprietary cache controller
* that require special SoC support.
*/
CMCC->CTRL.bit.CEN = 0;
gclk_reset();
osc32k_init();