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ARC: add scalar VPX port

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Add add scalar ARC VPX port and nSIM-based VPX5 platform
(close to vpx5_integer_full template)

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
This commit is contained in:
Evgeniy Paltsev 2023-08-03 16:51:25 +01:00 • committed by Fabio Baltieri
commit 45e3cfc220
10 changed files with 312 additions and 0 deletions
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1
boards/arc/nsim/doc/index.rst
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@ -30,6 +30,7 @@ available configurations are listed below:
* ``nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4
* ``nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
* ``nsim_hs_smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
* ``nsim_vpx5`` - ARCv2 VPX5 core, close to vpx5_integer_full template
* ``nsim_hs5x`` - 32-bit ARCv3 HS core with rich set of options
* ``nsim_hs6x`` - 64-bit ARCv3 HS core with rich set of options

31
boards/arc/nsim/nsim_vpx5.dts Normal file
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@ -0,0 +1,31 @@
/*
* Copyright (c) 2023, Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#define ICCM_SIZE DT_SIZE_K(256)
#define DCCM_SIZE DT_SIZE_K(256)
#define UART0_IRQ_NUM 23
#include "nsim.dtsi"
#include "nsim-ccm-mem.dtsi"
#include "nsim-uart-ns16550.dtsi"
/ {
model = "snps,nsim_hs";
compatible = "snps,nsim_hs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs";
reg = <0>;
};
};
};

12
boards/arc/nsim/nsim_vpx5.yaml Normal file
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@ -0,0 +1,12 @@
identifier: nsim_vpx5
name: VPX5 nSIM simulator
type: sim
simulation: nsim
simulation_exec: nsimdrv
arch: arc
toolchain:
- arcmwdt
testing:
ignore_tags:
- net
- bluetooth

14
boards/arc/nsim/nsim_vpx5_defconfig Normal file
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@ -0,0 +1,14 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_NSIM=y
CONFIG_SOC_NSIM_VPX5=y
CONFIG_BOARD_NSIM=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_XIP=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_ARC_EXCEPTION_DEBUG=y

96
boards/arc/nsim/support/mdb_vpx5.args Normal file
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@ -0,0 +1,96 @@
-arcv2hs
-core4
-uarch_rev=1:4
-Xcode_density
-rgf_num_banks=1
-rgf_num_wr_ports=2
-Xatomic
-Xll64
-Xunaligned
-Xdiv_rem=radix4
-Xswap
-Xbitscan
-Xmpy_option=qmpyh
-Xshift_assist
-Xbarrel_shifter
-Xtimer0
-Xtimer0_level=0
-Xtimer1
-Xtimer1_level=0
-Xrtc
-action_points=8
-ap_feature=1
-Xstack_check
-dmp_per0_base=14
-dmp_per0_limit=15
-volatile_base=12
-volatile_limit=0
-volatile_strict_ordering
-bpu_bc_entries=1024
-bpu_pt_entries=8192
-bpu_rs_entries=8
-bpu_bc_full_tag=1
-bpu_tosq_entries=5
-bpu_fb_entries=2
-interrupts=24
-interrupt_priorities=4
-ext_interrupts=8
-interrupt_base=0x0
-intvbase_ext
-dcache=32768,64,2,a
-dcache_version=5
-dcache_feature=2
-dcache_mem_cycles=1
-icache=32768,128,4,a
-icache_version=4
-icache_feature=2
-dccm_size=0x40000
-dccm_base=0x80000000
-dccm_mem_cycles=1
-iccm0_size=0x40000
-iccm0_base=0x00000000
-Xpct_counters=16
-Xpct_interrupt
-arconnect
-connect_asi=2
-connect_ici=3
-connect_icd=2
-connect_gfrc=4
-connect_idu=2
-connect_idu_cirqnum=4
-connect_ivc=1
-stu=4
-stu_initiator_num=1
-stu_initiator_dbw=128
-stu_phy_ch_num=1
-stu_req_fifo_depth=32
-stu_buffer_size=32
-stu_perf
-Xvdsp4
-Xvec_unit_rev_minor=1
-Xvec_width=512
-Xvec_mem_size=256k
-Xvec_mem_banks=32
-Xvec_mem_bank_width=16
-Xvec_max_fetch_size=16
-Xvec_num_slots=3
-Xvec_super_with_scalar
-Xvec_regs=40
-Xvec_fast=0
-Xvec_num_rd_ports=6
-Xvec_num_acc=8
-Xvec_num_mpy=2
-Xvec_mpy32
-Xvec_num_alu=3
-Xvec_guard_bit_option=2
-Xvec_mem_topology=0
-Xvec_stack_check
-Xvec_mem_base=0x90000000
-cluster_version=5
-scu
-scu_stb_entries=8
-scu_coherent_io=1
-cluster_peripheral_interfaces=1
-clock_gating
-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
-noprofile

105
boards/arc/nsim/support/nsim_vpx5.props Normal file
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@ -0,0 +1,105 @@
nsim_isa_family=av2hs
nsim_isa_core=4
arcver=0x54
nsim_isa_uarch_rev_major=1
nsim_isa_uarch_rev_minor=4
nsim_isa_code_density_option=2
nsim_isa_rgf_num_banks=1
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_atomic_option=1
nsim_isa_ll64_option=1
nsim_isa_unaligned_option=1
nsim_isa_div_rem_option=2
nsim_isa_swap_option=1
nsim_isa_bitscan_option=1
nsim_isa_mpy_option=9
nsim_isa_shift_option=3
nsim_isa_enable_timer_0=1
nsim_isa_timer_0_int_level=0
nsim_isa_enable_timer_1=1
nsim_isa_timer_1_int_level=0
nsim_isa_rtc_option=1
nsim_isa_num_actionpoints=8
nsim_isa_aps_feature=1
nsim_isa_stack_checking=1
nsim_isa_has_dmp_peripheral=1
nsim_isa_dmp_peripheral_version=2
nsim_isa_dmp_peripheral_count=1
nsim_isa_dmp_peripheral_base0=14
nsim_isa_dmp_peripheral_limit0=15
nsim_isa_volatile_base=12
nsim_isa_volatile_limit=0
nsim_isa_volatile_disable=0
nsim_isa_volatile_strict_ordering=1
nsim_bpu_bc_entries=1024
nsim_bpu_pt_entries=8192
nsim_bpu_rs_entries=8
nsim_bpu_bc_full_tag=1
nsim_bpu_tosq_entries=5
nsim_bpu_fb_entries=2
nsim_isa_number_of_interrupts=24
nsim_isa_number_of_levels=4
nsim_isa_number_of_external_interrupts=8
nsim_isa_intvbase_preset=0x0
nsim_isa_intvbase_ext=1
dcache=32768,64,2,a
nsim_isa_dc_version=5
nsim_isa_dc_feature_level=2
nsim_isa_dc_mem_cycles=1
icache=32768,128,4,a
nsim_isa_ic_version=4
nsim_isa_ic_feature_level=2
dccm_size=0x40000
dccm_base=0x80000000
nsim_isa_dccm_mem_cycles=1
iccm0_size=0x40000
iccm0_base=0x00000000
nsim_isa_pct_counters=16
nsim_isa_pct_interrupt=1
nsim_connect=2
nsim_connect_asi=2
nsim_connect_ici=3
nsim_connect_icd=2
nsim_connect_gfrc=4
nsim_connect_idu=2
nsim_connect_idu_cirqnum=4
nsim_connect_ivc=1
nsim_stu=4
nsim_stu_initiator_num=1
nsim_stu_initiator_dbw=128
nsim_stu_phy_ch_num=1
nsim_stu_req_fifo_depth=32
nsim_stu_buffer_size=32
nsim_stu_perf=1
nsim_isa_vec_unit=4
nsim_isa_vec_unit_rev_minor=1
nsim_isa_vec_width=512
vec_mem_size=256k
nsim_isa_vec_mem_banks=32
nsim_isa_vec_mem_bank_width=16
nsim_isa_vec_max_fetch_size=16
nsim_isa_vec_num_slots=3
nsim_isa_vec_super_with_scalar=1
nsim_isa_vec_regs=40
nsim_isa_vec_fast=0
nsim_isa_vec_num_rd_ports=6
nsim_isa_vec_num_acc=8
nsim_isa_vec_num_mpy=2
nsim_isa_vec_mpy32=1
nsim_isa_vec_num_alu=3
nsim_isa_vec_guard_bit_option=2
nsim_isa_vec_mem_topology=0
nsim_isa_vec_stack_check=1
vec_mem_base=0x90000000
nsim_cluster_version=5
nsim_isa_has_scu=1
nsim_isa_scu_stb_entries=8
nsim_isa_scu_coherent_io=1
nsim_cluster_peripheral_interfaces=1
nsim_isa_clock_gating=1
nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=23

16
soc/arc/snps_nsim/CMakeLists.txt
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@ -14,6 +14,10 @@ if(COMPILER STREQUAL gcc)
zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all)
endif()
endif()
if(CONFIG_SOC_NSIM_VPX5)
message(FATAL_ERROR "ARC VPX targets can be built with ARC MWDT toolchain only")
endif()
else()
# MWDT compiler options
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM -arcv2em -core3 -Xdiv_rem=radix2
@ -67,6 +71,18 @@ else()
zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -Hlib=hs38_full)
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_VPX5 -arcv2hs -core4 -uarch_rev=1:4 -Xcode_density
-HL -Xatomic -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh
-Xshift_assist -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a
-Hld_cycles=1 -DDCCM_SYSTEM_BASE_CORE0=0x80000000 -Hccm
-DICCM0_SYSTEM_BASE_CORE0=0x0000000 -Xstu=4 -Xvdsp4 -Xvec_unit_rev_minor=1
-Xvec_width=512 -Xvec_mem_size=256k -Xvec_mem_bank_width=16 -Xvec_max_fetch_size=16
-Xvec_num_slots=3 -Xvec_super_with_scalar -Xvec_regs=40 -Xvec_num_rd_ports=6
-Xvec_num_acc=8 -Xvec_num_mpy=2 -Xvec_mpy32 -Xvec_num_alu=3 -Xvec_guard_bit_option=2
-Xvec_stack_check -DVEC_MEM_SYS_BASE_CORE0=0xb4000000)
zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_VPX5 -Hlib=vpx5_integer_full)
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS5X -arcv3hs -core0 -Xdual_issue -uarch_rev=0:0
-HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
-Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)

3
soc/arc/snps_nsim/Kconfig
View file

@ -40,6 +40,9 @@ config SOC_NSIM_HS_MPUV6
select CPU_HAS_MPU
select CPU_HAS_FPU
config SOC_NSIM_VPX5
bool "Synopsys ARC VPX5 in nSIM"
config SOC_NSIM_HS6X
bool "Synopsys ARC HS6x in nSIM"

1
soc/arc/snps_nsim/Kconfig.defconfig
View file

@ -15,6 +15,7 @@ source "soc/arc/snps_nsim/Kconfig.defconfig.em7d_v22"
source "soc/arc/snps_nsim/Kconfig.defconfig.sem"
source "soc/arc/snps_nsim/Kconfig.defconfig.hs"
source "soc/arc/snps_nsim/Kconfig.defconfig.hs_smp"
source "soc/arc/snps_nsim/Kconfig.defconfig.vpx5"
source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x"
source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp"
source "soc/arc/snps_nsim/Kconfig.defconfig.hs_mpuv6"

33
soc/arc/snps_nsim/Kconfig.defconfig.vpx5 Normal file
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@ -0,0 +1,33 @@
# Copyright (c) 2023 Synopsys, Inc. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
if SOC_NSIM_VPX5
config CPU_HS3X
default y
config NUM_IRQ_PRIO_LEVELS
# This processor supports 16 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
default 4
config NUM_IRQS
# must be > the highest interrupt number used
default 24
config RGF_NUM_BANKS
default 1
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 5000000
config HARVARD
default y
config ARC_FIRQ
default n
config CACHE_MANAGEMENT
default y
endif # SOC_NSIM_VPX5