drivers: pinctrl: rcar: Add r8a779f0 support
Enable PFC controller for r8a779f0 SoC. Declare pin list for r8a779f0 SoC. Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
This commit is contained in:
Aymeric Aillet
Anas Nashif
parent
1738543c5d
commit
6033db5360
3 changed files with 1142 additions and 0 deletions
536
include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h
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536
include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h
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/*
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* Copyright (c) 2023 IoT.bzh
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779F0_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779F0_H_
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#include "pinctrl-rcar-common.h"
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/* Pins declaration */
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#define PIN_NONE -1
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#define PIN_SCIF_CLK RCAR_GP_PIN(0, 0)
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#define PIN_HSCK0 RCAR_GP_PIN(0, 1)
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#define PIN_HRX0 RCAR_GP_PIN(0, 2)
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#define PIN_HTX0 RCAR_GP_PIN(0, 3)
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#define PIN_HCTS0_N RCAR_GP_PIN(0, 4)
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#define PIN_HRTS0_N RCAR_GP_PIN(0, 5)
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#define PIN_RX0 RCAR_GP_PIN(0, 6)
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#define PIN_TX0 RCAR_GP_PIN(0, 7)
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#define PIN_SCK0 RCAR_GP_PIN(0, 8)
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#define PIN_RTS0_N RCAR_GP_PIN(0, 9)
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#define PIN_CTS0_N RCAR_GP_PIN(0, 10)
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#define PIN_MSIOF0_SYNC RCAR_GP_PIN(0, 11)
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#define PIN_MSIOF0_RXD RCAR_GP_PIN(0, 12)
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#define PIN_MSIOF0_TXD RCAR_GP_PIN(0, 13)
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#define PIN_MSIOF0_SCK RCAR_GP_PIN(0, 14)
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#define PIN_MSIOF0_SS1 RCAR_GP_PIN(0, 15)
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#define PIN_MSIOF0_SS2 RCAR_GP_PIN(0, 16)
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#define PIN_IRQ0 RCAR_GP_PIN(0, 17)
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#define PIN_IRQ1 RCAR_GP_PIN(0, 18)
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#define PIN_IRQ2 RCAR_GP_PIN(0, 19)
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#define PIN_IRQ3 RCAR_GP_PIN(0, 20)
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#define PIN_GP1_00 RCAR_GP_PIN(1, 0)
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#define PIN_GP1_01 RCAR_GP_PIN(1, 1)
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#define PIN_GP1_02 RCAR_GP_PIN(1, 2)
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#define PIN_GP1_03 RCAR_GP_PIN(1, 3)
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#define PIN_GP1_04 RCAR_GP_PIN(1, 4)
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#define PIN_GP1_05 RCAR_GP_PIN(1, 5)
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#define PIN_GP1_06 RCAR_GP_PIN(1, 6)
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#define PIN_GP1_07 RCAR_GP_PIN(1, 7)
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#define PIN_GP1_08 RCAR_GP_PIN(1, 8)
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#define PIN_GP1_09 RCAR_GP_PIN(1, 9)
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#define PIN_GP1_10 RCAR_GP_PIN(1, 10)
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#define PIN_GP1_11 RCAR_GP_PIN(1, 11)
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#define PIN_MMC_SD_CLK RCAR_GP_PIN(1, 12)
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#define PIN_MMC_SD_D0 RCAR_GP_PIN(1, 13)
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#define PIN_MMC_SD_D1 RCAR_GP_PIN(1, 14)
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#define PIN_MMC_SD_D2 RCAR_GP_PIN(1, 15)
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#define PIN_MMC_SD_D3 RCAR_GP_PIN(1, 16)
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#define PIN_MMC_D5 RCAR_GP_PIN(1, 17)
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#define PIN_MMC_D4 RCAR_GP_PIN(1, 18)
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#define PIN_MMC_D6 RCAR_GP_PIN(1, 19)
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#define PIN_MMC_DS RCAR_GP_PIN(1, 20)
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#define PIN_MMC_D7 RCAR_GP_PIN(1, 21)
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#define PIN_MMC_SD_CMD RCAR_GP_PIN(1, 22)
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#define PIN_SD_CD RCAR_GP_PIN(1, 23)
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#define PIN_SD_WP RCAR_GP_PIN(1, 24)
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#define PIN_RPC_INT_N RCAR_GP_PIN(2, 0)
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#define PIN_RPC_WP_N RCAR_GP_PIN(2, 1)
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#define PIN_RPC_RESET_N RCAR_GP_PIN(2, 2)
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#define PIN_QSPI1_SSL RCAR_GP_PIN(2, 3)
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#define PIN_QSPI1_IO3 RCAR_GP_PIN(2, 4)
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#define PIN_QSPI1_MISO_IO1 RCAR_GP_PIN(2, 5)
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#define PIN_QSPI1_IO2 RCAR_GP_PIN(2, 6)
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#define PIN_QSPI1_MOSI_IO0 RCAR_GP_PIN(2, 7)
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#define PIN_QSPI1_SPCLK RCAR_GP_PIN(2, 8)
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#define PIN_QSPI0_MOSI_IO0 RCAR_GP_PIN(2, 9)
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#define PIN_QSPI0_SPCLK RCAR_GP_PIN(2, 10)
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#define PIN_QSPI0_IO2 RCAR_GP_PIN(2, 11)
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#define PIN_QSPI0_MISO_IO1 RCAR_GP_PIN(2, 12)
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#define PIN_QSPI0_SSL RCAR_GP_PIN(2, 13)
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#define PIN_QSPI0_IO3 RCAR_GP_PIN(2, 14)
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#define PIN_PCIE0_CLKREQ_N RCAR_GP_PIN(2, 15)
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#define PIN_PCIE1_CLKREQ_N RCAR_GP_PIN(2, 16)
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#define PIN_TSN1_MDIO RCAR_GP_PIN(3, 0)
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#define PIN_TSN2_MDIO RCAR_GP_PIN(3, 1)
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#define PIN_TSN0_MDIO RCAR_GP_PIN(3, 2)
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#define PIN_TSN2_MDC RCAR_GP_PIN(3, 3)
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#define PIN_TSN0_MDC RCAR_GP_PIN(3, 4)
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#define PIN_TSN1_MDC RCAR_GP_PIN(3, 5)
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#define PIN_TSN1_LINK RCAR_GP_PIN(3, 6)
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#define PIN_TSN2_LINK RCAR_GP_PIN(3, 7)
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#define PIN_TSN0_LINK RCAR_GP_PIN(3, 8)
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#define PIN_TSN2_PHY_INT RCAR_GP_PIN(3, 9)
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#define PIN_TSN0_PHY_INT RCAR_GP_PIN(3, 10)
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#define PIN_TSN1_PHY_INT RCAR_GP_PIN(3, 11)
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#define PIN_TSN0_MAGIC RCAR_GP_PIN(3, 12)
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#define PIN_TSN1_AVTP_PPS RCAR_GP_PIN(3, 13)
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#define PIN_TSN1_AVTP_MATCH RCAR_GP_PIN(3, 14)
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#define PIN_TSN1_AVTP_CAPTURE RCAR_GP_PIN(3, 15)
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#define PIN_TSN0_AVTP_PPS RCAR_GP_PIN(3, 16)
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#define PIN_TSN0_AVTP_MATCH RCAR_GP_PIN(3, 17)
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#define PIN_TSN0_AVTP_CAPTURE RCAR_GP_PIN(3, 18)
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#define PIN_GP4_00 RCAR_GP_PIN(4, 0)
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#define PIN_GP4_01 RCAR_GP_PIN(4, 1)
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#define PIN_GP4_02 RCAR_GP_PIN(4, 2)
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#define PIN_GP4_03 RCAR_GP_PIN(4, 3)
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#define PIN_GP4_04 RCAR_GP_PIN(4, 4)
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#define PIN_GP4_05 RCAR_GP_PIN(4, 5)
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#define PIN_GP4_06 RCAR_GP_PIN(4, 6)
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#define PIN_GP4_07 RCAR_GP_PIN(4, 7)
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#define PIN_GP4_08 RCAR_GP_PIN(4, 8)
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#define PIN_GP4_09 RCAR_GP_PIN(4, 9)
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#define PIN_GP4_10 RCAR_GP_PIN(4, 10)
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#define PIN_GP4_11 RCAR_GP_PIN(4, 11)
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#define PIN_GP4_12 RCAR_GP_PIN(4, 12)
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#define PIN_GP4_13 RCAR_GP_PIN(4, 13)
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#define PIN_GP4_14 RCAR_GP_PIN(4, 14)
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#define PIN_GP4_15 RCAR_GP_PIN(4, 15)
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#define PIN_GP4_16 RCAR_GP_PIN(4, 16)
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#define PIN_GP4_17 RCAR_GP_PIN(4, 17)
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#define PIN_GP4_18 RCAR_GP_PIN(4, 18)
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#define PIN_GP4_19 RCAR_GP_PIN(4, 19)
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#define PIN_MSPI0SC RCAR_GP_PIN(4, 20)
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#define PIN_MSPI0SI RCAR_GP_PIN(4, 21)
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#define PIN_MSPI0SO_MSPI0DCS RCAR_GP_PIN(4, 22)
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#define PIN_MSPI0CSS1 RCAR_GP_PIN(4, 23)
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#define PIN_MSPI0CSS0 RCAR_GP_PIN(4, 24)
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#define PIN_MSPI1SI RCAR_GP_PIN(4, 25)
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#define PIN_MSPI1SO_MSPI1DCS RCAR_GP_PIN(4, 26)
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#define PIN_MSPI1CSS0 RCAR_GP_PIN(4, 27)
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#define PIN_MSPI1SC RCAR_GP_PIN(4, 28)
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#define PIN_MSPI1CSS2 RCAR_GP_PIN(4, 29)
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#define PIN_MSPI1CSS1 RCAR_GP_PIN(4, 30)
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#define PIN_RIIC0SCL RCAR_GP_PIN(5, 0)
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#define PIN_RIIC0SDA RCAR_GP_PIN(5, 1)
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#define PIN_ETNB0MD RCAR_GP_PIN(5, 2)
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#define PIN_ETNB0WOL RCAR_GP_PIN(5, 3)
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#define PIN_ETNB0LINKSTA RCAR_GP_PIN(5, 4)
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#define PIN_ETNB0MDC RCAR_GP_PIN(5, 5)
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#define PIN_ETNB0RXER RCAR_GP_PIN(5, 6)
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#define PIN_ETNB0RXD3 RCAR_GP_PIN(5, 7)
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#define PIN_ETNB0RXD1 RCAR_GP_PIN(5, 8)
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#define PIN_ETNB0RXD2 RCAR_GP_PIN(5, 9)
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#define PIN_ETNB0RXDV RCAR_GP_PIN(5, 10)
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#define PIN_ETNB0RXD0 RCAR_GP_PIN(5, 11)
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#define PIN_ETNB0RXCLK RCAR_GP_PIN(5, 12)
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#define PIN_ETNB0TXER RCAR_GP_PIN(5, 13)
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#define PIN_ETNB0TXD3 RCAR_GP_PIN(5, 14)
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#define PIN_ETNB0TXCLK RCAR_GP_PIN(5, 15)
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#define PIN_ETNB0TXD1 RCAR_GP_PIN(5, 16)
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#define PIN_ETNB0TXD2 RCAR_GP_PIN(5, 17)
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#define PIN_ETNB0TXEN RCAR_GP_PIN(5, 18)
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#define PIN_ETNB0TXD0 RCAR_GP_PIN(5, 19)
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#define PIN_RLIN37TX RCAR_GP_PIN(6, 0)
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#define PIN_RLIN37RX_INTP23 RCAR_GP_PIN(6, 1)
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#define PIN_RLIN36TX RCAR_GP_PIN(6, 2)
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#define PIN_RLIN36RX_INTP22 RCAR_GP_PIN(6, 3)
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#define PIN_RLIN35TX RCAR_GP_PIN(6, 4)
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#define PIN_RLIN35RX_INTP21 RCAR_GP_PIN(6, 5)
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#define PIN_RLIN34TX RCAR_GP_PIN(6, 6)
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#define PIN_RLIN34RX_INTP20 RCAR_GP_PIN(6, 7)
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#define PIN_RLIN33TX RCAR_GP_PIN(6, 8)
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#define PIN_RLIN33RX_INTP19 RCAR_GP_PIN(6, 9)
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#define PIN_RLIN32TX RCAR_GP_PIN(6, 10)
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#define PIN_RLIN32RX_INTP18 RCAR_GP_PIN(6, 11)
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#define PIN_RLIN31TX RCAR_GP_PIN(6, 12)
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#define PIN_RLIN31RX_INTP17 RCAR_GP_PIN(6, 13)
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#define PIN_RLIN30TX RCAR_GP_PIN(6, 14)
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#define PIN_RLIN30RX_INTP16 RCAR_GP_PIN(6, 15)
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#define PIN_INTP37 RCAR_GP_PIN(6, 16)
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#define PIN_INTP36 RCAR_GP_PIN(6, 17)
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#define PIN_INTP35 RCAR_GP_PIN(6, 18)
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#define PIN_INTP34 RCAR_GP_PIN(6, 19)
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#define PIN_INTP33 RCAR_GP_PIN(6, 20)
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#define PIN_INTP32 RCAR_GP_PIN(6, 21)
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#define PIN_NMI1 RCAR_GP_PIN(6, 22)
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#define PIN_PRESETOUT1_N RCAR_GP_PIN(6, 31)
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#define PIN_CAN0TX RCAR_GP_PIN(7, 0)
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#define PIN_CAN0RX_INTP0 RCAR_GP_PIN(7, 1)
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#define PIN_CAN1TX RCAR_GP_PIN(7, 2)
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#define PIN_CAN1RX_INTP1 RCAR_GP_PIN(7, 3)
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#define PIN_CAN2TX RCAR_GP_PIN(7, 4)
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#define PIN_CAN2RX_INTP2 RCAR_GP_PIN(7, 5)
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#define PIN_CAN3TX RCAR_GP_PIN(7, 6)
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#define PIN_CAN3RX_INTP3 RCAR_GP_PIN(7, 7)
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#define PIN_CAN4TX RCAR_GP_PIN(7, 8)
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#define PIN_CAN4RX_INTP4 RCAR_GP_PIN(7, 9)
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#define PIN_CAN5TX RCAR_GP_PIN(7, 10)
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#define PIN_CAN5RX_INTP5 RCAR_GP_PIN(7, 11)
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#define PIN_CAN6TX RCAR_GP_PIN(7, 12)
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#define PIN_CAN6RX_INTP6 RCAR_GP_PIN(7, 13)
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#define PIN_CAN7TX RCAR_GP_PIN(7, 14)
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#define PIN_CAN7RX_INTP7 RCAR_GP_PIN(7, 15)
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#define PIN_CAN8TX RCAR_GP_PIN(7, 16)
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#define PIN_CAN8RX_INTP8 RCAR_GP_PIN(7, 17)
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#define PIN_CAN9TX RCAR_GP_PIN(7, 18)
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#define PIN_CAN9RX_INTP9 RCAR_GP_PIN(7, 19)
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#define PIN_CAN10TX RCAR_GP_PIN(7, 20)
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#define PIN_CAN10RX_INTP10 RCAR_GP_PIN(7, 21)
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#define PIN_CAN11TX RCAR_GP_PIN(7, 22)
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#define PIN_CAN11RX_INTP11 RCAR_GP_PIN(7, 23)
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#define PIN_CAN12TX RCAR_GP_PIN(7, 24)
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#define PIN_CAN12RX_INTP12 RCAR_GP_PIN(7, 25)
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#define PIN_CAN13TX RCAR_GP_PIN(7, 26)
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#define PIN_CAN13RX_INTP13 RCAR_GP_PIN(7, 27)
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#define PIN_CAN14TX RCAR_GP_PIN(7, 28)
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#define PIN_CAN14RX_INTP14 RCAR_GP_PIN(7, 29)
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#define PIN_CAN15TX RCAR_GP_PIN(7, 30)
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#define PIN_CAN15RX_INTP15 RCAR_GP_PIN(7, 31)
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/* Pinmux function declarations */
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#define FUNC_SCIF_CLK IP0SR0(0, 0)
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#define FUNC_HSCK0 IP0SR0(4, 0)
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#define FUNC_SCK3 IP0SR0(4, 1)
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#define FUNC_MSIOF3_SCK IP0SR0(4, 2)
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#define FUNC_TSN0_AVTP_CAPTURE_A IP0SR0(4, 5)
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#define FUNC_HRX0 IP0SR0(8, 0)
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#define FUNC_RX3 IP0SR0(8, 1)
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#define FUNC_MSIOF3_RXD IP0SR0(8, 2)
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#define FUNC_TSN0_AVTP_MATCH_A IP0SR0(8, 5)
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#define FUNC_HTX0 IP0SR0(12, 0)
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#define FUNC_TX3 IP0SR0(12, 1)
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#define FUNC_MSIOF3_TXD IP0SR0(12, 2)
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#define FUNC_HCTS0_N IP0SR0(16, 0)
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#define FUNC_CTS3_N IP0SR0(16, 1)
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#define FUNC_MSIOF3_SS1 IP0SR0(16, 2)
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#define FUNC_TSN0_MDC_A IP0SR0(16, 5)
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#define FUNC_HRTS0_N IP0SR0(20, 0)
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#define FUNC_RTS3_N IP0SR0(20, 1)
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#define FUNC_MSIOF3_SS2 IP0SR0(20, 2)
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#define FUNC_TSN0_MDIO_A IP0SR0(20, 5)
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#define FUNC_RX0 IP0SR0(24, 0)
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#define FUNC_HRX1 IP0SR0(24, 1)
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#define FUNC_MSIOF1_RXD IP0SR0(24, 3)
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#define FUNC_TSN1_AVTP_MATCH_A IP0SR0(24, 5)
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#define FUNC_TX0 IP0SR0(28, 0)
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#define FUNC_HTX1 IP0SR0(28, 1)
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#define FUNC_MSIOF1_TXD IP0SR0(28, 3)
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#define FUNC_TSN1_AVTP_CAPTURE_A IP0SR0(28, 5)
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#define FUNC_SCK0 IP1SR0(0, 0)
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#define FUNC_HSCK1 IP1SR0(0, 1)
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#define FUNC_MSIOF1_SCK IP1SR0(0, 3)
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#define FUNC_RTS0_N IP1SR0(4, 0)
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#define FUNC_HRTS1_N IP1SR0(4, 1)
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#define FUNC_MSIOF3_SYNC IP1SR0(4, 2)
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#define FUNC_TSN1_MDIO_A IP1SR0(4, 5)
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#define FUNC_CTS0_N IP1SR0(8, 0)
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#define FUNC_HCTS1_N IP1SR0(8, 1)
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#define FUNC_MSIOF1_SYNC IP1SR0(8, 3)
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#define FUNC_TSN1_MDC_A IP1SR0(8, 5)
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#define FUNC_MSIOF0_SYNC IP1SR0(12, 0)
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#define FUNC_HCTS3_N IP1SR0(12, 1)
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#define FUNC_CTS1_N IP1SR0(12, 2)
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#define FUNC_IRQ4 IP1SR0(12, 3)
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#define FUNC_TSN0_LINK_A IP1SR0(12, 5)
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#define FUNC_MSIOF0_RXD IP1SR0(16, 0)
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#define FUNC_HRX3 IP1SR0(16, 1)
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#define FUNC_RX1 IP1SR0(16, 2)
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#define FUNC_MSIOF0_TXD IP1SR0(20, 0)
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#define FUNC_HTX3 IP1SR0(20, 1)
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#define FUNC_TX1 IP1SR0(20, 2)
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#define FUNC_MSIOF0_SCK IP1SR0(24, 0)
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#define FUNC_HSCK3 IP1SR0(24, 1)
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#define FUNC_SCK1 IP1SR0(24, 2)
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#define FUNC_MSIOF0_SS1 IP1SR0(28, 0)
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#define FUNC_HRTS3_N IP1SR0(28, 1)
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#define FUNC_RTS1_N IP1SR0(28, 2)
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#define FUNC_IRQ5 IP1SR0(28, 3)
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#define FUNC_TSN1_LINK_A IP1SR0(28, 5)
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#define FUNC_MSIOF0_SS2 IP2SR0(0, 0)
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#define FUNC_TSN2_LINK_A IP2SR0(0, 5)
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#define FUNC_IRQ0 IP2SR0(4, 0)
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#define FUNC_MSIOF1_SS1 IP2SR0(4, 3)
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#define FUNC_TSN0_MAGIC_A IP2SR0(4, 5)
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#define FUNC_IRQ1 IP2SR0(8, 0)
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#define FUNC_MSIOF1_SS2 IP2SR0(8, 3)
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#define FUNC_TSN0_PHY_INT_A IP2SR0(8, 5)
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#define FUNC_IRQ2 IP2SR0(12, 0)
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#define FUNC_TSN1_PHY_INT_A IP2SR0(12, 5)
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#define FUNC_IRQ3 IP2SR0(16, 0)
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#define FUNC_TSN2_PHY_INT_A IP2SR0(16, 5)
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#define FUNC_GP1_00 IP0SR1(0, 0)
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#define FUNC_TCLK1 IP0SR1(0, 1)
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#define FUNC_HSCK2 IP0SR1(0, 2)
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#define FUNC_GP1_01 IP0SR1(4, 0)
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#define FUNC_TCLK4 IP0SR1(4, 1)
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#define FUNC_HRX2 IP0SR1(4, 2)
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#define FUNC_GP1_02 IP0SR1(8, 0)
|
||||
#define FUNC_HTX2 IP0SR1(8, 2)
|
||||
#define FUNC_MSIOF2_SS1 IP0SR1(8, 3)
|
||||
#define FUNC_TSN2_MDC_A IP0SR1(8, 5)
|
||||
#define FUNC_GP1_03 IP0SR1(12, 0)
|
||||
#define FUNC_TCLK2 IP0SR1(12, 1)
|
||||
#define FUNC_HCTS2_N IP0SR1(12, 2)
|
||||
#define FUNC_MSIOF2_SS2 IP0SR1(12, 3)
|
||||
#define FUNC_CTS4_N IP0SR1(12, 4)
|
||||
#define FUNC_TSN2_MDIO_A IP0SR1(12, 5)
|
||||
#define FUNC_GP1_04 IP0SR1(16, 0)
|
||||
#define FUNC_TCLK3 IP0SR1(16, 1)
|
||||
#define FUNC_HRTS2_N IP0SR1(16, 2)
|
||||
#define FUNC_MSIOF2_SYNC IP0SR1(16, 3)
|
||||
#define FUNC_RTS4_N IP0SR1(16, 4)
|
||||
#define FUNC_GP1_05 IP0SR1(20, 0)
|
||||
#define FUNC_MSIOF2_SCK IP0SR1(20, 1)
|
||||
#define FUNC_SCK4 IP0SR1(20, 2)
|
||||
#define FUNC_GP1_06 IP0SR1(24, 0)
|
||||
#define FUNC_MSIOF2_RXD IP0SR1(24, 1)
|
||||
#define FUNC_RX4 IP0SR1(24, 2)
|
||||
#define FUNC_GP1_07 IP0SR1(28, 0)
|
||||
#define FUNC_MSIOF2_TXD IP0SR1(28, 1)
|
||||
#define FUNC_TX4 IP0SR1(28, 2)
|
||||
#define FUNC_GP4_00 IP0SR4(0, 0)
|
||||
#define FUNC_MSPI4SC IP0SR4(0, 1)
|
||||
#define FUNC_TAUD0I2 IP0SR4(0, 3)
|
||||
#define FUNC_TAUD0O2 IP0SR4(0, 4)
|
||||
#define FUNC_GP4_01 IP0SR4(4, 0)
|
||||
#define FUNC_MSPI4SI IP0SR4(4, 1)
|
||||
#define FUNC_TAUD0I4 IP0SR4(4, 3)
|
||||
#define FUNC_TAUD0O4 IP0SR4(4, 4)
|
||||
#define FUNC_GP4_02 IP0SR4(8, 0)
|
||||
#define FUNC_MSPI4SO_MSPI4DCS IP0SR4(8, 1)
|
||||
#define FUNC_TAUD0I3 IP0SR4(8, 3)
|
||||
#define FUNC_TAUD0O3 IP0SR4(8, 4)
|
||||
#define FUNC_GP4_03 IP0SR4(12, 0)
|
||||
#define FUNC_MSPI4CSS1 IP0SR4(12, 1)
|
||||
#define FUNC_TAUD0I6 IP0SR4(12, 3)
|
||||
#define FUNC_TAUD0O6 IP0SR4(12, 4)
|
||||
#define FUNC_GP4_04 IP0SR4(16, 0)
|
||||
#define FUNC_MSPI4CSS0 IP0SR4(16, 1)
|
||||
#define FUNC_MSPI4SSI_N IP0SR4(16, 2)
|
||||
#define FUNC_TAUD0I5 IP0SR4(16, 3)
|
||||
#define FUNC_TAUD0O5 IP0SR4(16, 4)
|
||||
#define FUNC_GP4_05 IP0SR4(20, 0)
|
||||
#define FUNC_MSPI4CSS3 IP0SR4(20, 1)
|
||||
#define FUNC_TAUD0I8 IP0SR4(20, 3)
|
||||
#define FUNC_TAUD0O8 IP0SR4(20, 4)
|
||||
#define FUNC_GP4_06 IP0SR4(24, 0)
|
||||
#define FUNC_MSPI4CSS2 IP0SR4(24, 1)
|
||||
#define FUNC_TAUD0I7 IP0SR4(24, 3)
|
||||
#define FUNC_TAUD0O7 IP0SR4(24, 4)
|
||||
#define FUNC_GP4_07 IP0SR4(28, 0)
|
||||
#define FUNC_MSPI4CSS5 IP0SR4(28, 1)
|
||||
#define FUNC_TAUD0I10 IP0SR4(28, 3)
|
||||
#define FUNC_TAUD0O10 IP0SR4(28, 4)
|
||||
#define FUNC_GP4_08 IP1SR4(0, 0)
|
||||
#define FUNC_MSPI4CSS4 IP1SR4(0, 1)
|
||||
#define FUNC_TAUD0I9 IP1SR4(0, 3)
|
||||
#define FUNC_TAUD0O9 IP1SR4(0, 4)
|
||||
#define FUNC_GP4_09 IP1SR4(4, 0)
|
||||
#define FUNC_MSPI4CSS7 IP1SR4(4, 1)
|
||||
#define FUNC_TAUD0I12 IP1SR4(4, 3)
|
||||
#define FUNC_TAUD0O12 IP1SR4(4, 4)
|
||||
#define FUNC_GP4_10 IP1SR4(8, 0)
|
||||
#define FUNC_MSPI4CSS6 IP1SR4(8, 1)
|
||||
#define FUNC_TAUD0I11 IP1SR4(8, 3)
|
||||
#define FUNC_TAUD0O11 IP1SR4(8, 4)
|
||||
#define FUNC_GP4_11 IP1SR4(12, 0)
|
||||
#define FUNC_ERRORIN0_N IP1SR4(12, 1)
|
||||
#define FUNC_TAUD0I14 IP1SR4(12, 3)
|
||||
#define FUNC_TAUD0O14 IP1SR4(12, 4)
|
||||
#define FUNC_GP4_12 IP1SR4(16, 0)
|
||||
#define FUNC_ERROROUT_C_N IP1SR4(16, 1)
|
||||
#define FUNC_TAUD0I13 IP1SR4(16, 3)
|
||||
#define FUNC_TAUD0O13 IP1SR4(16, 4)
|
||||
#define FUNC_GP4_13 IP1SR4(20, 0)
|
||||
#define FUNC_GP4_14 IP1SR4(24, 0)
|
||||
#define FUNC_ERRORIN1_N IP1SR4(24, 1)
|
||||
#define FUNC_TAUD0I15 IP1SR4(24, 3)
|
||||
#define FUNC_TAUD0O15 IP1SR4(24, 4)
|
||||
#define FUNC_GP4_15 IP1SR4(28, 0)
|
||||
#define FUNC_MSPI1CSS3 IP1SR4(28, 1)
|
||||
#define FUNC_TAUD1I1 IP1SR4(28, 3)
|
||||
#define FUNC_TAUD1O1 IP1SR4(28, 4)
|
||||
#define FUNC_GP4_16 IP2SR4(0, 0)
|
||||
#define FUNC_TAUD1I0 IP2SR4(0, 3)
|
||||
#define FUNC_TAUD1O0 IP2SR4(0, 4)
|
||||
#define FUNC_GP4_17 IP2SR4(4, 0)
|
||||
#define FUNC_MSPI1CSS5 IP2SR4(4, 1)
|
||||
#define FUNC_TAUD1I3 IP2SR4(4, 3)
|
||||
#define FUNC_TAUD1O3 IP2SR4(4, 4)
|
||||
#define FUNC_GP4_18 IP2SR4(8, 0)
|
||||
#define FUNC_MSPI1CSS4 IP2SR4(8, 1)
|
||||
#define FUNC_TAUD1I2 IP2SR4(8, 3)
|
||||
#define FUNC_TAUD1O2 IP2SR4(8, 4)
|
||||
#define FUNC_GP4_19 IP2SR4(12, 0)
|
||||
#define FUNC_MSPI1CSS6 IP2SR4(12, 1)
|
||||
#define FUNC_TAUD1I4 IP2SR4(12, 3)
|
||||
#define FUNC_TAUD1O4 IP2SR4(12, 4)
|
||||
#define FUNC_MSPI0SC IP2SR4(16, 0)
|
||||
#define FUNC_MSPI1CSS7 IP2SR4(16, 1)
|
||||
#define FUNC_TAUD1I5 IP2SR4(16, 3)
|
||||
#define FUNC_TAUD1O5 IP2SR4(16, 4)
|
||||
#define FUNC_MSPI0SI IP2SR4(20, 0)
|
||||
#define FUNC_TAUD1I7 IP2SR4(20, 3)
|
||||
#define FUNC_TAUD1O7 IP2SR4(20, 4)
|
||||
#define FUNC_MSPI0SO_MSPI0DCS IP2SR4(24, 0)
|
||||
#define FUNC_TAUD1I6 IP2SR4(24, 3)
|
||||
#define FUNC_TAUD1O6 IP2SR4(24, 4)
|
||||
#define FUNC_MSPI0CSS1 IP2SR4(28, 0)
|
||||
#define FUNC_TAUD1I9 IP2SR4(28, 3)
|
||||
#define FUNC_TAUD1O9 IP2SR4(28, 4)
|
||||
#define FUNC_MSPI0CSS0 IP3SR4(0, 0)
|
||||
#define FUNC_MSPI0SSI_N IP3SR4(0, 1)
|
||||
#define FUNC_TAUD1I8 IP3SR4(0, 3)
|
||||
#define FUNC_TAUD1O8 IP3SR4(0, 4)
|
||||
#define FUNC_MSPI1SO_MSPI1DCS IP3SR4(8, 0)
|
||||
#define FUNC_MSPI0CSS3 IP3SR4(8, 2)
|
||||
#define FUNC_TAUD1I11 IP3SR4(8, 3)
|
||||
#define FUNC_TAUD1O11 IP3SR4(8, 4)
|
||||
#define FUNC_MSPI1SC IP3SR4(16, 0)
|
||||
#define FUNC_MSPI0CSS2 IP3SR4(16, 2)
|
||||
#define FUNC_TAUD1I10 IP3SR4(16, 3)
|
||||
#define FUNC_TAUD1O10 IP3SR4(16, 4)
|
||||
#define FUNC_RIIC0SCL IP0SR5(0, 0)
|
||||
#define FUNC_TAUD0I0 IP0SR5(0, 3)
|
||||
#define FUNC_TAUD0O0 IP0SR5(0, 4)
|
||||
#define FUNC_RIIC0SDA IP0SR5(4, 0)
|
||||
#define FUNC_TAUD0I1 IP0SR5(4, 3)
|
||||
#define FUNC_TAUD0O1 IP0SR5(4, 4)
|
||||
#define FUNC_ETNB0MD IP0SR5(8, 0)
|
||||
#define FUNC_ETNB0WOL IP0SR5(12, 0)
|
||||
#define FUNC_ETNB0LINKSTA IP0SR5(16, 0)
|
||||
#define FUNC_ETNB0MDC IP0SR5(20, 0)
|
||||
#define FUNC_ETNB0RXCLK IP0SR5(24, 0)
|
||||
#define FUNC_ETNB0CRS_DV IP0SR5(24, 1)
|
||||
#define FUNC_ETNB0TXCLK IP0SR5(28, 0)
|
||||
#define FUNC_ETNB0REFCLK IP0SR5(28, 1)
|
||||
#define FUNC_RLIN33TX IP1SR6(0, 0)
|
||||
#define FUNC_TAUJ3O3 IP1SR6(0, 3)
|
||||
#define FUNC_TAUJ3I3 IP1SR6(0, 4)
|
||||
#define FUNC_NMI1 IP1SR6(0, 5)
|
||||
#define FUNC_RLIN33RX_INTP19 IP1SR6(4, 0)
|
||||
#define FUNC_TAUJ3O2 IP1SR6(4, 3)
|
||||
#define FUNC_TAUJ3I2 IP1SR6(4, 4)
|
||||
#define FUNC_RLIN32TX IP1SR6(8, 0)
|
||||
#define FUNC_TAUJ3O1 IP1SR6(8, 3)
|
||||
#define FUNC_TAUJ3I1 IP1SR6(8, 4)
|
||||
#define FUNC_RLIN32RX_INTP18 IP1SR6(12, 0)
|
||||
#define FUNC_TAUJ3O0 IP1SR6(12, 3)
|
||||
#define FUNC_TAUJ3I0 IP1SR6(12, 4)
|
||||
#define FUNC_INTP35 IP1SR6(12, 5)
|
||||
#define FUNC_RLIN31TX IP1SR6(16, 0)
|
||||
#define FUNC_TAUJ1I3 IP1SR6(16, 3)
|
||||
#define FUNC_TAUJ1O3 IP1SR6(16, 4)
|
||||
#define FUNC_INTP34 IP1SR6(16, 5)
|
||||
#define FUNC_RLIN31RX_INTP17 IP1SR6(20, 0)
|
||||
#define FUNC_TAUJ1I2 IP1SR6(20, 3)
|
||||
#define FUNC_TAUJ1O2 IP1SR6(20, 4)
|
||||
#define FUNC_INTP33 IP1SR6(20, 5)
|
||||
#define FUNC_RLIN30TX IP1SR6(24, 0)
|
||||
#define FUNC_TAUJ1I1 IP1SR6(24, 3)
|
||||
#define FUNC_TAUJ1O1 IP1SR6(24, 4)
|
||||
#define FUNC_RLIN30RX_INTP16 IP1SR6(28, 0)
|
||||
#define FUNC_TAUJ1I0 IP1SR6(28, 3)
|
||||
#define FUNC_TAUJ1O0 IP1SR6(28, 4)
|
||||
#define FUNC_FLXA0STPWT IP2SR6(8, 2)
|
||||
#define FUNC_CAN0TX IP0SR7(0, 0)
|
||||
#define FUNC_RSENT0SPCO IP0SR7(0, 1)
|
||||
#define FUNC_MSPI2SO_MSPI2DCS IP0SR7(0, 3)
|
||||
#define FUNC_CAN0RX_INTP0 IP0SR7(4, 0)
|
||||
#define FUNC_RSENT0RX IP0SR7(4, 1)
|
||||
#define FUNC_RSENT0RX_RSENT0SPCO IP0SR7(4, 2)
|
||||
#define FUNC_MSPI2SC IP0SR7(4, 3)
|
||||
#define FUNC_CAN1TX IP0SR7(8, 0)
|
||||
#define FUNC_RSENT1SPCO IP0SR7(8, 1)
|
||||
#define FUNC_MSPI2SSI_N IP0SR7(8, 3)
|
||||
#define FUNC_MSPI2CSS0 IP0SR7(8, 4)
|
||||
#define FUNC_CAN1RX_INTP1 IP0SR7(12, 0)
|
||||
#define FUNC_RSENT1RX IP0SR7(12, 1)
|
||||
#define FUNC_RSENT1RX_RSENT1SPCO IP0SR7(12, 2)
|
||||
#define FUNC_MSPI2SI IP0SR7(12, 3)
|
||||
#define FUNC_CAN2TX IP0SR7(16, 0)
|
||||
#define FUNC_RSENT2SPCO IP0SR7(16, 1)
|
||||
#define FUNC_MSPI2CSS2 IP0SR7(16, 4)
|
||||
#define FUNC_CAN2RX_INTP2 IP0SR7(20, 0)
|
||||
#define FUNC_RSENT2RX IP0SR7(20, 1)
|
||||
#define FUNC_RSENT2RX_RSENT2SPCO IP0SR7(20, 2)
|
||||
#define FUNC_MSPI2CSS1 IP0SR7(20, 4)
|
||||
#define FUNC_CAN3TX IP0SR7(24, 0)
|
||||
#define FUNC_RSENT3SPCO IP0SR7(24, 1)
|
||||
#define FUNC_MSPI2CSS4 IP0SR7(24, 4)
|
||||
#define FUNC_CAN3RX_INTP3 IP0SR7(28, 0)
|
||||
#define FUNC_RSENT3RX IP0SR7(28, 1)
|
||||
#define FUNC_RSENT3RX_RSENT3SPCO IP0SR7(28, 2)
|
||||
#define FUNC_MSPI2CSS3 IP0SR7(28, 4)
|
||||
#define FUNC_CAN4TX IP1SR7(0, 0)
|
||||
#define FUNC_RSENT4SPCO IP1SR7(0, 1)
|
||||
#define FUNC_MSPI2CSS6 IP1SR7(0, 4)
|
||||
#define FUNC_CAN4RX_INTP4 IP1SR7(4, 0)
|
||||
#define FUNC_RSENT4RX IP1SR7(4, 1)
|
||||
#define FUNC_RSENT4RX_RSENT4SPCO IP1SR7(4, 2)
|
||||
#define FUNC_MSPI2CSS5 IP1SR7(4, 4)
|
||||
#define FUNC_CAN5TX IP1SR7(8, 0)
|
||||
#define FUNC_RSENT5SPCO IP1SR7(8, 1)
|
||||
#define FUNC_CAN5RX_INTP5 IP1SR7(12, 0)
|
||||
#define FUNC_RSENT5RX IP1SR7(12, 1)
|
||||
#define FUNC_RSENT5RX_RSENT5SPCO IP1SR7(12, 2)
|
||||
#define FUNC_MSPI2CSS7 IP1SR7(12, 4)
|
||||
#define FUNC_CAN6TX IP1SR7(16, 0)
|
||||
#define FUNC_RSENT6SPCO IP1SR7(16, 1)
|
||||
#define FUNC_MSPI3SO_MSPI3DCS IP1SR7(16, 3)
|
||||
#define FUNC_CAN6RX_INTP6 IP1SR7(20, 0)
|
||||
#define FUNC_RSENT6RX IP1SR7(20, 1)
|
||||
#define FUNC_RSENT6RX_RSENT6SPCO IP1SR7(20, 2)
|
||||
#define FUNC_MSPI3SC IP1SR7(20, 3)
|
||||
#define FUNC_CAN7TX IP1SR7(24, 0)
|
||||
#define FUNC_RSENT7SPCO IP1SR7(24, 1)
|
||||
#define FUNC_MSPI3SSI_N IP1SR7(24, 3)
|
||||
#define FUNC_CAN7RX_INTP7 IP1SR7(28, 0)
|
||||
#define FUNC_RSENT7RX IP1SR7(28, 1)
|
||||
#define FUNC_RSENT7RX_RSENT7SPCO IP1SR7(28, 2)
|
||||
#define FUNC_MSPI3SI IP1SR7(28, 3)
|
||||
#define FUNC_CAN8TX IP2SR7(0, 0)
|
||||
#define FUNC_RLIN38TX IP2SR7(0, 1)
|
||||
#define FUNC_MSPI3CSS1 IP2SR7(0, 3)
|
||||
#define FUNC_CAN8RX_INTP8 IP2SR7(4, 0)
|
||||
#define FUNC_RLIN38RX_INTP24 IP2SR7(4, 1)
|
||||
#define FUNC_MSPI3CSS0 IP2SR7(4, 3)
|
||||
#define FUNC_CAN9TX IP2SR7(8, 0)
|
||||
#define FUNC_RLIN39TX IP2SR7(8, 1)
|
||||
#define FUNC_MSPI3CSS3 IP2SR7(8, 3)
|
||||
#define FUNC_CAN9RX_INTP9 IP2SR7(12, 0)
|
||||
#define FUNC_RLIN39RX_INTP25 IP2SR7(12, 1)
|
||||
#define FUNC_MSPI3CSS2 IP2SR7(12, 3)
|
||||
#define FUNC_CAN10TX IP2SR7(16, 0)
|
||||
#define FUNC_RLIN310TX IP2SR7(16, 1)
|
||||
#define FUNC_MSPI3CSS5 IP2SR7(16, 3)
|
||||
#define FUNC_CAN10RX_INTP10 IP2SR7(20, 0)
|
||||
#define FUNC_RLIN310RX_INTP26 IP2SR7(20, 1)
|
||||
#define FUNC_MSPI3CSS4 IP2SR7(20, 3)
|
||||
#define FUNC_CAN11TX IP2SR7(24, 0)
|
||||
#define FUNC_RLIN311TX IP2SR7(24, 1)
|
||||
#define FUNC_MSPI3CSS7 IP2SR7(24, 3)
|
||||
#define FUNC_CAN11RX_INTP11 IP2SR7(28, 0)
|
||||
#define FUNC_RLIN311RX_INTP27 IP2SR7(28, 1)
|
||||
#define FUNC_MSPI3CSS6 IP2SR7(28, 3)
|
||||
#define FUNC_FLXA0RXDB IP3SR7(8, 2)
|
||||
#define FUNC_FLXA0RXDA IP3SR7(12, 2)
|
||||
#define FUNC_FLXA0TXDB IP3SR7(16, 2)
|
||||
#define FUNC_FLXA0TXDA IP3SR7(20, 2)
|
||||
#define FUNC_FLXA0TXENB IP3SR7(24, 2)
|
||||
#define FUNC_FLXA0TXENA IP3SR7(28, 2)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779F0_H_ */
|
||||
|
|
@ -1,2 +1,4 @@
|
|||
# Copyright (c) 2023 IoT.bzh
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c)
|
||||
|
|
|
|||
604
soc/arm/renesas_rcar/gen4/pfc_r8a779f0.c
Normal file
604
soc/arm/renesas_rcar/gen4/pfc_r8a779f0.c
Normal file
|
|
@ -0,0 +1,604 @@
|
|||
/*
|
||||
* Copyright (c) 2023 IoT.bzh
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include "pinctrl_soc.h"
|
||||
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h>
|
||||
|
||||
const struct pfc_drive_reg pfc_drive_regs[] = {
|
||||
/* DRV0CTRL0 */
|
||||
{ 0x80, {
|
||||
{ RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
|
||||
{ RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
|
||||
{ RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */
|
||||
{ RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */
|
||||
{ RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */
|
||||
{ RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */
|
||||
{ RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */
|
||||
{ RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */
|
||||
} },
|
||||
/* DRV1CTRL0 */
|
||||
{ 0x84, {
|
||||
{ RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
|
||||
{ RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */
|
||||
{ RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */
|
||||
{ RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */
|
||||
{ RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */
|
||||
{ RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */
|
||||
{ RCAR_GP_PIN(0, 9), 4, 3 }, /* RTS0_N */
|
||||
{ RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */
|
||||
} },
|
||||
/* DRV2CTRL0 */
|
||||
{ 0x88, {
|
||||
{ RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */
|
||||
{ RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */
|
||||
{ RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */
|
||||
{ RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */
|
||||
{ RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */
|
||||
} },
|
||||
/* DRV3CTRL0 is empty */
|
||||
/* DRV0CTRL1 */
|
||||
{ 0x80, {
|
||||
{ RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */
|
||||
{ RCAR_GP_PIN(1, 6), 24, 3 }, /* GP1_06 */
|
||||
{ RCAR_GP_PIN(1, 5), 20, 3 }, /* GP1_05 */
|
||||
{ RCAR_GP_PIN(1, 4), 16, 3 }, /* GP1_04 */
|
||||
{ RCAR_GP_PIN(1, 3), 12, 3 }, /* GP1_03 */
|
||||
{ RCAR_GP_PIN(1, 2), 8, 3 }, /* GP1_02 */
|
||||
{ RCAR_GP_PIN(1, 1), 4, 3 }, /* GP1_01 */
|
||||
{ RCAR_GP_PIN(1, 0), 0, 3 }, /* GP1_00 */
|
||||
} },
|
||||
/* DRV1CTRL1 */
|
||||
{ 0x84, {
|
||||
{ RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */
|
||||
{ RCAR_GP_PIN(1, 14), 24, 3 }, /* MMC_SD_D1 */
|
||||
{ RCAR_GP_PIN(1, 13), 20, 3 }, /* MMC_SD_D0 */
|
||||
{ RCAR_GP_PIN(1, 12), 16, 3 }, /* MMC_SD_CLK */
|
||||
{ RCAR_GP_PIN(1, 11), 12, 3 }, /* GP1_11 */
|
||||
{ RCAR_GP_PIN(1, 10), 8, 3 }, /* GP1_10 */
|
||||
{ RCAR_GP_PIN(1, 9), 4, 3 }, /* GP1_09 */
|
||||
{ RCAR_GP_PIN(1, 8), 0, 3 }, /* GP1_08 */
|
||||
} },
|
||||
/* DRV2CTRL1 */
|
||||
{ 0x88, {
|
||||
{ RCAR_GP_PIN(1, 23), 28, 3 }, /* SD_CD */
|
||||
{ RCAR_GP_PIN(1, 22), 24, 3 }, /* MMC_SD_CMD */
|
||||
{ RCAR_GP_PIN(1, 21), 20, 3 }, /* MMC_D7 */
|
||||
{ RCAR_GP_PIN(1, 20), 16, 3 }, /* MMC_DS */
|
||||
{ RCAR_GP_PIN(1, 19), 12, 3 }, /* MMC_D6 */
|
||||
{ RCAR_GP_PIN(1, 18), 8, 3 }, /* MMC_D4 */
|
||||
{ RCAR_GP_PIN(1, 17), 4, 3 }, /* MMC_D5 */
|
||||
{ RCAR_GP_PIN(1, 16), 0, 3 }, /* MMC_SD_D3 */
|
||||
} },
|
||||
/* DRV3CTRL1 */
|
||||
{ 0x8c, {
|
||||
{ RCAR_GP_PIN(1, 24), 0, 3 }, /* SD_WP */
|
||||
} },
|
||||
/* DRV0CTRL2 */
|
||||
{ 0x80, {
|
||||
{ RCAR_GP_PIN(2, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
|
||||
{ RCAR_GP_PIN(2, 6), 24, 2 }, /* QSPI1_IO2 */
|
||||
{ RCAR_GP_PIN(2, 5), 20, 2 }, /* QSPI1_MISO_IO1 */
|
||||
{ RCAR_GP_PIN(2, 4), 16, 2 }, /* QSPI1_IO3 */
|
||||
{ RCAR_GP_PIN(2, 3), 12, 2 }, /* QSPI1_SSL */
|
||||
{ RCAR_GP_PIN(2, 2), 8, 2 }, /* RPC_RESET_N */
|
||||
{ RCAR_GP_PIN(2, 1), 4, 2 }, /* RPC_WP_N */
|
||||
{ RCAR_GP_PIN(2, 0), 0, 2 }, /* RPC_INT_N */
|
||||
} },
|
||||
/* DRV1CTRL2 */
|
||||
{ 0x84, {
|
||||
{ RCAR_GP_PIN(2, 15), 28, 3 }, /* PCIE0_CLKREQ_N */
|
||||
{ RCAR_GP_PIN(2, 14), 24, 2 }, /* QSPI0_IO3 */
|
||||
{ RCAR_GP_PIN(2, 13), 20, 2 }, /* QSPI0_SSL */
|
||||
{ RCAR_GP_PIN(2, 12), 16, 2 }, /* QSPI0_MISO_IO1 */
|
||||
{ RCAR_GP_PIN(2, 11), 12, 2 }, /* QSPI0_IO2 */
|
||||
{ RCAR_GP_PIN(2, 10), 8, 2 }, /* QSPI0_SPCLK */
|
||||
{ RCAR_GP_PIN(2, 9), 4, 2 }, /* QSPI0_MOSI_IO0 */
|
||||
{ RCAR_GP_PIN(2, 8), 0, 2 }, /* QSPI1_SPCLK */
|
||||
} },
|
||||
/* DRV2CTRL2 */
|
||||
{ 0x88, {
|
||||
{ RCAR_GP_PIN(2, 16), 0, 3 }, /* PCIE1_CLKREQ_N */
|
||||
} },
|
||||
/* DRV3CTRL2 is empty */
|
||||
/* DRV0CTRL3 */
|
||||
{ 0x80, {
|
||||
{ RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */
|
||||
{ RCAR_GP_PIN(3, 6), 24, 3 }, /* TSN1_LINK_B */
|
||||
{ RCAR_GP_PIN(3, 5), 20, 3 }, /* TSN1_MDC_B */
|
||||
{ RCAR_GP_PIN(3, 4), 16, 3 }, /* TSN0_MDC_B */
|
||||
{ RCAR_GP_PIN(3, 3), 12, 3 }, /* TSN2_MDC_B */
|
||||
{ RCAR_GP_PIN(3, 2), 8, 3 }, /* TSN0_MDIO_B */
|
||||
{ RCAR_GP_PIN(3, 1), 4, 3 }, /* TSN2_MDIO_B */
|
||||
{ RCAR_GP_PIN(3, 0), 0, 3 }, /* TSN1_MDIO_B */
|
||||
} },
|
||||
/* DRV1CTRL3 */
|
||||
{ 0x84, {
|
||||
{ RCAR_GP_PIN(3, 15), 28, 3 }, /* TSN1_AVTP_CAPTURE_B */
|
||||
{ RCAR_GP_PIN(3, 14), 24, 3 }, /* TSN1_AVTP_MATCH_B */
|
||||
{ RCAR_GP_PIN(3, 13), 20, 3 }, /* TSN1_AVTP_PPS */
|
||||
{ RCAR_GP_PIN(3, 12), 16, 3 }, /* TSN0_MAGIC_B */
|
||||
{ RCAR_GP_PIN(3, 11), 12, 3 }, /* TSN1_PHY_INT_B */
|
||||
{ RCAR_GP_PIN(3, 10), 8, 3 }, /* TSN0_PHY_INT_B */
|
||||
{ RCAR_GP_PIN(3, 9), 4, 3 }, /* TSN2_PHY_INT_B */
|
||||
{ RCAR_GP_PIN(3, 8), 0, 3 }, /* TSN0_LINK_B */
|
||||
} },
|
||||
/* DRV2CTRL3 */
|
||||
{ 0x88, {
|
||||
{ RCAR_GP_PIN(3, 18), 8, 3 }, /* TSN0_AVTP_CAPTURE_B */
|
||||
{ RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */
|
||||
{ RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
|
||||
} },
|
||||
/* DRV3CTRL3 is empty */
|
||||
/* DRV0CTRL4 */
|
||||
{ 0x80, {
|
||||
{ RCAR_GP_PIN(4, 7), 28, 3 }, /* GP4_07 */
|
||||
{ RCAR_GP_PIN(4, 6), 24, 3 }, /* GP4_06 */
|
||||
{ RCAR_GP_PIN(4, 5), 20, 3 }, /* GP4_05 */
|
||||
{ RCAR_GP_PIN(4, 4), 16, 3 }, /* GP4_04 */
|
||||
{ RCAR_GP_PIN(4, 3), 12, 3 }, /* GP4_03 */
|
||||
{ RCAR_GP_PIN(4, 2), 8, 3 }, /* GP4_02 */
|
||||
{ RCAR_GP_PIN(4, 1), 4, 3 }, /* GP4_01 */
|
||||
{ RCAR_GP_PIN(4, 0), 0, 3 }, /* GP4_00 */
|
||||
} },
|
||||
/* DRV1CTRL4 */
|
||||
{ 0x84, {
|
||||
{ RCAR_GP_PIN(4, 15), 28, 3 }, /* GP4_15 */
|
||||
{ RCAR_GP_PIN(4, 14), 24, 3 }, /* GP4_14 */
|
||||
{ RCAR_GP_PIN(4, 13), 20, 3 }, /* GP4_13 */
|
||||
{ RCAR_GP_PIN(4, 12), 16, 3 }, /* GP4_12 */
|
||||
{ RCAR_GP_PIN(4, 11), 12, 3 }, /* GP4_11 */
|
||||
{ RCAR_GP_PIN(4, 10), 8, 3 }, /* GP4_10 */
|
||||
{ RCAR_GP_PIN(4, 9), 4, 3 }, /* GP4_09 */
|
||||
{ RCAR_GP_PIN(4, 8), 0, 3 }, /* GP4_08 */
|
||||
} },
|
||||
/* DRV2CTRL4 */
|
||||
{ 0x88, {
|
||||
{ RCAR_GP_PIN(4, 23), 28, 3 }, /* MSPI0CSS1 */
|
||||
{ RCAR_GP_PIN(4, 22), 24, 3 }, /* MPSI0SO/MSPI0DCS */
|
||||
{ RCAR_GP_PIN(4, 21), 20, 3 }, /* MPSI0SI */
|
||||
{ RCAR_GP_PIN(4, 20), 16, 3 }, /* MSPI0SC */
|
||||
{ RCAR_GP_PIN(4, 19), 12, 3 }, /* GP4_19 */
|
||||
{ RCAR_GP_PIN(4, 18), 8, 3 }, /* GP4_18 */
|
||||
{ RCAR_GP_PIN(4, 17), 4, 3 }, /* GP4_17 */
|
||||
{ RCAR_GP_PIN(4, 16), 0, 3 }, /* GP4_16 */
|
||||
} },
|
||||
/* DRV3CTRL4 */
|
||||
{ 0x8c, {
|
||||
{ RCAR_GP_PIN(4, 30), 24, 3 }, /* MSPI1CSS1 */
|
||||
{ RCAR_GP_PIN(4, 29), 20, 3 }, /* MSPI1CSS2 */
|
||||
{ RCAR_GP_PIN(4, 28), 16, 3 }, /* MSPI1SC */
|
||||
{ RCAR_GP_PIN(4, 27), 12, 3 }, /* MSPI1CSS0 */
|
||||
{ RCAR_GP_PIN(4, 26), 8, 3 }, /* MPSI1SO/MSPI1DCS */
|
||||
{ RCAR_GP_PIN(4, 25), 4, 3 }, /* MSPI1SI */
|
||||
{ RCAR_GP_PIN(4, 24), 0, 3 }, /* MSPI0CSS0 */
|
||||
} },
|
||||
/* DRV0CTRL5 */
|
||||
{ 0x80, {
|
||||
{ RCAR_GP_PIN(5, 7), 28, 3 }, /* ETNB0RXD3 */
|
||||
{ RCAR_GP_PIN(5, 6), 24, 3 }, /* ETNB0RXER */
|
||||
{ RCAR_GP_PIN(5, 5), 20, 3 }, /* ETNB0MDC */
|
||||
{ RCAR_GP_PIN(5, 4), 16, 3 }, /* ETNB0LINKSTA */
|
||||
{ RCAR_GP_PIN(5, 3), 12, 3 }, /* ETNB0WOL */
|
||||
{ RCAR_GP_PIN(5, 2), 8, 3 }, /* ETNB0MD */
|
||||
{ RCAR_GP_PIN(5, 1), 4, 3 }, /* RIIC0SDA */
|
||||
{ RCAR_GP_PIN(5, 0), 0, 3 }, /* RIIC0SCL */
|
||||
} },
|
||||
/* DRV1CTRL5 */
|
||||
{ 0x84, {
|
||||
{ RCAR_GP_PIN(5, 15), 28, 3 }, /* ETNB0TXCLK */
|
||||
{ RCAR_GP_PIN(5, 14), 24, 3 }, /* ETNB0TXD3 */
|
||||
{ RCAR_GP_PIN(5, 13), 20, 3 }, /* ETNB0TXER */
|
||||
{ RCAR_GP_PIN(5, 12), 16, 3 }, /* ETNB0RXCLK */
|
||||
{ RCAR_GP_PIN(5, 11), 12, 3 }, /* ETNB0RXD0 */
|
||||
{ RCAR_GP_PIN(5, 10), 8, 3 }, /* ETNB0RXDV */
|
||||
{ RCAR_GP_PIN(5, 9), 4, 3 }, /* ETNB0RXD2 */
|
||||
{ RCAR_GP_PIN(5, 8), 0, 3 }, /* ETNB0RXD1 */
|
||||
} },
|
||||
/* DRV2CTRL5 */
|
||||
{ 0x88, {
|
||||
{ RCAR_GP_PIN(5, 19), 12, 3 }, /* ETNB0TXD0 */
|
||||
{ RCAR_GP_PIN(5, 18), 8, 3 }, /* ETNB0TXEN */
|
||||
{ RCAR_GP_PIN(5, 17), 4, 3 }, /* ETNB0TXD2 */
|
||||
{ RCAR_GP_PIN(5, 16), 0, 3 }, /* ETNB0TXD1 */
|
||||
} },
|
||||
/* DRV3CTRL5 is empty */
|
||||
/* DRV0CTRL6 */
|
||||
{ 0x80, {
|
||||
{ RCAR_GP_PIN(6, 7), 28, 3 }, /* RLIN34RX/INTP20 */
|
||||
{ RCAR_GP_PIN(6, 6), 24, 3 }, /* RLIN34TX */
|
||||
{ RCAR_GP_PIN(6, 5), 20, 3 }, /* RLIN35RX/INTP21 */
|
||||
{ RCAR_GP_PIN(6, 4), 16, 3 }, /* RLIN35TX */
|
||||
{ RCAR_GP_PIN(6, 3), 12, 3 }, /* RLIN36RX/INTP22 */
|
||||
{ RCAR_GP_PIN(6, 2), 8, 3 }, /* RLIN36TX */
|
||||
{ RCAR_GP_PIN(6, 1), 4, 3 }, /* RLIN37RX/INTP23 */
|
||||
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* RLIN37TX */
|
||||
} },
|
||||
/* DRV1CTRL6 */
|
||||
{ 0x84, {
|
||||
{ RCAR_GP_PIN(6, 15), 28, 3 }, /* RLIN30RX/INTP16 */
|
||||
{ RCAR_GP_PIN(6, 14), 24, 3 }, /* RLIN30TX */
|
||||
{ RCAR_GP_PIN(6, 13), 20, 3 }, /* RLIN31RX/INTP17 */
|
||||
{ RCAR_GP_PIN(6, 12), 16, 3 }, /* RLIN31TX */
|
||||
{ RCAR_GP_PIN(6, 11), 12, 3 }, /* RLIN32RX/INTP18 */
|
||||
{ RCAR_GP_PIN(6, 10), 8, 3 }, /* RLIN32TX */
|
||||
{ RCAR_GP_PIN(6, 9), 4, 3 }, /* RLIN33RX/INTP19 */
|
||||
{ RCAR_GP_PIN(6, 8), 0, 3 }, /* RLIN33TX */
|
||||
} },
|
||||
/* DRV2CTRL6 */
|
||||
{ 0x88, {
|
||||
{ RCAR_GP_PIN(6, 22), 24, 3 }, /* NMI1 */
|
||||
{ RCAR_GP_PIN(6, 21), 20, 3 }, /* INTP32 */
|
||||
{ RCAR_GP_PIN(6, 20), 16, 3 }, /* INTP33 */
|
||||
{ RCAR_GP_PIN(6, 19), 12, 3 }, /* INTP34 */
|
||||
{ RCAR_GP_PIN(6, 18), 8, 3 }, /* INTP35 */
|
||||
{ RCAR_GP_PIN(6, 17), 4, 3 }, /* INTP36 */
|
||||
{ RCAR_GP_PIN(6, 16), 0, 3 }, /* INTP37 */
|
||||
} },
|
||||
/* DRV3CTRL6 */
|
||||
{ 0x8c, {
|
||||
{ RCAR_GP_PIN(6, 31), 28, 3 }, /* PRESETOUT1# */
|
||||
} },
|
||||
/* DRV0CTRL7 */
|
||||
{ 0x80, {
|
||||
{ RCAR_GP_PIN(7, 7), 28, 3 }, /* CAN3RX/INTP3 */
|
||||
{ RCAR_GP_PIN(7, 6), 24, 3 }, /* CAN3TX */
|
||||
{ RCAR_GP_PIN(7, 5), 20, 3 }, /* CAN2RX/INTP2 */
|
||||
{ RCAR_GP_PIN(7, 4), 16, 3 }, /* CAN2TX */
|
||||
{ RCAR_GP_PIN(7, 3), 12, 3 }, /* CAN1RX/INTP1 */
|
||||
{ RCAR_GP_PIN(7, 2), 8, 3 }, /* CAN1TX */
|
||||
{ RCAR_GP_PIN(7, 1), 4, 3 }, /* CAN0RX/INTP0 */
|
||||
{ RCAR_GP_PIN(7, 0), 0, 3 }, /* CAN0TX */
|
||||
} },
|
||||
/* DRV1CTRL7 */
|
||||
{ 0x84, {
|
||||
{ RCAR_GP_PIN(7, 15), 28, 3 }, /* CAN7RX/INTP7 */
|
||||
{ RCAR_GP_PIN(7, 14), 24, 3 }, /* CAN7TX */
|
||||
{ RCAR_GP_PIN(7, 13), 20, 3 }, /* CAN6RX/INTP6 */
|
||||
{ RCAR_GP_PIN(7, 12), 16, 3 }, /* CAN6TX */
|
||||
{ RCAR_GP_PIN(7, 11), 12, 3 }, /* CAN5RX/INTP5 */
|
||||
{ RCAR_GP_PIN(7, 10), 8, 3 }, /* CAN5TX */
|
||||
{ RCAR_GP_PIN(7, 9), 4, 3 }, /* CAN4RX/INTP4 */
|
||||
{ RCAR_GP_PIN(7, 8), 0, 3 }, /* CAN4TX */
|
||||
} },
|
||||
/* DRV2CTRL7 */
|
||||
{ 0x88, {
|
||||
{ RCAR_GP_PIN(7, 23), 28, 3 }, /* CAN11RX/INTP11 */
|
||||
{ RCAR_GP_PIN(7, 22), 24, 3 }, /* CAN11TX */
|
||||
{ RCAR_GP_PIN(7, 21), 20, 3 }, /* CAN10RX/INTP10 */
|
||||
{ RCAR_GP_PIN(7, 20), 16, 3 }, /* CAN10TX */
|
||||
{ RCAR_GP_PIN(7, 19), 12, 3 }, /* CAN9RX/INTP9 */
|
||||
{ RCAR_GP_PIN(7, 18), 8, 3 }, /* CAN9TX */
|
||||
{ RCAR_GP_PIN(7, 17), 4, 3 }, /* CAN8RX/INTP8 */
|
||||
{ RCAR_GP_PIN(7, 16), 0, 3 }, /* CAN8TX */
|
||||
} },
|
||||
/* DRV3CTRL7 */
|
||||
{ 0x8c, {
|
||||
{ RCAR_GP_PIN(7, 31), 28, 3 }, /* CAN15RX/INTP15 */
|
||||
{ RCAR_GP_PIN(7, 30), 24, 3 }, /* CAN15TX */
|
||||
{ RCAR_GP_PIN(7, 29), 20, 3 }, /* CAN14RX/INTP14 */
|
||||
{ RCAR_GP_PIN(7, 28), 16, 3 }, /* CAN14TX */
|
||||
{ RCAR_GP_PIN(7, 27), 12, 3 }, /* CAN13RX/INTP13 */
|
||||
{ RCAR_GP_PIN(7, 26), 8, 3 }, /* CAN13TX */
|
||||
{ RCAR_GP_PIN(7, 25), 4, 3 }, /* CAN12RX/INTP12 */
|
||||
{ RCAR_GP_PIN(7, 24), 0, 3 }, /* CAN12TX */
|
||||
} },
|
||||
/* DRV0CTRLSYS0 */
|
||||
{ 0x80, {
|
||||
{ RCAR_GP_PIN(8, 0), 0, 3 }, /* PRESETOUT0# */
|
||||
} },
|
||||
/* DRV1CTRLSYS0 */
|
||||
{ 0x84, {
|
||||
{ RCAR_GP_PIN(8, 12), 16, 2 }, /* DCUTCK0 */
|
||||
{ RCAR_GP_PIN(8, 11), 12, 2 }, /* DCUTDO0 */
|
||||
{ RCAR_GP_PIN(8, 10), 8, 2 }, /* DCUTDI0 */
|
||||
{ RCAR_GP_PIN(8, 9), 4, 2 }, /* DCUTDY0# */
|
||||
{ RCAR_GP_PIN(8, 8), 0, 2 }, /* DCUTMS0 */
|
||||
} },
|
||||
{ },
|
||||
};
|
||||
|
||||
#define PFC_BIAS_REG(r1, r2) \
|
||||
.puen = r1, \
|
||||
.pud = r2, \
|
||||
.pins =
|
||||
|
||||
const struct pfc_bias_reg pfc_bias_regs[] = {
|
||||
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN0, PUD0 */
|
||||
[0] = RCAR_GP_PIN(0, 0), /* SCIF_CLK */
|
||||
[1] = RCAR_GP_PIN(0, 1), /* HSCK0 */
|
||||
[2] = RCAR_GP_PIN(0, 2), /* HRX0 */
|
||||
[3] = RCAR_GP_PIN(0, 3), /* HTX0 */
|
||||
[4] = RCAR_GP_PIN(0, 4), /* HCTS0_N */
|
||||
[5] = RCAR_GP_PIN(0, 5), /* HRTS0_N */
|
||||
[6] = RCAR_GP_PIN(0, 6), /* RX0 */
|
||||
[7] = RCAR_GP_PIN(0, 7), /* TX0 */
|
||||
[8] = RCAR_GP_PIN(0, 8), /* SCK0 */
|
||||
[9] = RCAR_GP_PIN(0, 9), /* RTS0_N */
|
||||
[10] = RCAR_GP_PIN(0, 10), /* CTS0_N */
|
||||
[11] = RCAR_GP_PIN(0, 11), /* MSIOF0_SYNC */
|
||||
[12] = RCAR_GP_PIN(0, 12), /* MSIOF0_RXD */
|
||||
[13] = RCAR_GP_PIN(0, 13), /* MSIOF0_TXD */
|
||||
[14] = RCAR_GP_PIN(0, 14), /* MSIOF0_SCK */
|
||||
[15] = RCAR_GP_PIN(0, 15), /* MSIOF0_SS1 */
|
||||
[16] = RCAR_GP_PIN(0, 16), /* MSIOF0_SS2 */
|
||||
[17] = RCAR_GP_PIN(0, 17), /* IRQ0 */
|
||||
[18] = RCAR_GP_PIN(0, 18), /* IRQ1 */
|
||||
[19] = RCAR_GP_PIN(0, 19), /* IRQ2 */
|
||||
[20] = RCAR_GP_PIN(0, 20), /* IRQ3 */
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
} },
|
||||
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN1, PUD1 */
|
||||
[0] = RCAR_GP_PIN(1, 0), /* GP1_00 */
|
||||
[1] = RCAR_GP_PIN(1, 1), /* GP1_01 */
|
||||
[2] = RCAR_GP_PIN(1, 2), /* GP1_02 */
|
||||
[3] = RCAR_GP_PIN(1, 3), /* GP1_03 */
|
||||
[4] = RCAR_GP_PIN(1, 4), /* GP1_04 */
|
||||
[5] = RCAR_GP_PIN(1, 5), /* GP1_05 */
|
||||
[6] = RCAR_GP_PIN(1, 6), /* GP1_06 */
|
||||
[7] = RCAR_GP_PIN(1, 7), /* GP1_07 */
|
||||
[8] = RCAR_GP_PIN(1, 8), /* GP1_08 */
|
||||
[9] = RCAR_GP_PIN(1, 9), /* GP1_09 */
|
||||
[10] = RCAR_GP_PIN(1, 10), /* GP1_10 */
|
||||
[11] = RCAR_GP_PIN(1, 11), /* GP1_11 */
|
||||
[12] = RCAR_GP_PIN(1, 12), /* MMC_SD_CLK */
|
||||
[13] = RCAR_GP_PIN(1, 13), /* MMC_SD_D0 */
|
||||
[14] = RCAR_GP_PIN(1, 14), /* MMC_SD_D1 */
|
||||
[15] = RCAR_GP_PIN(1, 15), /* MMC_SD_D2 */
|
||||
[16] = RCAR_GP_PIN(1, 16), /* MMC_SD_D3 */
|
||||
[17] = RCAR_GP_PIN(1, 17), /* MMC_D5 */
|
||||
[18] = RCAR_GP_PIN(1, 18), /* MMC_D4 */
|
||||
[19] = RCAR_GP_PIN(1, 19), /* MMC_D6 */
|
||||
[20] = RCAR_GP_PIN(1, 20), /* MMC_DS */
|
||||
[21] = RCAR_GP_PIN(1, 21), /* MMC_D7 */
|
||||
[22] = RCAR_GP_PIN(1, 22), /* MMC_SD_CMD */
|
||||
[23] = RCAR_GP_PIN(1, 23), /* SD_CD */
|
||||
[24] = RCAR_GP_PIN(1, 24), /* SD_WP */
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
} },
|
||||
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN2, PUD2 */
|
||||
[0] = RCAR_GP_PIN(2, 0), /* RPC_INT_N */
|
||||
[1] = RCAR_GP_PIN(2, 1), /* RPC_WP_N */
|
||||
[2] = RCAR_GP_PIN(2, 2), /* RPC_RESET_N */
|
||||
[3] = RCAR_GP_PIN(2, 3), /* QSPI1_SSL */
|
||||
[4] = RCAR_GP_PIN(2, 4), /* QSPI1_IO3 */
|
||||
[5] = RCAR_GP_PIN(2, 5), /* QSPI1_MISO_IO1 */
|
||||
[6] = RCAR_GP_PIN(2, 6), /* QSPI1_IO2 */
|
||||
[7] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI_IO0 */
|
||||
[8] = RCAR_GP_PIN(2, 8), /* QSPI1_SPCLK */
|
||||
[9] = RCAR_GP_PIN(2, 9), /* QSPI0_MOSI_IO0 */
|
||||
[10] = RCAR_GP_PIN(2, 10), /* QSPI0_SPCLK */
|
||||
[11] = RCAR_GP_PIN(2, 11), /* QSPI0_IO2 */
|
||||
[12] = RCAR_GP_PIN(2, 12), /* QSPI0_MISO_IO1 */
|
||||
[13] = RCAR_GP_PIN(2, 13), /* QSPI0_SSL */
|
||||
[14] = RCAR_GP_PIN(2, 14), /* QSPI0_IO3 */
|
||||
[15] = RCAR_GP_PIN(2, 15), /* PCIE0_CLKREQ_N */
|
||||
[16] = RCAR_GP_PIN(2, 16), /* PCIE1_CLKREQ_N */
|
||||
[17] = PIN_NONE,
|
||||
[18] = PIN_NONE,
|
||||
[19] = PIN_NONE,
|
||||
[20] = PIN_NONE,
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
} },
|
||||
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN3, PUD3 */
|
||||
[0] = RCAR_GP_PIN(3, 0), /* TSN1_MDIO_B */
|
||||
[1] = RCAR_GP_PIN(3, 1), /* TSN2_MDIO_B */
|
||||
[2] = RCAR_GP_PIN(3, 2), /* TSN0_MDIO_B */
|
||||
[3] = RCAR_GP_PIN(3, 3), /* TSN2_MDC_B */
|
||||
[4] = RCAR_GP_PIN(3, 4), /* TSN0_MDC_B */
|
||||
[5] = RCAR_GP_PIN(3, 5), /* TSN1_MDC_B */
|
||||
[6] = RCAR_GP_PIN(3, 6), /* TSN1_LINK_B */
|
||||
[7] = RCAR_GP_PIN(3, 7), /* TSN2_LINK_B */
|
||||
[8] = RCAR_GP_PIN(3, 8), /* TSN0_LINK_B */
|
||||
[9] = RCAR_GP_PIN(3, 9), /* TSN2_PHY_INT_B */
|
||||
[10] = RCAR_GP_PIN(3, 10), /* TSN0_PHY_INT_B */
|
||||
[11] = RCAR_GP_PIN(3, 11), /* TSN1_PHY_INT_B */
|
||||
[12] = RCAR_GP_PIN(3, 12), /* TSN0_MAGIC_B */
|
||||
[13] = RCAR_GP_PIN(3, 13), /* TSN1_AVTP_PPS */
|
||||
[14] = RCAR_GP_PIN(3, 14), /* TSN1_AVTP_MATCH_B */
|
||||
[15] = RCAR_GP_PIN(3, 15), /* TSN1_AVTP_CAPTURE_B */
|
||||
[16] = RCAR_GP_PIN(3, 16), /* TSN0_AVTP_PPS */
|
||||
[17] = RCAR_GP_PIN(3, 17), /* TSN0_AVTP_MATCH_B */
|
||||
[18] = RCAR_GP_PIN(3, 18), /* TSN0_AVTP_CAPTURE_B */
|
||||
[19] = PIN_NONE,
|
||||
[20] = PIN_NONE,
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
} },
|
||||
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN4, PUD4 */
|
||||
[0] = RCAR_GP_PIN(4, 0), /* GP4_00 */
|
||||
[1] = RCAR_GP_PIN(4, 1), /* GP4_01 */
|
||||
[2] = RCAR_GP_PIN(4, 2), /* GP4_02 */
|
||||
[3] = RCAR_GP_PIN(4, 3), /* GP4_03 */
|
||||
[4] = RCAR_GP_PIN(4, 4), /* GP4_04 */
|
||||
[5] = RCAR_GP_PIN(4, 5), /* GP4_05 */
|
||||
[6] = RCAR_GP_PIN(4, 6), /* GP4_06 */
|
||||
[7] = RCAR_GP_PIN(4, 7), /* GP4_07 */
|
||||
[8] = RCAR_GP_PIN(4, 8), /* GP4_08 */
|
||||
[9] = RCAR_GP_PIN(4, 9), /* GP4_09 */
|
||||
[10] = RCAR_GP_PIN(4, 10), /* GP4_10 */
|
||||
[11] = RCAR_GP_PIN(4, 11), /* GP4_11 */
|
||||
[12] = RCAR_GP_PIN(4, 12), /* GP4_12 */
|
||||
[13] = RCAR_GP_PIN(4, 13), /* GP4_13 */
|
||||
[14] = RCAR_GP_PIN(4, 14), /* GP4_14 */
|
||||
[15] = RCAR_GP_PIN(4, 15), /* GP4_15 */
|
||||
[16] = RCAR_GP_PIN(4, 16), /* GP4_16 */
|
||||
[17] = RCAR_GP_PIN(4, 17), /* GP4_17 */
|
||||
[18] = RCAR_GP_PIN(4, 18), /* GP4_18 */
|
||||
[19] = RCAR_GP_PIN(4, 19), /* GP4_19 */
|
||||
[20] = RCAR_GP_PIN(4, 20), /* MSPI0SC */
|
||||
[21] = RCAR_GP_PIN(4, 21), /* MSPI0SI */
|
||||
[22] = RCAR_GP_PIN(4, 22), /* MSPI0SO/MSPI0DCS */
|
||||
[23] = RCAR_GP_PIN(4, 23), /* MSPI0CSS1 */
|
||||
[24] = RCAR_GP_PIN(4, 24), /* MSPI0CSS0 */
|
||||
[25] = RCAR_GP_PIN(4, 25), /* MSPI1SI */
|
||||
[26] = RCAR_GP_PIN(4, 26), /* MSPI1SO/MSPI1DCS */
|
||||
[27] = RCAR_GP_PIN(4, 27), /* MSPI1CSS0 */
|
||||
[28] = RCAR_GP_PIN(4, 28), /* MSPI1SC */
|
||||
[29] = RCAR_GP_PIN(4, 29), /* MSPI1CSS2 */
|
||||
[30] = RCAR_GP_PIN(4, 30), /* MSPI1CSS1 */
|
||||
[31] = PIN_NONE,
|
||||
} },
|
||||
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN5, PUD5 */
|
||||
[0] = RCAR_GP_PIN(5, 0), /* RIIC0SCL */
|
||||
[1] = RCAR_GP_PIN(5, 1), /* RIIC0SDA */
|
||||
[2] = RCAR_GP_PIN(5, 2), /* ETNB0MD */
|
||||
[3] = RCAR_GP_PIN(5, 3), /* ETNB0WOL */
|
||||
[4] = RCAR_GP_PIN(5, 4), /* ETNB0LINKSTA */
|
||||
[5] = RCAR_GP_PIN(5, 5), /* ETNB0MDC */
|
||||
[6] = RCAR_GP_PIN(5, 6), /* ETNB0RXER */
|
||||
[7] = RCAR_GP_PIN(5, 7), /* ETNB0RXD3 */
|
||||
[8] = RCAR_GP_PIN(5, 8), /* ETNB0RXD1 */
|
||||
[9] = RCAR_GP_PIN(5, 9), /* ETNB0RXD2 */
|
||||
[10] = RCAR_GP_PIN(5, 10), /* ETNB0RXDV */
|
||||
[11] = RCAR_GP_PIN(5, 11), /* ETNB0RXD0 */
|
||||
[12] = RCAR_GP_PIN(5, 12), /* ETNB0RXCLK */
|
||||
[13] = RCAR_GP_PIN(5, 13), /* ETNB0TXER */
|
||||
[14] = RCAR_GP_PIN(5, 14), /* ETNB0TXD3 */
|
||||
[15] = RCAR_GP_PIN(5, 15), /* ETNB0TXCLK */
|
||||
[16] = RCAR_GP_PIN(5, 16), /* ETNB0TXD1 */
|
||||
[17] = RCAR_GP_PIN(5, 17), /* ETNB0TXD2 */
|
||||
[18] = RCAR_GP_PIN(5, 18), /* ETNB0TXEN */
|
||||
[19] = RCAR_GP_PIN(5, 19), /* ETNB0TXD0 */
|
||||
[20] = PIN_NONE,
|
||||
[21] = PIN_NONE,
|
||||
[22] = PIN_NONE,
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
} },
|
||||
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN6, PUD6 */
|
||||
[0] = RCAR_GP_PIN(6, 0), /* RLIN37TX */
|
||||
[1] = RCAR_GP_PIN(6, 1), /* RLIN37RX/INTP23 */
|
||||
[2] = RCAR_GP_PIN(6, 2), /* RLIN36TX */
|
||||
[3] = RCAR_GP_PIN(6, 3), /* RLIN36RX/INTP22 */
|
||||
[4] = RCAR_GP_PIN(6, 4), /* RLIN35TX */
|
||||
[5] = RCAR_GP_PIN(6, 5), /* RLIN35RX/INTP21 */
|
||||
[6] = RCAR_GP_PIN(6, 6), /* RLIN34TX */
|
||||
[7] = RCAR_GP_PIN(6, 7), /* RLIN34RX/INTP20 */
|
||||
[8] = RCAR_GP_PIN(6, 8), /* RLIN33TX */
|
||||
[9] = RCAR_GP_PIN(6, 9), /* RLIN33RX/INTP19 */
|
||||
[10] = RCAR_GP_PIN(6, 10), /* RLIN32TX */
|
||||
[11] = RCAR_GP_PIN(6, 11), /* RLIN32RX/INTP18 */
|
||||
[12] = RCAR_GP_PIN(6, 12), /* RLIN31TX */
|
||||
[13] = RCAR_GP_PIN(6, 13), /* RLIN31RX/INTP17 */
|
||||
[14] = RCAR_GP_PIN(6, 14), /* RLIN30TX */
|
||||
[15] = RCAR_GP_PIN(6, 15), /* RLIN30RX/INTP16 */
|
||||
[16] = RCAR_GP_PIN(6, 16), /* INTP37 */
|
||||
[17] = RCAR_GP_PIN(6, 17), /* INTP36 */
|
||||
[18] = RCAR_GP_PIN(6, 18), /* INTP35 */
|
||||
[19] = RCAR_GP_PIN(6, 19), /* INTP34 */
|
||||
[20] = RCAR_GP_PIN(6, 20), /* INTP33 */
|
||||
[21] = RCAR_GP_PIN(6, 21), /* INTP32 */
|
||||
[22] = RCAR_GP_PIN(6, 22), /* NMI1 */
|
||||
[23] = PIN_NONE,
|
||||
[24] = PIN_NONE,
|
||||
[25] = PIN_NONE,
|
||||
[26] = PIN_NONE,
|
||||
[27] = PIN_NONE,
|
||||
[28] = PIN_NONE,
|
||||
[29] = PIN_NONE,
|
||||
[30] = PIN_NONE,
|
||||
[31] = PIN_NONE,
|
||||
} },
|
||||
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN7, PUD7 */
|
||||
[0] = RCAR_GP_PIN(7, 0), /* CAN0TX */
|
||||
[1] = RCAR_GP_PIN(7, 1), /* CAN0RX/INTP0 */
|
||||
[2] = RCAR_GP_PIN(7, 2), /* CAN1TX */
|
||||
[3] = RCAR_GP_PIN(7, 3), /* CAN1RX/INTP1 */
|
||||
[4] = RCAR_GP_PIN(7, 4), /* CAN2TX */
|
||||
[5] = RCAR_GP_PIN(7, 5), /* CAN2RX/INTP2 */
|
||||
[6] = RCAR_GP_PIN(7, 6), /* CAN3TX */
|
||||
[7] = RCAR_GP_PIN(7, 7), /* CAN3RX/INTP3 */
|
||||
[8] = RCAR_GP_PIN(7, 8), /* CAN4TX */
|
||||
[9] = RCAR_GP_PIN(7, 9), /* CAN4RX/INTP4 */
|
||||
[10] = RCAR_GP_PIN(7, 10), /* CAN5TX */
|
||||
[11] = RCAR_GP_PIN(7, 11), /* CAN5RX/INTP5 */
|
||||
[12] = RCAR_GP_PIN(7, 12), /* CAN6TX */
|
||||
[13] = RCAR_GP_PIN(7, 13), /* CAN6RX/INTP6 */
|
||||
[14] = RCAR_GP_PIN(7, 14), /* CAN7TX */
|
||||
[15] = RCAR_GP_PIN(7, 15), /* CAN7RX/INTP7 */
|
||||
[16] = RCAR_GP_PIN(7, 16), /* CAN8TX */
|
||||
[17] = RCAR_GP_PIN(7, 17), /* CAN8RX/INTP8 */
|
||||
[18] = RCAR_GP_PIN(7, 18), /* CAN9TX */
|
||||
[19] = RCAR_GP_PIN(7, 19), /* CAN9RX/INTP9 */
|
||||
[20] = RCAR_GP_PIN(7, 20), /* CAN10TX */
|
||||
[21] = RCAR_GP_PIN(7, 21), /* CAN10RX/INTP10 */
|
||||
[22] = RCAR_GP_PIN(7, 22), /* CAN11TX */
|
||||
[23] = RCAR_GP_PIN(7, 23), /* CAN11RX/INTP11 */
|
||||
[24] = RCAR_GP_PIN(7, 24), /* CAN12TX */
|
||||
[25] = RCAR_GP_PIN(7, 25), /* CAN12RX/INTP12 */
|
||||
[26] = RCAR_GP_PIN(7, 26), /* CAN13TX */
|
||||
[27] = RCAR_GP_PIN(7, 27), /* CAN13RX/INTP13 */
|
||||
[28] = RCAR_GP_PIN(7, 28), /* CAN14TX */
|
||||
[29] = RCAR_GP_PIN(7, 29), /* CAN14RX/INTP14 */
|
||||
[30] = RCAR_GP_PIN(7, 30), /* CAN15TX */
|
||||
[31] = RCAR_GP_PIN(7, 31), /* CAN15RX/INTP15 */
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void)
|
||||
{
|
||||
return pfc_bias_regs;
|
||||
}
|
||||
|
||||
const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void)
|
||||
{
|
||||
return pfc_drive_regs;
|
||||
}
|
||||
|
||||
int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index)
|
||||
{
|
||||
if (RCAR_IS_GP_PIN(pin) == false)
|
||||
return -EINVAL;
|
||||
|
||||
*reg_index = pin / 32;
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue