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soc: arm64: add support of r8a77961

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Add support of r8a77961 SoC to gen3 series.
Create a dtsi file with a common part for both r8a77951 and r8a77961.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
This commit is contained in:
Mykola Kvach 2023-05-02 13:36:34 +03:00 • committed by Carles Cufí
commit 38675f2b92
6 changed files with 130 additions and 66 deletions
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2
drivers/clock_control/CMakeLists.txt
View file

@ -63,7 +63,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_AGILEX clock_agilex.c)
if(CONFIG_CLOCK_CONTROL_RCAR_CPG_MSSR)
zephyr_library_sources(clock_control_renesas_cpg_mssr.c)
zephyr_library_sources_ifdef(CONFIG_SOC_R8A77951 clock_control_r8a7795_cpg_mssr.c)
zephyr_library_sources_ifdef(CONFIG_DT_HAS_RENESAS_R8A7795_CPG_MSSR_ENABLED clock_control_r8a7795_cpg_mssr.c)
endif()
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AST10X0 clock_control_ast10x0.c)

70
dts/arm64/renesas/r8a77951.dtsi
View file

@ -5,15 +5,10 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm64/armv8-a.dtsi>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
#include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
#include "rcar_gen3_ca57.dtsi"
/ {
compatible = "renesas,r8a77951";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
@ -26,63 +21,8 @@
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
method = "smc";
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400", "arm,gic" ;
#interrupt-cells = <4>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1010000 0 0x1000>,
<0 0xf1020000 0 0x20000>;
status = "okay";
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7795-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,rcar-pfc";
reg = <0 0xe6060000 0 0x50c>;
};
scif2: serial@e6e88000 {
compatible = "renesas,rcar-scif";
reg = <0 0xe6e88000 0 0x64>;
interrupt-parent = <&gic>;
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE R8A7795_CLK_S3D4>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
current-speed = <115200>;
interrupt-names = "irq_0";
status = "disabled";
};
};
};
&cpg {
compatible = "renesas,r8a7795-cpg-mssr";
};

28
dts/arm64/renesas/r8a77961.dtsi Normal file
View file

@ -0,0 +1,28 @@
/*
* Device Tree Source for the R-Car M3 (R8A77961) SoC
*
* Copyright (C) 2023 EPAM Systems.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "rcar_gen3_ca57.dtsi"
/ {
compatible = "renesas,r8a77961";
cpus {
#address-cells = <1>;
#size-cells = <0>;
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
};
};
};
&cpg {
compatible = "renesas,r8a7795-cpg-mssr";
};

84
dts/arm64/renesas/rcar_gen3_ca57.dtsi Normal file
View file

@ -0,0 +1,84 @@
/*
* Device Tree Source for the R-Car H3/M3 (R8A77951/R8A77961) SoC
*
* Copyright (C) 2023 EPAM Systems.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm64/armv8-a.dtsi>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
#include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
method = "smc";
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400", "arm,gic" ;
#interrupt-cells = <4>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1010000 0 0x1000>,
<0 0xf1020000 0 0x20000>;
status = "okay";
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
cpg: clock-controller@e6150000 {
reg = <0 0xe6150000 0 0x1000>;
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
emmc2: mmc@ee140000 {
compatible = "renesas,rcar-mmc";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
clocks = <&cpg CPG_MOD 312>;
max-frequency = <200000000>;
status = "disabled";
};
pfc: pin-controller@e6060000 {
compatible = "renesas,rcar-pfc";
reg = <0 0xe6060000 0 0x50c>;
};
scif2: serial@e6e88000 {
compatible = "renesas,rcar-scif";
reg = <0 0xe6e88000 0 0x64>;
interrupt-parent = <&gic>;
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE R8A7795_CLK_S3D4>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
current-speed = <115200>;
interrupt-names = "irq_0";
status = "disabled";
};
};
};

9
soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77961 Normal file
View file

@ -0,0 +1,9 @@
# Copyright (c) 2023 EPAM Systems
# SPDX-License-Identifier: Apache-2.0
if SOC_R8A77961
config SOC
default "r8a77961"
endif # SOC_R8A77961

3
soc/arm64/renesas_rcar/gen3/Kconfig.soc
View file

@ -8,4 +8,7 @@ choice
config SOC_ARM64_R8A77951
bool "R8A77951"
config SOC_R8A77961
bool "R8A77961"
endchoice