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soc: arm: use sys_cache* to enable caches for stm32f7 and stm32h7

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Use sys_cache* functions to enable the caches for stm32f7 and
stm32h7. This ensures that CONFIG_CACHE_MANAGEMENT is
considered correctly.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This commit is contained in:
Benedikt Schmidt 2023-12-18 11:16:12 +01:00 • committed by Carles Cufí
commit 10c0b86f83
2 changed files with 6 additions and 14 deletions
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10
soc/arm/st_stm32/stm32f7/soc.c
View file

@ -12,6 +12,7 @@
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/cache.h>
#include <soc.h>
#include <cmsis_core.h>
@ -30,13 +31,8 @@ static int st_stm32f7_init(void)
/* Enable ART Flash cache accelerator */
LL_FLASH_EnableART();
if (IS_ENABLED(CONFIG_ICACHE)) {
SCB_EnableICache();
}
if (IS_ENABLED(CONFIG_DCACHE)) {
SCB_EnableDCache();
}
sys_cache_instr_enable();
sys_cache_data_enable();
/* Update CMSIS SystemCoreClock variable (HCLK) */
/* At reset, system core clock is set to 16 MHz from HSI */

10
soc/arm/st_stm32/stm32h7/soc_m7.c
View file

@ -12,6 +12,7 @@
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/cache.h>
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
@ -54,13 +55,8 @@ static int stm32h7_m4_wakeup(void)
*/
static int stm32h7_init(void)
{
if (IS_ENABLED(CONFIG_ICACHE)) {
SCB_EnableICache();
}
if (IS_ENABLED(CONFIG_DCACHE)) {
SCB_EnableDCache();
}
sys_cache_instr_enable();
sys_cache_data_enable();
/* Update CMSIS SystemCoreClock variable (HCLK) */
/* At reset, system core clock is set to 64 MHz from HSI */