soc: arm: use sys_cache* to enable caches for stm32f7 and stm32h7
Use sys_cache* functions to enable the caches for stm32f7 and stm32h7. This ensures that CONFIG_CACHE_MANAGEMENT is considered correctly. Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
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2 changed files with 6 additions and 14 deletions
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@ -12,6 +12,7 @@
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/cache.h>
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#include <soc.h>
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#include <cmsis_core.h>
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@ -30,13 +31,8 @@ static int st_stm32f7_init(void)
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/* Enable ART Flash cache accelerator */
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LL_FLASH_EnableART();
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if (IS_ENABLED(CONFIG_ICACHE)) {
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SCB_EnableICache();
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}
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if (IS_ENABLED(CONFIG_DCACHE)) {
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SCB_EnableDCache();
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}
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sys_cache_instr_enable();
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sys_cache_data_enable();
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 16 MHz from HSI */
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@ -12,6 +12,7 @@
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/cache.h>
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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@ -54,13 +55,8 @@ static int stm32h7_m4_wakeup(void)
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*/
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static int stm32h7_init(void)
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{
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if (IS_ENABLED(CONFIG_ICACHE)) {
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SCB_EnableICache();
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}
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if (IS_ENABLED(CONFIG_DCACHE)) {
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SCB_EnableDCache();
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}
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sys_cache_instr_enable();
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sys_cache_data_enable();
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 64 MHz from HSI */
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