driver: clock_control: npcx: add support for npcx4 series
This CL introduces new clock architectures in npcx4 series and wraps clock configurations of different series by device tree files. For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val` prop of pcc DT node now. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
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8ae0bb8b70
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5c7ab5c2bf
7 changed files with 114 additions and 53 deletions
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@ -28,6 +28,8 @@ struct npcx_pcc_config {
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#define HAL_PMC_INST(dev) \
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((struct pmc_reg *)((const struct npcx_pcc_config *)(dev)->config)->base_pmc)
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static uint8_t pddwn_ctl_val[] = {NPCX_PWDWN_CTL_INIT};
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/* Clock controller local functions */
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static inline int npcx_clock_control_on(const struct device *dev,
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clock_control_subsys_t sub_system)
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@ -89,6 +91,11 @@ static int npcx_clock_control_get_subsys_rate(const struct device *dev,
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case NPCX_CLOCK_BUS_FIU:
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*rate = CORE_CLK/(FIUDIV_VAL + 1);
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break;
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#if defined(FIU1DIV_VAL)
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case NPCX_CLOCK_BUS_FIU1:
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*rate = CORE_CLK/(FIU1DIV_VAL + 1);
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break;
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#endif
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case NPCX_CLOCK_BUS_CORE:
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*rate = CORE_CLK;
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break;
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@ -144,30 +151,36 @@ static struct clock_control_driver_api npcx_clock_control_api = {
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};
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/* valid clock frequency check */
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BUILD_ASSERT(CORE_CLK <= MHZ(100) && CORE_CLK >= MHZ(4) &&
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BUILD_ASSERT(OFMCLK <= MAX_OFMCLK, "Exceed maximum OFMCLK setting");
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BUILD_ASSERT(CORE_CLK <= MAX_OFMCLK && CORE_CLK >= MHZ(4) &&
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OFMCLK % CORE_CLK == 0 &&
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OFMCLK / CORE_CLK <= 10,
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"Invalid CORE_CLK setting");
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BUILD_ASSERT(CORE_CLK / (FIUDIV_VAL + 1) <= MHZ(50) &&
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BUILD_ASSERT(CORE_CLK / (FIUDIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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CORE_CLK / (FIUDIV_VAL + 1) >= MHZ(4),
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"Invalid FIUCLK setting");
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BUILD_ASSERT(CORE_CLK / (AHB6DIV_VAL + 1) <= MHZ(50) &&
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#if defined(FIU1DIV_VAL)
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BUILD_ASSERT(CORE_CLK / (FIU1DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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CORE_CLK / (FIU1DIV_VAL + 1) >= MHZ(4),
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"Invalid FIU1CLK setting");
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#endif
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BUILD_ASSERT(CORE_CLK / (AHB6DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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CORE_CLK / (AHB6DIV_VAL + 1) >= MHZ(4),
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"Invalid AHB6_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB1DIV_VAL + 1) <= MHZ(50) &&
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BUILD_ASSERT(APBSRC_CLK / (APB1DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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APBSRC_CLK / (APB1DIV_VAL + 1) >= MHZ(4) &&
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(APB1DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB1_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB2DIV_VAL + 1) <= MHZ(50) &&
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BUILD_ASSERT(APBSRC_CLK / (APB2DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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APBSRC_CLK / (APB2DIV_VAL + 1) >= MHZ(8) &&
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(APB2DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB2_CLK setting");
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BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= MHZ(50) &&
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BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
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APBSRC_CLK / (APB3DIV_VAL + 1) >= KHZ(12500) &&
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(APB3DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB3_CLK setting");
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#if defined(APB4DIV_VAL)
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BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) <= MHZ(100) &&
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BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) <= MAX_OFMCLK &&
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APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(8) &&
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(APB4DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB4_CLK setting");
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@ -205,36 +218,23 @@ static int npcx_clock_control_init(const struct device *dev)
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}
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/* Set all clock prescalers of core and peripherals. */
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inst_cdcg->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL);
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inst_cdcg->HFCBCD = (FIUDIV_VAL << 4);
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inst_cdcg->HFCBCD1 = (APB1DIV_VAL | (APB2DIV_VAL << 4));
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#if defined(APB4DIV_VAL)
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inst_cdcg->HFCBCD2 = (APB3DIV_VAL | (APB4DIV_VAL << 4));
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#else
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inst_cdcg->HFCBCD2 = APB3DIV_VAL;
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#endif
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inst_cdcg->HFCGP = VAL_HFCGP;
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inst_cdcg->HFCBCD = VAL_HFCBCD;
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inst_cdcg->HFCBCD1 = VAL_HFCBCD1;
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inst_cdcg->HFCBCD2 = VAL_HFCBCD2;
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/*
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* Power-down (turn off clock) the modules initially for better
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* power consumption.
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*/
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL1) = 0xFB; /* No SDP_PD/FIU_PD */
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL2) = 0xFF;
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL3) = 0x1F; /* No GDMA_PD */
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL4) = 0xFF;
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL5) = 0xFA;
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#if CONFIG_ESPI
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/* Don't gate the clock of the eSPI module if eSPI interface is required */
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL6) = 0x7F;
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#else
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL6) = 0xFF;
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#endif
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#if defined(CONFIG_SOC_SERIES_NPCX7)
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL7) = 0xE7;
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#elif defined(CONFIG_SOC_SERIES_NPCX9)
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL7) = 0xFF;
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL8) = 0x31;
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#endif
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for (int i = 0; i < ARRAY_SIZE(pddwn_ctl_val); i++) {
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NPCX_PWDWN_CTL(pmc_base, i) = pddwn_ctl_val[i];
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}
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/* Turn off the clock of the eSPI module only if eSPI isn't required */
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if (!IS_ENABLED(CONFIG_ESPI)) {
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NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL6) |= BIT(7);
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}
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return 0;
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}
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@ -115,6 +115,14 @@
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apb3-prescaler = <8>; /* APB3_CLK runs at 15MHz */
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apb4-prescaler = <8>; /* APB4_CLK runs at 15MHz */
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ram-pd-depth = <8>; /* Valid bit-depth of RAM_PDn reg */
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pwdwn-ctl-val = <0xfb
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0xff
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0x1f /* No GDMA1_PD/GDMA2_PD */
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0xff
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0xfa
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0x7f /* No ESPI_PD */
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0xff
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0xcf>; /* No FIU_PD */
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};
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/* Wake-up input source mapping for GPIOs in npcx4 series */
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@ -94,6 +94,13 @@
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apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
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apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
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ram-pd-depth = <12>; /* Valid bit-depth of RAM_PDn reg */
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pwdwn-ctl-val = <0xfb /* No FIU_PD */
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0xff
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0x1f /* No GDMA_PD */
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0xff
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0xfa
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0x7f /* No ESPI_PD */
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0xe7>;
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};
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/* Wake-up input source mapping for GPIOs in npcx7 series */
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@ -114,6 +114,14 @@
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apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
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apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */
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ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */
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pwdwn-ctl-val = <0xfb /* No FIU_PD */
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0xff
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0x1f /* No GDMA_PD */
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0xff
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0xfa
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0x7f /* No ESPI_PD */
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0xff
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0x31>;
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};
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/* Wake-up input source mapping for GPIOs in npcx9 series */
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@ -32,6 +32,7 @@ properties:
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description: |
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Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
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only the following values are allowed:
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120000000, 120 MHz
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100000000, 100 MHz
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96000000, 96 MHz
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90000000, 90 MHz
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@ -39,9 +40,8 @@ properties:
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66000000, 66 MHz
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50000000, 50 MHz
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48000000, 48 MHz
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40000000, 40 MHz (default value after reset)
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33000000, 33 MHz
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enum:
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- 120000000
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- 100000000
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- 96000000
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- 90000000
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@ -49,8 +49,6 @@ properties:
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- 66000000
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- 50000000
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- 48000000
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- 40000000
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- 33000000
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core-prescaler:
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type: int
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@ -208,6 +206,7 @@ properties:
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ram-pd-depth:
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type: int
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enum:
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- 8
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- 12
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- 15
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description: |
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@ -216,6 +215,13 @@ properties:
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itself to 1 for better power consumption and this valid bit-depth
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varies in different NPCX series.
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pwdwn-ctl-val:
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type: array
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required: true
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description: |
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Power-down (turn off clock) the modules during system initialization for
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better power consumption.
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clock-cells:
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- bus
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- ctl
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@ -18,6 +18,8 @@
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#define NPCX_CLOCK_BUS_APB4 8
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#define NPCX_CLOCK_BUS_AHB6 9
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#define NPCX_CLOCK_BUS_FMCLK 10
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#define NPCX_CLOCK_BUS_FIU0 NPCX_CLOCK_BUS_FIU
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#define NPCX_CLOCK_BUS_FIU1 11
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/* clock enable/disable references */
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#define NPCX_PWDWN_CTL1 0
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@ -51,15 +51,28 @@ struct npcx_clk_cfg {
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#endif /* !CONFIG_SOC_SERIES_NPCX7 */
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#endif
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/* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */
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#define NPCX_PWDWN_CTL_ITEMS_INIT(node, prop, idx) DT_PROP_BY_IDX(node, prop, idx),
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#define NPCX_PWDWN_CTL_INIT DT_FOREACH_PROP_ELEM(DT_NODELABEL(pcc), \
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pwdwn_ctl_val, NPCX_PWDWN_CTL_ITEMS_INIT)
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/*
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* NPCX7 and later series clock tree macros:
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* (Please refer Figure 58. for more information.)
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*
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* Suggestion:
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* - OFMCLK > 50MHz, XF_RANGE should be 1, else 0.
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* - CORE_CLK > 50MHz, AHB6DIV should be 1, else 0.
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* - CORE_CLK > 50MHz, FIUDIV should be 1, else 0.
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* Maximum OFMCLK in npcx7/9 series is 100MHz,
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* Maximum OFMCLK in npcx4 series is 120MHz,
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*
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* Suggestion for npcx series:
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* - OFMCLK > MAX_OFMCLK/2, XF_RANGE should be 1, else 0.
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* - CORE_CLK > MAX_OFMCLK/2, AHB6DIV should be 1, else 0.
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* - CORE_CLK > MAX_OFMCLK/2, FIUDIV should be 1, else 0.
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*/
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#if defined(CONFIG_SOC_SERIES_NPCX4)
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#define MAX_OFMCLK 120000000
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#else
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#define MAX_OFMCLK 100000000
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#endif /* CONFIG_SOC_SERIES_NPCX4 */
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/* Core domain clock */
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#define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler))
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@ -67,8 +80,8 @@ struct npcx_clk_cfg {
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#define LFCLK 32768
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/* FMUL clock */
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#if (OFMCLK > 50000000)
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#define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 if OFMCLK > 50MHz */
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#if (OFMCLK > (MAX_OFMCLK / 2))
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#define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 */
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#else
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#define FMCLK OFMCLK /* FMUL clock = OFMCLK */
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#endif
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@ -77,18 +90,27 @@ struct npcx_clk_cfg {
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#define APBSRC_CLK OFMCLK
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/* AHB6 clock */
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#if (CORE_CLK > 50000000)
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#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 if CORE_CLK > 50MHz */
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#if (CORE_CLK > (MAX_OFMCLK / 2))
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#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 */
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#else
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#define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */
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#endif
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/* FIU clock divider */
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#if (CORE_CLK > 50000000)
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#if (CORE_CLK > (MAX_OFMCLK / 2))
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#define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */
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#else
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#define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
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#endif
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#if defined(CONFIG_SOC_SERIES_NPCX4)
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#if (CORE_CLK > (MAX_OFMCLK / 2))
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#define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */
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#else
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#define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */
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#endif
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#endif /* CONFIG_SOC_SERIES_NPCX4 */
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/* Get APB clock freq */
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#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
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@ -96,8 +118,8 @@ struct npcx_clk_cfg {
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* Frequency multiplier M/N value definitions according to the requested
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* OFMCLK (Unit:Hz).
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*/
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#if (OFMCLK > 50000000)
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#define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 if OFMCLK > 50MHz */
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#if (OFMCLK > (MAX_OFMCLK / 2))
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#define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 */
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#else
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#define HFCGN_VAL 0x02
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#endif
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@ -125,16 +147,24 @@ struct npcx_clk_cfg {
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#elif (OFMCLK == 48000000)
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#define HFCGMH_VAL 0x0B
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#define HFCGML_VAL 0x72
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#elif (OFMCLK == 40000000)
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#define HFCGMH_VAL 0x09
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#define HFCGML_VAL 0x89
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#elif (OFMCLK == 33000000)
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#define HFCGMH_VAL 0x07
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#define HFCGML_VAL 0xDE
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#else
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#error "Unsupported OFMCLK Frequency"
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#endif
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/* Clock prescaler configurations in different series */
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#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
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#if defined(FIU1DIV_VAL)
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#define VAL_HFCBCD ((FIU1DIV_VAL << 4) | (FIUDIV_VAL << 2))
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#else
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#define VAL_HFCBCD (FIUDIV_VAL << 4)
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#endif /* FIU1DIV_VAL */
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#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
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#if defined(APB4DIV_VAL)
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#define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4))
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#else
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#define VAL_HFCBCD2 APB3DIV_VAL
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#endif /* APB4DIV_VAL */
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/**
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* @brief Function to notify clock driver that backup the counter value of
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* low-frequency timer before ec entered deep idle state.
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