soc: riscv: Add initial support for Efinix Sapphire SoC

- It's a riscv privilege spec SoC

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>

soc/riscv/riscv-privileged/efinix-sapphire/CMakeLists.txt

@@ -0,0 +1,4 @@
+# Copyright (c) 2023 Efinix Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)

soc/riscv/riscv-privileged/efinix-sapphire/Kconfig.defconfig.series

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+# Copyright (c) 2023 Efinix Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_EFINIX_SAPPHIRE
+
+config SOC_SERIES
+	default "efinix-sapphire"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 100000000
+
+config RISCV_HAS_CPU_IDLE
+	bool
+
+config RISCV_SOC_INTERRUPT_INIT
+	bool
+	default y
+
+config RISCV_HAS_PLIC
+	bool
+	default y
+
+config NUM_IRQS
+	int
+	default 36
+
+config 2ND_LVL_INTR_00_OFFSET
+	default 11
+
+endif # SOC_SERIES_EFINIX_SAPPHIRE

soc/riscv/riscv-privileged/efinix-sapphire/Kconfig.series

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+# Copyright (c) 2023 Efinix Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_EFINIX_SAPPHIRE
+	bool "Efinix Sapphire SOC implementation"
+	select RISCV
+	select SOC_FAMILY_RISCV_PRIVILEGED
+	help
+	  Enable support for Efinix Sapphire SOC implementation

soc/riscv/riscv-privileged/efinix-sapphire/Kconfig.soc

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+# Copyright (c) 2023 Efinix Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "Efinix SoC selection"
+	depends on SOC_SERIES_EFINIX_SAPPHIRE
+
+config SOC_RISCV32_EFINIX_SAPPHIRE
+	bool "Efinix Sapphire VexRiscv system implementation"
+	select ATOMIC_OPERATIONS_BUILTIN
+	select INCLUDE_RESET_VECTOR
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+
+endchoice

soc/riscv/riscv-privileged/efinix-sapphire/linker.ld

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+# SPDX-License-Identifier: Apache-2.0
+
+#include <zephyr/arch/riscv/common/linker.ld>

soc/riscv/riscv-privileged/efinix-sapphire/soc.h

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+/*
+ * Copyright (c) 2023 Efinix Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __RISCV32_EFINIX_SAPPHIRE_SOC_H_
+#define __RISCV32_EFINIX_SAPPHIRE_SOC_H_
+
+#include "soc_common.h"
+#include <zephyr/arch/common/sys_io.h>
+#include <zephyr/devicetree.h>
+
+#ifndef _ASMLANGUAGE
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* __RISCV32_EFINIX_SAPPHIRE_SOC_H_ */