boards: arm: add efm32gg_sltb009a board
- Add Silabs SLTB009A board - Add Silabs EFM32GG12B SoC Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This commit is contained in:
Wojciech Sipak
Carles Cufí
parent
b9b42bb832
commit
e9613856cb
15 changed files with 637 additions and 0 deletions
8
boards/arm/efm32gg_sltb009a/Kconfig.board
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8
boards/arm/efm32gg_sltb009a/Kconfig.board
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# EFM32GG SLTB009A board configuration
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_EFM32GG_SLTB009A
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bool "SiLabs EFM32GG-SLTB009A (Giant Gecko 12)"
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depends on SOC_SERIES_EFM32GG12B
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select SOC_PART_NUMBER_EFM32GG12B810F1024GM64
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24
boards/arm/efm32gg_sltb009a/Kconfig.defconfig
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24
boards/arm/efm32gg_sltb009a/Kconfig.defconfig
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# EFM32GG SLTB009A default board configuration
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_EFM32GG_SLTB009A
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config BOARD
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string
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default "efm32gg_sltb009a"
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config CMU_HFXO_FREQ
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default 50000000
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config CMU_HFRCO_FREQ
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default 72000000
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config CMU_LFXO_FREQ
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default 32768
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config LOG_BACKEND_SWO_FREQ_HZ
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default 875000
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depends on LOG_BACKEND_SWO
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endif # BOARD_EFM32GG_SLTB009A
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5
boards/arm/efm32gg_sltb009a/board.cmake
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5
boards/arm/efm32gg_sltb009a/board.cmake
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@ -0,0 +1,5 @@
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(jlink "--device=EFM32GG12B810F1024")
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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152
boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.dts
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152
boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.dts
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/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <silabs/efm32gg12b810f1024gm64.dtsi>
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/ {
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model = "Silicon Labs EFM32GG SLTB009A board";
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compatible = "silabs,efm32gg_sltb009a";
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chosen {
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zephyr,console = &usart0;
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zephyr,shell-uart = &usart0;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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};
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/* These aliases are provided for compatibility with samples */
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aliases {
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led0 = &led0;
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led1 = &led1;
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sw0 = &button0;
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sw1 = &button1;
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watchdog0 = &wdog0;
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};
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leds {
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compatible = "gpio-leds";
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led0: led_0 {
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gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
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label = "LED 0";
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};
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led1: led_1 {
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gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>;
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label = "LED 1";
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};
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};
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buttons {
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compatible = "gpio-keys";
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button0: button_0 {
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gpios = <&gpiod 5 GPIO_ACTIVE_HIGH>;
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label = "User Push Button 0";
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};
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button1: button_1 {
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gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>;
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label = "User Push Button 1";
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};
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};
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};
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&usart0 {
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current-speed = <115200>;
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location-rx = <GECKO_LOCATION(1) GECKO_PORT_E GECKO_PIN(6)>;
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location-tx = <GECKO_LOCATION(1) GECKO_PORT_E GECKO_PIN(7)>;
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status = "okay";
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};
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&usart4 {
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current-speed = <115200>;
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location-rx = <GECKO_LOCATION(0) GECKO_PORT_B GECKO_PIN(8)>;
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location-tx = <GECKO_LOCATION(0) GECKO_PORT_B GECKO_PIN(7)>;
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status = "okay";
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};
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&leuart0 {
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current-speed = <9600>;
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location-rx = <GECKO_LOCATION(1) GECKO_PORT_B GECKO_PIN(14)>;
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location-tx = <GECKO_LOCATION(1) GECKO_PORT_B GECKO_PIN(13)>;
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status = "okay";
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};
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&i2c0 {
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location-sda = <GECKO_LOCATION(4) GECKO_PORT_C GECKO_PIN(0)>;
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location-scl = <GECKO_LOCATION(4) GECKO_PORT_C GECKO_PIN(1)>;
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status = "okay";
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};
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&i2c1 {
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location-sda = <GECKO_LOCATION(0) GECKO_PORT_C GECKO_PIN(4)>;
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location-scl = <GECKO_LOCATION(0) GECKO_PORT_C GECKO_PIN(5)>;
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status = "okay";
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};
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&rtcc0 {
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prescaler = <1>;
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status = "okay";
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};
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&gpioa {
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status = "okay";
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board-controller-enable {
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// VCOM Isolation. Set PA15 to HIGH to enable VCOM_{RX,TX}.
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gpio-hog;
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gpios = <15 GPIO_ACTIVE_HIGH>;
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output-high;
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};
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};
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&gpio {
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location-swo = <0>;
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status = "okay";
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};
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&gpiob {
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status = "okay";
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};
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&gpioc {
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status = "okay";
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};
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&gpiod {
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status = "okay";
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};
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&gpioe {
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status = "okay";
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};
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&gpiof {
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status = "okay";
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};
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&flash0 {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Set 12Kb of storage at the end of the 2048Kb of flash */
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storage_partition: partition@1fd000 {
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label = "storage";
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reg = <0x001fd000 0x00003000>;
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};
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};
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};
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&wdog0 {
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status = "okay";
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};
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&trng0 {
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status = "okay";
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};
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&cpu0 {
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clock-frequency = <72000000>;
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};
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15
boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.yaml
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15
boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.yaml
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identifier: efm32gg_sltb009a
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name: EFM32GG-SLTB009A
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type: mcu
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arch: arm
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ram: 192
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flash: 1024
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toolchain:
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- zephyr
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supported:
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- i2c
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- gpio
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- nvs
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testing:
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ignore_tags:
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- bluetooth
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12
boards/arm/efm32gg_sltb009a/efm32gg_sltb009a_defconfig
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12
boards/arm/efm32gg_sltb009a/efm32gg_sltb009a_defconfig
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_SERIES_EFM32GG12B=y
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CONFIG_BOARD_EFM32GG_SLTB009A=y
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CONFIG_ARM_MPU=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_GPIO=y
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
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CONFIG_CMU_HFCLK_HFRCO=y
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248
dts/arm/silabs/efm32gg12b.dtsi
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248
dts/arm/silabs/efm32gg12b.dtsi
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/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include "gpio_gecko.h"
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/ {
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chosen {
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zephyr,entropy = &trng0;
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zephyr,flash-controller = &msc;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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soc {
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msc: flash-controller@40000000 {
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compatible = "silabs,gecko-flash-controller";
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reg = <0x40000000 0x110>;
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interrupts = <33 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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write-block-size = <4>;
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erase-block-size = <4096>;
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};
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};
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rtcc0: rtcc@40062000 { /* RTCC0 */
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compatible = "silabs,gecko-rtcc";
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reg = <0x40062000 0x184>;
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interrupts = <31 0>;
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clock-frequency = <32768>;
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prescaler = <1>;
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status = "disabled";
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};
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uart0: uart@40014000 { /* UART0 */
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compatible = "silabs,gecko-uart";
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reg = <0x40014000 0x400>;
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interrupts = <21 0 22 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <0>;
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status = "disabled";
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};
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uart1: uart@40014400 { /* UART1 */
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compatible = "silabs,gecko-uart";
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reg = <0x40014400 0x400>;
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interrupts = <23 0 24 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <1>;
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status = "disabled";
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};
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usart0: usart@40010000 { /* USART0 */
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compatible = "silabs,gecko-usart";
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reg = <0x40010000 0x400>;
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interrupts = <6 0 7 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <0>;
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status = "disabled";
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};
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usart1: usart@40010400 { /* USART1 */
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compatible = "silabs,gecko-usart";
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reg = <0x40010400 0x400>;
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interrupts = <17 0 18 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <1>;
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status = "disabled";
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};
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usart2: usart@40010800 { /* USART2 */
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compatible = "silabs,gecko-usart";
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reg = <0x40010800 0x400>;
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interrupts = <19 0 20 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <2>;
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status = "disabled";
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};
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usart3: usart@40010c00 { /* USART3 */
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compatible = "silabs,gecko-usart";
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reg = <0x40010c00 0x400>;
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interrupts = <37 0 38 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <3>;
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status = "disabled";
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};
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usart4: usart@40011000 { /* USART4 */
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compatible = "silabs,gecko-usart";
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reg = <0x40011000 0x400>;
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interrupts = <39 0 40 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <4>;
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status = "disabled";
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};
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leuart0: leuart@4006a000 { /* LEUART0 */
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compatible = "silabs,gecko-leuart";
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reg = <0x4006a000 0x400>;
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interrupts = <25 0>;
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peripheral-id = <0>;
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status = "disabled";
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};
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leuart1: leuart@4006a400 { /* LEUART1 */
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compatible = "silabs,gecko-leuart";
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reg = <0x4006a400 0x400>;
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interrupts = <26 0>;
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peripheral-id = <1>;
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status = "disabled";
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};
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i2c0: i2c@40089000 {
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compatible = "silabs,gecko-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40089000 0x400>;
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interrupts = <11 0>;
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status = "disabled";
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};
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i2c1: i2c@40089400 {
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compatible = "silabs,gecko-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40089400 0x400>;
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interrupts = <12 0>;
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status = "disabled";
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};
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gpio: gpio@40088400 {
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compatible = "silabs,gecko-gpio";
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reg = <0x40088400 0xc00>;
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interrupts = <3 2 13 2>;
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interrupt-names = "GPIO_EVEN", "GPIO_ODD";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@40088000 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x40088000 0x30>;
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peripheral-id = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiob: gpio@40088030 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x40088030 0x30>;
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peripheral-id = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpioc: gpio@40088060 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x40088060 0x30>;
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peripheral-id = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiod: gpio@40088090 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x40088090 0x30>;
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peripheral-id = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpioe: gpio@400880c0 {
|
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compatible = "silabs,gecko-gpio-port";
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reg = <0x400880c0 0x30>;
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peripheral-id = <4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiof: gpio@400880f0 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x400880f0 0x30>;
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peripheral-id = <5>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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};
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trng0: trng@4001d000 {
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compatible = "silabs,gecko-trng";
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reg = <0x4001d000 0x400>;
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interrupts = <57 0>;
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status = "disabled";
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};
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wdog0: wdog@40052000 {
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compatible = "silabs,gecko-wdog";
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reg = <0x40052000 0x2C>;
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peripheral-id = <0>;
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interrupts = <1 0>;
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status = "disabled";
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};
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wdog1: wdog@40052400 {
|
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compatible = "silabs,gecko-wdog";
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reg = <0x40052400 0x2C>;
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peripheral-id = <1>;
|
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interrupts = <55 0>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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26
dts/arm/silabs/efm32gg12b810f1024gm64.dtsi
Normal file
26
dts/arm/silabs/efm32gg12b810f1024gm64.dtsi
Normal file
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|
@ -0,0 +1,26 @@
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/*
|
||||
* Copyright (c) 2023 Antmicro <www.antmicro.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <silabs/efm32gg12b.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(192)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "silabs,efm32gg12b", "silabs,efm32gg12",
|
||||
"silabs,efm32", "simple-bus";
|
||||
|
||||
flash-controller@40000000 {
|
||||
flash0: flash@0 {
|
||||
reg = <0 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
# Silicon Labs EFM32GG12B (Giant Gecko) platform configuration options
|
||||
# Copyright (c) 2023 Antmicro <www.antmicro.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config GPIO_GECKO
|
||||
default y
|
||||
depends on GPIO || LOG_BACKEND_SWO
|
||||
20
soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.series
Normal file
20
soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.series
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
# EFM32GG12B series configuration options
|
||||
# Copyright (c) 2023 Antmicro <www.antmicro.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_EFM32GG12B
|
||||
|
||||
config SOC_SERIES
|
||||
default "efm32gg12b"
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "EFM32GG12B810F1024GM64" if SOC_PART_NUMBER_EFM32GG12B810F1024GM64
|
||||
|
||||
config NUM_IRQS
|
||||
int
|
||||
# must be >= the highest interrupt number used
|
||||
default 68
|
||||
|
||||
source "soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.efm32gg12b"
|
||||
|
||||
endif # SOC_SERIES_EFM32GG12B
|
||||
21
soc/arm/silabs_exx32/efm32gg12b/Kconfig.series
Normal file
21
soc/arm/silabs_exx32/efm32gg12b/Kconfig.series
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
# EFM32GG12B (Giant Gecko) MCU line
|
||||
# Copyright (c) 2023 Antmicro <www.antmicro.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_EFM32GG12B
|
||||
bool "EFM32GG12B Series MCU"
|
||||
select ARM
|
||||
select HAS_SILABS_GECKO
|
||||
select HAS_SWO
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
select SOC_FAMILY_EXX32
|
||||
select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
|
||||
select SOC_GECKO_HAS_HFRCO_FREQRANGE
|
||||
select SOC_GECKO_CMU
|
||||
select SOC_GECKO_EMU
|
||||
select SOC_GECKO_GPIO
|
||||
select SOC_GECKO_TRNG
|
||||
help
|
||||
Enable support for EFM32 GiantGecko MCU series
|
||||
7
soc/arm/silabs_exx32/efm32gg12b/Kconfig.soc
Normal file
7
soc/arm/silabs_exx32/efm32gg12b/Kconfig.soc
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
# EFM32GG12B (Giant Gecko) MCU line
|
||||
# Copyright (c) 2023 Antmicro <www.antmicro.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_PART_NUMBER_EFM32GG12B810F1024GM64
|
||||
bool
|
||||
depends on SOC_SERIES_EFM32GG12B
|
||||
14
soc/arm/silabs_exx32/efm32gg12b/linker.ld
Normal file
14
soc/arm/silabs_exx32/efm32gg12b/linker.ld
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Antmicro <www.antmicro.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Linker command/script file
|
||||
*
|
||||
* This is the linker script for both standard images.
|
||||
*/
|
||||
|
||||
#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>
|
||||
37
soc/arm/silabs_exx32/efm32gg12b/soc.h
Normal file
37
soc/arm/silabs_exx32/efm32gg12b/soc.h
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Antmicro <www.antmicro.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Board configuration macros for the EFM32GG12B SoC family.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SOC__H_
|
||||
#define _SOC__H_
|
||||
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <em_bus.h>
|
||||
#include <em_common.h>
|
||||
|
||||
|
||||
#include "soc_pinmap.h"
|
||||
#include "../common/soc_gpio.h"
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC__H_ */
|
||||
41
soc/arm/silabs_exx32/efm32gg12b/soc_pinmap.h
Normal file
41
soc/arm/silabs_exx32/efm32gg12b/soc_pinmap.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Antmicro <www.antmicro.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief Silabs EFM32GG12B MCU pin definitions.
|
||||
*
|
||||
* This file contains pin configuration data required by different MCU
|
||||
* modules to correctly configure GPIO controller.
|
||||
*/
|
||||
|
||||
#ifndef _SILABS_EFM32GG12B_SOC_PINMAP_H_
|
||||
#define _SILABS_EFM32GG12B_SOC_PINMAP_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <soc.h>
|
||||
#include <em_gpio.h>
|
||||
|
||||
#define GPIO_NODE DT_INST(0, silabs_gecko_gpio)
|
||||
#if DT_NODE_HAS_PROP(GPIO_NODE, location_swo)
|
||||
#define SWO_LOCATION DT_PROP(GPIO_NODE, location_swo)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIO_GECKO
|
||||
/* Serial Wire Output (SWO) */
|
||||
#if (SWO_LOCATION == 0)
|
||||
#define PIN_SWO {gpioPortF, 2, gpioModePushPull, 1}
|
||||
#elif (SWO_LOCATION == 1)
|
||||
#define PIN_SWO {gpioPortC, 15, gpioModePushPull, 1}
|
||||
#elif (SWO_LOCATION == 2)
|
||||
#define PIN_SWO {gpioPortD, 1, gpioModePushPull, 1}
|
||||
#elif (SWO_LOCATION == 3)
|
||||
#define PIN_SWO {gpioPortD, 2, gpioModePushPull, 1}
|
||||
#elif (SWO_LOCATION >= 4)
|
||||
#error ("Invalid SWO pin location")
|
||||
#endif
|
||||
#endif /* CONFIG_GPIO_GECKO */
|
||||
|
||||
#endif /* _SILABS_EFM32GG12B_SOC_PINMAP_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue