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soc: stm32: unify cache conditionals for F7 and H7 targets

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The instruction cache in the STM32F7 and H7 was enabled regardless
of the value assigned via Kconfig to the CONFIG_ICACHE parameter.
This commit adds the missing conditional checks; note that this does
not affect the compiled behavior unless CONFIG_ICACHE is explicitly
disabled by the user.

Remove a redundant low-level check on DCache being already enabled,
since it is also performed inside the SCB_EnableDCache function.

Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
This commit is contained in:
Luca Burelli 2023-11-30 14:32:05 +01:00 • committed by Fabio Baltieri
commit 11d4f8e5e5
2 changed files with 8 additions and 8 deletions
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8
soc/arm/st_stm32/stm32f7/soc.c
View file

@ -30,12 +30,12 @@ static int st_stm32f7_init(void)
/* Enable ART Flash cache accelerator */
LL_FLASH_EnableART();
SCB_EnableICache();
if (IS_ENABLED(CONFIG_ICACHE)) {
SCB_EnableICache();
}
if (IS_ENABLED(CONFIG_DCACHE)) {
if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
SCB_EnableDCache();
}
SCB_EnableDCache();
}
/* Update CMSIS SystemCoreClock variable (HCLK) */

8
soc/arm/st_stm32/stm32h7/soc_m7.c
View file

@ -54,12 +54,12 @@ static int stm32h7_m4_wakeup(void)
*/
static int stm32h7_init(void)
{
SCB_EnableICache();
if (IS_ENABLED(CONFIG_ICACHE)) {
SCB_EnableICache();
}
if (IS_ENABLED(CONFIG_DCACHE)) {
if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
SCB_EnableDCache();
}
SCB_EnableDCache();
}
/* Update CMSIS SystemCoreClock variable (HCLK) */