soc: stm32: unify cache conditionals for F7 and H7 targets
The instruction cache in the STM32F7 and H7 was enabled regardless of the value assigned via Kconfig to the CONFIG_ICACHE parameter. This commit adds the missing conditional checks; note that this does not affect the compiled behavior unless CONFIG_ICACHE is explicitly disabled by the user. Remove a redundant low-level check on DCache being already enabled, since it is also performed inside the SCB_EnableDCache function. Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
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2 changed files with 8 additions and 8 deletions
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@ -30,12 +30,12 @@ static int st_stm32f7_init(void)
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/* Enable ART Flash cache accelerator */
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LL_FLASH_EnableART();
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SCB_EnableICache();
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if (IS_ENABLED(CONFIG_ICACHE)) {
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SCB_EnableICache();
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}
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if (IS_ENABLED(CONFIG_DCACHE)) {
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if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
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SCB_EnableDCache();
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}
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SCB_EnableDCache();
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}
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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@ -54,12 +54,12 @@ static int stm32h7_m4_wakeup(void)
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*/
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static int stm32h7_init(void)
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{
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SCB_EnableICache();
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if (IS_ENABLED(CONFIG_ICACHE)) {
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SCB_EnableICache();
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}
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if (IS_ENABLED(CONFIG_DCACHE)) {
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if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
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SCB_EnableDCache();
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}
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SCB_EnableDCache();
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}
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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