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soc: atmel_sam0: Setup clocks for USB on SAML21 parts

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GCLK Gen 2 was dedicated to USB, but never setup... this patch
configures it for 48 MHz, derrived from DFLL.

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
This commit is contained in:
Attie Grande 2023-11-26 15:37:34 +00:00 • committed by Maureen Helm
commit 9f76adbfa8
1 changed files with 13 additions and 0 deletions
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13
soc/arm/atmel_sam0/common/soc_saml2x.c
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@ -215,6 +215,18 @@ static inline void gclk_main_configure(void)
GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_DFLL48M_Val;
}
#if !CONFIG_USB_DC_SAM0
#define gclk_usb_configure()
#else
static inline void gclk_usb_configure(void)
{
GCLK->GENCTRL[2].reg = 0
| GCLK_GENCTRL_SRC_DFLL48M
| GCLK_GENCTRL_DIV(1)
| GCLK_GENCTRL_GENEN;
}
#endif
#if !CONFIG_ADC_SAM0
#define gclk_adc_configure()
#else
@ -255,5 +267,6 @@ void z_arm_platform_init(void)
flash_waitstates_init();
pm_init();
gclk_main_configure();
gclk_usb_configure();
gclk_adc_configure();
}