soc: atmel_sam0: Setup clocks for USB on SAML21 parts
GCLK Gen 2 was dedicated to USB, but never setup... this patch configures it for 48 MHz, derrived from DFLL. Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
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@ -215,6 +215,18 @@ static inline void gclk_main_configure(void)
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GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_DFLL48M_Val;
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}
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#if !CONFIG_USB_DC_SAM0
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#define gclk_usb_configure()
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#else
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static inline void gclk_usb_configure(void)
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{
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GCLK->GENCTRL[2].reg = 0
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| GCLK_GENCTRL_SRC_DFLL48M
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| GCLK_GENCTRL_DIV(1)
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| GCLK_GENCTRL_GENEN;
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}
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#endif
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#if !CONFIG_ADC_SAM0
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#define gclk_adc_configure()
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#else
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@ -255,5 +267,6 @@ void z_arm_platform_init(void)
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flash_waitstates_init();
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pm_init();
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gclk_main_configure();
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gclk_usb_configure();
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gclk_adc_configure();
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}
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