soc: arm: nxp: lpc55xxx: Change PLL1 frequency to 144 MHz
Reduce the main clock frequency from 150MHz to 144MHz which allows meeting the full range of CAN bitrates. Fixes: #60811 Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
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1 changed files with 4 additions and 4 deletions
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@ -66,8 +66,8 @@ const pll_setup_t pll1Setup = {
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SYSCON_PLL1CTRL_SELP(31U),
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.pllndec = SYSCON_PLL1NDEC_NDIV(8U),
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.pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
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.pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
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.pllRate = 150000000U,
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.pllmdec = SYSCON_PLL1MDEC_MDIV(144U),
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.pllRate = 144000000U,
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.flags = PLL_SETUPFLAG_WAITLOCK
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};
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#endif
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@ -103,11 +103,11 @@ static ALWAYS_INLINE void clock_init(void)
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SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;
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ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
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/* Setting the Core Clock to either 96MHz or in the case of using PLL, 150MHz */
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/* Setting the Core Clock to either 96MHz or in the case of using PLL, 144MHz */
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#if defined(CONFIG_SOC_LPC55S06) || !defined(CONFIG_INIT_PLL1)
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SystemCoreClock = 96000000U;
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#else
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SystemCoreClock = 150000000U;
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SystemCoreClock = 144000000U;
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#endif
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