driver: flash: npcx: add support for npcx4 series
This CL introduces new Flash Interface Unit (FIU) hardware in npcx4 series. The different operations of npcx9 and npcx4 FIU include: 1. 4-byte mode support for DRA mode move to SPI_DEV reg 2. To access the second flash in DRA mode, we need to configure SPI_DEV_SEL field in BURST_CFG additionally. Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
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4 changed files with 68 additions and 14 deletions
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@ -96,11 +96,43 @@ static inline void qspi_npcx_config_uma_mode(const struct device *dev,
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}
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}
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static inline void qspi_npcx_config_dra_4byte_mode(const struct device *dev,
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const struct npcx_qspi_cfg *qspi_cfg)
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{
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#if !defined(CONFIG_SOC_SERIES_NPCX7) /* NPCX7 doesn't support this feature */
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struct fiu_reg *const inst = HAL_INSTANCE(dev);
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#if defined(CONFIG_SOC_SERIES_NPCX9)
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if (qspi_cfg->enter_4ba != 0) {
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if ((qspi_cfg->flags & NPCX_QSPI_SEC_FLASH_SL) != 0) {
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inst->SPI1_DEV |= BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS11);
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} else {
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inst->SPI1_DEV |= BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS10);
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}
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} else {
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inst->SPI1_DEV &= ~(BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS11) |
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BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS10));
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}
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#elif defined(CONFIG_SOC_SERIES_NPCX4)
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if (qspi_cfg->enter_4ba != 0) {
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SET_FIELD(inst->SPI_DEV, NPCX_SPI_DEV_NADDRB, NPCX_DEV_NUM_ADDR_4BYTE);
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}
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#endif
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#endif /* CONFIG_SOC_SERIES_NPCX7 */
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}
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static inline void qspi_npcx_config_dra_mode(const struct device *dev,
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const struct npcx_qspi_cfg *qspi_cfg)
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{
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struct fiu_reg *const inst = HAL_INSTANCE(dev);
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/* Select SPI device number for DRA mode in npcx4 series */
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX4)) {
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int spi_dev_num = (qspi_cfg->flags & NPCX_QSPI_SEC_FLASH_SL) != 0 ? 1 : 0;
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SET_FIELD(inst->BURST_CFG, NPCX_BURST_CFG_SPI_DEV_SEL, spi_dev_num);
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}
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/* Enable quad mode of Direct Read Mode if needed */
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if (qspi_cfg->qer_type != JESD216_DW15_QER_NONE) {
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inst->RESP_CFG |= BIT(NPCX_RESP_CFG_QUAD_EN);
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@ -112,18 +144,7 @@ static inline void qspi_npcx_config_dra_mode(const struct device *dev,
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SET_FIELD(inst->SPI_FL_CFG, NPCX_SPI_FL_CFG_RD_MODE, qspi_cfg->rd_mode);
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/* Enable/Disable 4 byte address mode for Direct Read Access (DRA) */
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#if !defined(CONFIG_SOC_SERIES_NPCX7) /* NPCX7 doesn't support this feature */
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if (qspi_cfg->enter_4ba != 0) {
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if ((qspi_cfg->flags & NPCX_QSPI_SEC_FLASH_SL) != 0) {
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inst->SPI1_DEV |= BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS11);
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} else {
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inst->SPI1_DEV |= BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS10);
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}
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} else {
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inst->SPI1_DEV &= ~(BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS11) |
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BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS10));
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}
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#endif /* CONFIG_SOC_SERIES_NPCX7 */
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qspi_npcx_config_dra_4byte_mode(dev, qspi_cfg);
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}
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static inline void qspi_npcx_fiu_set_operation(const struct device *dev, uint32_t operation)
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@ -249,11 +270,16 @@ static int qspi_npcx_fiu_init(const struct device *dev)
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/* Enable direct access for 2 external SPI devices */
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if (config->en_direct_access_2dev) {
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) {
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX9) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX4)) {
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inst->FIU_EXT_CFG |= BIT(NPCX_FIU_EXT_CFG_SPI1_2DEV);
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}
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}
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/* Make sure there is no address field (UMA_ADDR_SIZE is zero) in UMA mode */
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX4)) {
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SET_FIELD(inst->UMA_ECTS, NPCX_UMA_ECTS_UMA_ADDR_SIZE, 0);
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}
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return 0;
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}
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@ -19,6 +19,12 @@ extern "C" {
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#define NPCX_UMA_ACCESS_READ BIT(1)
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#define NPCX_UMA_ACCESS_ADDR BIT(2)
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/* Valid value of Dn_NADDRB that sets the number of address bytes in a transaction */
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#define NPCX_DEV_NUM_ADDR_1BYTE 1
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#define NPCX_DEV_NUM_ADDR_2BYTE 2
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#define NPCX_DEV_NUM_ADDR_3BYTE 3
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#define NPCX_DEV_NUM_ADDR_4BYTE 4
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/* UMA operation configuration for a SPI device */
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struct npcx_uma_cfg {
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uint8_t opcode;
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@ -1533,10 +1533,24 @@ struct fiu_reg {
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volatile uint8_t SPI1_DEV;
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/* 0x03E-0x3F */
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volatile uint8_t reserved9[2];
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#elif defined(CONFIG_SOC_SERIES_NPCX4)
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/* 0x034: UMA address byte 0-3 */
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volatile uint32_t UMA_AB0_3;
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/* 0x038-0x3B */
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volatile uint8_t reserved8[4];
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/* 0x03C: SPI Device */
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volatile uint8_t SPI_DEV;
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/* 0x03D */
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volatile uint8_t reserved9;
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/* 0x03E */
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volatile uint8_t SPI_DEV_SIZE;
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/* 0x03F */
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volatile uint8_t reserved10;
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#endif
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};
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/* FIU register fields */
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#define NPCX_BURST_CFG_SPI_DEV_SEL FIELD(4, 2)
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#define NPCX_RESP_CFG_IAD_EN 0
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#define NPCX_RESP_CFG_DEV_SIZE_EX 2
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#define NPCX_RESP_CFG_QUAD_EN 3
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@ -1550,12 +1564,20 @@ struct fiu_reg {
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#define NPCX_UMA_ECTS_SW_CS1 1
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#define NPCX_UMA_ECTS_SEC_CS 2
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#define NPCX_UMA_ECTS_UMA_LOCK 3
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#define NPCX_UMA_ECTS_UMA_ADDR_SIZE FIELD(4, 3)
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#define NPCX_SPI1_DEV_FOUR_BADDR_CS10 6
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#define NPCX_SPI1_DEV_FOUR_BADDR_CS11 7
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#define NPCX_SPI1_DEV_SPI1_LO_DEV_SIZE FIELD(0, 4)
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#if defined(CONFIG_SOC_SERIES_NPCX9)
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#define NPCX_FIU_EXT_CFG_SPI1_2DEV 7
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#else
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#define NPCX_FIU_EXT_CFG_SPI1_2DEV 6
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#endif
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#define NPCX_FIU_EXT_CFG_SET_DMM_EN 2
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#define NPCX_FIU_EXT_CFG_SET_CMD_EN 1
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#define NPCX_SPI_DEV_NADDRB FIELD(5, 3)
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#define NPCX_MSR_IE_CFG_UMA_BLOCK 3
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/* UMA fields selections */
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#define UMA_FLD_ADDR BIT(NPCX_UMA_CTS_A_SIZE) /* 3-bytes ADR field */
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@ -162,7 +162,7 @@ NPCX_REG_OFFSET_CHECK(ps2_reg, PSISIG, 0x008);
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NPCX_REG_OFFSET_CHECK(ps2_reg, PSIEN, 0x00a);
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/* FIU register structure check */
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#if defined(CONFIG_SOC_SERIES_NPCX9)
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#if defined(CONFIG_SOC_SERIES_NPCX9) || defined(CONFIG_SOC_SERIES_NPCX4)
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NPCX_REG_SIZE_CHECK(fiu_reg, 0x040);
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#else
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NPCX_REG_SIZE_CHECK(fiu_reg, 0x034);
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