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soc: atmel: sam: Fix cache management

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The current platform initialization do not take in consideration cache
management for historic reasons. This fixes any miss configuration and
allow users to enable/disable caches at board definition. The default
value is cache disabled and the below examples are for SAMV71 which
have both I/D Cache available:

I Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE=n

D Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_ICACHE=n

I/D Cache disabled:
CONFIG_ICACHE=n
CONFIG_DCACHE=n

I/D Cache Enabled:
CONFIG_CACHE_MANAGEMENT=y

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke 2023-08-03 12:57:38 +02:00 • committed by Carles Cufí
commit ea24dd40eb
8 changed files with 20 additions and 12 deletions
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1
boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_BOARD_SAM_E70_XPLAINED=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_ARM_MPU=y
CONFIG_CACHE_MANAGEMENT=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_WDT_DISABLE_AT_BOOT=y

1
boards/arm/sam_e70_xplained/sam_e70b_xplained_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_BOARD_SAM_E70_XPLAINED=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_ARM_MPU=y
CONFIG_CACHE_MANAGEMENT=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_WDT_DISABLE_AT_BOOT=y

1
boards/arm/sam_v71_xult/sam_v71_xult_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_BOARD_SAM_V71_XULT=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_ARM_MPU=y
CONFIG_CACHE_MANAGEMENT=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_WDT_DISABLE_AT_BOOT=y

1
boards/arm/sam_v71_xult/sam_v71b_xult_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_BOARD_SAM_V71_XULT=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_ARM_MPU=y
CONFIG_CACHE_MANAGEMENT=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_WDT_DISABLE_AT_BOOT=y

3
soc/arm/atmel_sam/same70/Kconfig.defconfig.series
View file

@ -38,7 +38,4 @@ config NUM_IRQS
default 74 if SOC_ATMEL_SAME70_REVB
default 71
config CACHE_MANAGEMENT
default y
endif # SOC_SERIES_SAME70

11
soc/arm/atmel_sam/same70/soc.c
View file

@ -226,10 +226,15 @@ static ALWAYS_INLINE void clock_init(void)
void z_arm_platform_init(void)
{
SCB_EnableICache();
if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_ICACHE)) {
SCB_EnableICache();
} else {
SCB_DisableICache();
}
if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_DCACHE)) {
SCB_EnableDCache();
} else {
SCB_DisableDCache();
}
/*

3
soc/arm/atmel_sam/samv71/Kconfig.defconfig.series
View file

@ -38,7 +38,4 @@ config NUM_IRQS
default 74 if SOC_ATMEL_SAMV71_REVB
default 71
config CACHE_MANAGEMENT
default y
endif # SOC_SERIES_SAMV71

11
soc/arm/atmel_sam/samv71/soc.c
View file

@ -226,10 +226,15 @@ static ALWAYS_INLINE void clock_init(void)
void z_arm_platform_init(void)
{
SCB_EnableICache();
if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_ICACHE)) {
SCB_EnableICache();
} else {
SCB_DisableICache();
}
if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_DCACHE)) {
SCB_EnableDCache();
} else {
SCB_DisableDCache();
}
/*