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soc: atmel: Enable platform specific init

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This replace pre kernel initialization by the platform specific
initialization call. The platform specific init will configure
at very beginning the clocks, flash wait states and cache.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke 2023-08-03 12:52:57 +02:00 • committed by Carles Cufí
commit 45ad244212
30 changed files with 65 additions and 97 deletions
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1
soc/arm/atmel_sam/sam3x/Kconfig.series
View file

@ -13,6 +13,7 @@ config SOC_SERIES_SAM3X
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select SOC_FAMILY_SAM
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAM3X Cortex-M3 microcontrollers.

15
soc/arm/atmel_sam/sam3x/soc.c
View file

@ -1,6 +1,7 @@
/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -192,15 +193,7 @@ static ALWAYS_INLINE void clock_init(void)
}
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This has to be run at the very beginning thus the init priority is set at
* 0 (zero).
*
* @return 0
*/
static int atmel_sam3x_init(void)
void z_arm_platform_init(void)
{
/*
* Set FWS (Flash Wait State) value before increasing Master Clock
@ -213,8 +206,4 @@ static int atmel_sam3x_init(void)
/* Setup system clocks */
clock_init();
return 0;
}
SYS_INIT(atmel_sam3x_init, PRE_KERNEL_1, 0);

3
soc/arm/atmel_sam/sam4e/Kconfig.series
View file

@ -2,7 +2,7 @@
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# Copyright (c) 2019-2020 Gerson Fernando Budke <nandojve@gmail.com>
# Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM4E
@ -13,6 +13,7 @@ config SOC_SERIES_SAM4E
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select SOC_FAMILY_SAM
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAM4E Cortex-M4 microcontrollers.

16
soc/arm/atmel_sam/sam4e/soc.c
View file

@ -2,7 +2,7 @@
* Copyright (c) 2013-2015 Wind River Systems, Inc.
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2017 Justin Watson
* Copyright (c) 2019 Gerson Fernando Budke
* Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -180,15 +180,7 @@ static ALWAYS_INLINE void clock_init(void)
}
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_sam4e_init(void)
void z_arm_platform_init(void)
{
/*
* Set FWS (Flash Wait State) value before increasing Master Clock
@ -202,8 +194,4 @@ static int atmel_sam4e_init(void)
/* Setup system clocks. */
clock_init();
return 0;
}
SYS_INIT(atmel_sam4e_init, PRE_KERNEL_1, 0);

3
soc/arm/atmel_sam/sam4l/Kconfig.series
View file

@ -1,4 +1,4 @@
# Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
# Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM4L
@ -8,6 +8,7 @@ config SOC_SERIES_SAM4L
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select SOC_FAMILY_SAM
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAM4L Cortex-M4 microcontrollers.

16
soc/arm/atmel_sam/sam4l/soc.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
@ -253,15 +253,7 @@ static ALWAYS_INLINE void clock_init(void)
PM->MCCTRL = OSC_SRC_PLL0;
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_sam4l_init(void)
void z_arm_platform_init(void)
{
#if defined(CONFIG_WDT_DISABLE_AT_BOOT)
wdt_set_ctrl(WDT->CTRL & ~WDT_CTRL_EN);
@ -272,8 +264,4 @@ static int atmel_sam4l_init(void)
/* Setup system clocks. */
clock_init();
return 0;
}
SYS_INIT(atmel_sam4l_init, PRE_KERNEL_1, 0);

3
soc/arm/atmel_sam/sam4s/Kconfig.series
View file

@ -2,7 +2,7 @@
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
# Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM4S
@ -12,6 +12,7 @@ config SOC_SERIES_SAM4S
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select SOC_FAMILY_SAM
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAM4S Cortex-M4 microcontrollers.

15
soc/arm/atmel_sam/sam4s/soc.c
View file

@ -2,6 +2,7 @@
* Copyright (c) 2013-2015 Wind River Systems, Inc.
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2017 Justin Watson
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -179,15 +180,7 @@ static ALWAYS_INLINE void clock_init(void)
}
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_sam4s_init(void)
void z_arm_platform_init(void)
{
/*
* Set FWS (Flash Wait State) value before increasing Master Clock
@ -202,8 +195,4 @@ static int atmel_sam4s_init(void)
/* Setup system clocks. */
clock_init();
return 0;
}
SYS_INIT(atmel_sam4s_init, PRE_KERNEL_1, 0);

1
soc/arm/atmel_sam/same70/Kconfig.defconfig.series
View file

@ -1,6 +1,7 @@
# Atmel SAM E70 MCU series configuration options
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAME70

1
soc/arm/atmel_sam/same70/Kconfig.series
View file

@ -12,6 +12,7 @@ config SOC_SERIES_SAME70
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU_DOUBLE_PRECISION
select SOC_FAMILY_SAM
select PLATFORM_SPECIFIC_INIT
select ASF
select HAS_SWO
select XIP

22
soc/arm/atmel_sam/same70/soc.c
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016 Piotr Mienkowski
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
@ -223,15 +224,7 @@ static ALWAYS_INLINE void clock_init(void)
}
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run at the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_same70_init(void)
void z_arm_platform_init(void)
{
SCB_EnableICache();
@ -249,7 +242,18 @@ static int atmel_same70_init(void)
/* Setup system clocks */
clock_init();
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run at the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_same70_init(void)
{
/* Check that the CHIP CIDR matches the HAL one */
if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",

2
soc/arm/atmel_sam/samv71/Kconfig.defconfig.series
View file

@ -1,7 +1,7 @@
# Atmel SAM V71 MCU series configuration options
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2019 Gerson Fernando Budke
# Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAMV71

1
soc/arm/atmel_sam/samv71/Kconfig.series
View file

@ -12,6 +12,7 @@ config SOC_SERIES_SAMV71
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU_DOUBLE_PRECISION
select SOC_FAMILY_SAM
select PLATFORM_SPECIFIC_INIT
select ASF
select HAS_SWO
select XIP

23
soc/arm/atmel_sam/samv71/soc.c
View file

@ -1,6 +1,6 @@
/*
* Copyright (c) 2016 Piotr Mienkowski
* Copyright (c) 2019 Gerson Fernando Budke
* Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
@ -224,15 +224,7 @@ static ALWAYS_INLINE void clock_init(void)
}
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run at the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_samv71_init(void)
void z_arm_platform_init(void)
{
SCB_EnableICache();
@ -250,7 +242,18 @@ static int atmel_samv71_init(void)
/* Setup system clocks */
clock_init();
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run at the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_samv71_init(void)
{
/* Check that the CHIP CIDR matches the HAL one */
if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",

7
soc/arm/atmel_sam0/common/soc_samc2x.c
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2022 Kamil Serwus
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -42,14 +43,10 @@ static void gclks_init(void)
| GCLK_GENCTRL_GENEN;
}
static int atmel_samc_init(void)
void z_arm_platform_init(void)
{
flash_waitstates_init();
osc48m_init();
mclk_init();
gclks_init();
return 0;
}
SYS_INIT(atmel_samc_init, PRE_KERNEL_1, 0);

7
soc/arm/atmel_sam0/common/soc_samd2x.c
View file

@ -1,6 +1,7 @@
/*
* Copyright (c) 2017 Google LLC.
* Copyright (c) 2023 Ionut Catalin Pavel <iocapa@iocapa.com>
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -254,7 +255,7 @@ static inline void osc8m_disable(void)
}
#endif
static int atmel_samd_init(void)
void z_arm_platform_init(void)
{
osc8m_init();
osc32k_init();
@ -265,8 +266,4 @@ static int atmel_samd_init(void)
gclk_main_configure();
gclk_adc_configure();
osc8m_disable();
return 0;
}
SYS_INIT(atmel_samd_init, PRE_KERNEL_1, 0);

7
soc/arm/atmel_sam0/common/soc_samd5x.c
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2019 ML!PA Consulting GmbH
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -104,7 +105,7 @@ static void gclk_connect(uint8_t gclk, uint8_t src, uint8_t div)
| GCLK_GENCTRL_GENEN;
}
static int atmel_samd_init(void)
void z_arm_platform_init(void)
{
uint8_t dfll_div;
@ -129,8 +130,4 @@ static int atmel_samd_init(void)
/* connect GCLK2 to 48 MHz DFLL for USB */
gclk_connect(2, GCLK_SOURCE_DFLL48M, 0);
return 0;
}
SYS_INIT(atmel_samd_init, PRE_KERNEL_1, 0);

7
soc/arm/atmel_sam0/common/soc_saml2x.c
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2021 Argentum Systems Ltd.
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -242,7 +243,7 @@ static inline void pause_for_debug(void)
static inline void pause_for_debug(void) {}
#endif
static int atmel_saml_init(void)
void z_arm_platform_init(void)
{
pause_for_debug();
@ -255,8 +256,4 @@ static int atmel_saml_init(void)
pm_init();
gclk_main_configure();
gclk_adc_configure();
return 0;
}
SYS_INIT(atmel_saml_init, PRE_KERNEL_1, 0);

1
soc/arm/atmel_sam0/samc20/Kconfig.series
View file

@ -11,6 +11,7 @@ config SOC_SERIES_SAMC20
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAMC20 Cortex-M0+ microcontrollers.

1
soc/arm/atmel_sam0/samc21/Kconfig.series
View file

@ -11,6 +11,7 @@ config SOC_SERIES_SAMC21
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAMC21 Cortex-M0+ microcontrollers.

1
soc/arm/atmel_sam0/samd20/Kconfig.series
View file

@ -11,6 +11,7 @@ config SOC_SERIES_SAMD20
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAMD20 Cortex-M0+ microcontrollers.

1
soc/arm/atmel_sam0/samd21/Kconfig.series
View file

@ -11,6 +11,7 @@ config SOC_SERIES_SAMD21
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAMD21 Cortex-M0+ microcontrollers.

1
soc/arm/atmel_sam0/samd51/Kconfig.series
View file

@ -12,6 +12,7 @@ config SOC_SERIES_SAMD51
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAMD51 Cortex-M4F microcontrollers.

1
soc/arm/atmel_sam0/same51/Kconfig.series
View file

@ -12,6 +12,7 @@ config SOC_SERIES_SAME51
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAME51 Cortex-M4F microcontrollers.

1
soc/arm/atmel_sam0/same53/Kconfig.series
View file

@ -12,6 +12,7 @@ config SOC_SERIES_SAME53
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAME53 Cortex-M4F microcontrollers.

1
soc/arm/atmel_sam0/same54/Kconfig.series
View file

@ -12,6 +12,7 @@ config SOC_SERIES_SAME54
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAME54 Cortex-M4F microcontrollers.

1
soc/arm/atmel_sam0/saml21/Kconfig.series
View file

@ -11,6 +11,7 @@ config SOC_SERIES_SAML21
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAML21 Cortex-M0+ microcontrollers.

1
soc/arm/atmel_sam0/samr21/Kconfig.series
View file

@ -11,6 +11,7 @@ config SOC_SERIES_SAMR21
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAMR21 Cortex-M0+ microcontrollers.

1
soc/arm/atmel_sam0/samr34/Kconfig.series
View file

@ -11,6 +11,7 @@ config SOC_SERIES_SAMR34
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAMR34 Cortex-M0+ microcontrollers.

1
soc/arm/atmel_sam0/samr35/Kconfig.series
View file

@ -11,6 +11,7 @@ config SOC_SERIES_SAMR35
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select SOC_FAMILY_SAM0
select PLATFORM_SPECIFIC_INIT
select ASF
help
Enable support for Atmel SAMR35 Cortex-M0+ microcontrollers.