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soc: arm: use sys_cache* for enabling the caches on same70 and samv71

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Use the sys_cache* functions to enable the caches on same70 and
samv71. This will ensure that CONFIG_CACHE_MANAGEMENT is
considered correctly.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This commit is contained in:
Benedikt Schmidt 2023-12-18 10:53:02 +01:00 • committed by Carles Cufí
commit 8b4516226b
4 changed files with 32 additions and 20 deletions
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1
soc/arm/atmel_sam/same70/Kconfig.series
View file

@ -14,6 +14,7 @@ config SOC_SERIES_SAME70
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select SOC_FAMILY_SAM
select INIT_ARCH_HW_AT_BOOT
select PLATFORM_SPECIFIC_INIT
select ASF
select HAS_SWO

25
soc/arm/atmel_sam/same70/soc.c
View file

@ -14,6 +14,8 @@
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/cache.h>
#include <zephyr/arch/cache.h>
#include <soc.h>
#include <cmsis_core.h>
#include <zephyr/logging/log.h>
@ -226,16 +228,19 @@ static ALWAYS_INLINE void clock_init(void)
void z_arm_platform_init(void)
{
if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_ICACHE)) {
SCB_EnableICache();
} else {
SCB_DisableICache();
}
if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_DCACHE)) {
SCB_EnableDCache();
} else {
SCB_DisableDCache();
}
/*
* DTCM is enabled by default at reset, therefore we have to disable
* it first to get the caches into a state where then the
* sys_cache*-functions can enable them, if requested by the
* configuration.
*/
SCB_DisableDCache();
/*
* Enable the caches only if configured to do so.
*/
sys_cache_instr_enable();
sys_cache_data_enable();
/*
* Set FWS (Flash Wait State) value before increasing Master Clock

1
soc/arm/atmel_sam/samv71/Kconfig.series
View file

@ -14,6 +14,7 @@ config SOC_SERIES_SAMV71
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select SOC_FAMILY_SAM
select INIT_ARCH_HW_AT_BOOT
select PLATFORM_SPECIFIC_INIT
select ASF
select HAS_SWO

25
soc/arm/atmel_sam/samv71/soc.c
View file

@ -14,6 +14,8 @@
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/cache.h>
#include <zephyr/arch/cache.h>
#include <soc.h>
#include <cmsis_core.h>
#include <zephyr/logging/log.h>
@ -226,16 +228,19 @@ static ALWAYS_INLINE void clock_init(void)
void z_arm_platform_init(void)
{
if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_ICACHE)) {
SCB_EnableICache();
} else {
SCB_DisableICache();
}
if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_DCACHE)) {
SCB_EnableDCache();
} else {
SCB_DisableDCache();
}
/*
* DTCM is enabled by default at reset, therefore we have to disable
* it first to get the caches into a state where then the
* sys_cache*-functions can enable them, if requested by the
* configuration.
*/
SCB_DisableDCache();
/*
* Enable the caches only if configured to do so.
*/
sys_cache_instr_enable();
sys_cache_data_enable();
/*
* Set FWS (Flash Wait State) value before increasing Master Clock