soc: arm: fix missing configs & defines

Some SoC have missing feature selections in their Kconfig.
Some others are missing includes of CMSIS-Core headers.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>

soc/arm/ambiq/apollo4x/Kconfig.series

@@ -10,6 +10,7 @@ config SOC_SERIES_APOLLO4X
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
 	select SOC_FAMILY_AMBIQ
 	select HAS_SWO
 	select AMBIQ_HAL

soc/arm/arm/designstart/soc.h

@@ -7,7 +7,6 @@
 #ifndef _SOC_H_
 #define _SOC_H_
 
-
-#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
+#include <cmsis_core_m_defaults.h>
 
 #endif /* _SOC_H_ */

soc/arm/arm/musca_s1/Kconfig.soc

@@ -11,5 +11,7 @@ config SOC_V2M_MUSCA_S1
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_ARM_MPU
 	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
 
 endchoice

soc/arm/aspeed/ast10x0/soc.h

@@ -25,4 +25,6 @@
 
 void aspeed_print_sysrst_info(void);
 
+#include <cmsis_core_m_defaults.h>
+
 #endif /* ZEPHYR_SOC_ARM_ASPEED_AST10X0_SOC_H_*/

soc/arm/atmel_sam0/samc21/Kconfig.series

@@ -10,6 +10,7 @@ config SOC_SERIES_SAMC21
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
+	select CPU_HAS_ARM_MPU
 	select SOC_FAMILY_SAM0
 	select PLATFORM_SPECIFIC_INIT
 	select ASF

soc/arm/bcm_vk/valkyrie/soc.h

@@ -292,4 +292,6 @@ typedef enum IRQn {
 #define PCIE0_PERST_FE_INTR		BIT(1)
 #define PCIE0_PERST_INB_FE_INTR		BIT(3)
 
+#include <core_cm7.h>
+
 #endif

soc/arm/bcm_vk/viper/soc.h

@@ -9,10 +9,10 @@
 
 #include <zephyr/sys/util.h>
 #include <zephyr/toolchain.h>
+#include <zephyr/arch/arm/cortex_m/nvic.h>
 
 #ifndef _ASMLANGUAGE
 
-
 /* Interrupt Number Definition */
 typedef enum IRQn {
 	/* CORTEX-M7 Processor Exceptions Numbers */
@@ -301,4 +301,6 @@ typedef enum IRQn {
 #define LS_ICFG_PMON_LITE_SW_RESETN		0x482f0120
 #define PCIE_PMON_LITE_SW_RESETN		BIT(0)
 
+#include <core_cm7.h>
+
 #endif

soc/arm/cypress/Kconfig

@@ -12,12 +12,15 @@ config SOC_PSOC6_M0
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
+	select CPU_HAS_ARM_MPU
 
 config SOC_PSOC6_M4
 	bool "SOC_PSOC6_M4"
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
 
 endchoice
 

soc/arm/gigadevice/gd32a50x/Kconfig.series

@@ -6,6 +6,7 @@ config SOC_SERIES_GD32A50X
 	select ARM
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
+	select ARMV8_M_DSP
 	select CPU_CORTEX_M33
 	select SOC_FAMILY_GD32_ARM
 	select GD32_HAS_AF_PINMUX

soc/arm/gigadevice/gd32e50x/Kconfig.series

@@ -7,6 +7,7 @@ config SOC_SERIES_GD32E50X
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
 	select CPU_CORTEX_M33
+	select ARMV8_M_DSP
 	select SOC_FAMILY_GD32_ARM
 	select GD32_HAS_AFIO_PINMUX
 	select GD32_HAS_IRC_40K

soc/arm/gigadevice/gd32l23x/Kconfig.series

@@ -6,6 +6,7 @@ config SOC_SERIES_GD32L23X
 	select ARM
 	select CPU_CORTEX_M23
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
 	select SOC_FAMILY_GD32_ARM
 	select GD32_HAS_AF_PINMUX
 	select GD32_HAS_IRC_32K

soc/arm/microchip_mec/mec1501/Kconfig.series

@@ -8,6 +8,7 @@ config SOC_SERIES_MEC1501X
 	select ARM
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_ARM_MPU
 	select SOC_FAMILY_MEC
 	select HAS_PM
 	help

soc/arm/microchip_mec/mec172x/soc.h

@@ -242,6 +242,8 @@ typedef enum {
 	MAX_IRQn
 } IRQn_Type;
 
+#include <core_cm4.h>
+
 #include <zephyr/sys/util.h>
 
 /* chip specific register defines */

soc/arm/nuvoton_npcx/npcx4/soc.h

@@ -7,9 +7,7 @@
 #ifndef _NUVOTON_NPCX_SOC_H_
 #define _NUVOTON_NPCX_SOC_H_
 
-/* CMSIS required definitions */
-#define __FPU_PRESENT  CONFIG_CPU_HAS_FPU
-#define __MPU_PRESENT  CONFIG_CPU_HAS_ARM_MPU
+#include <cmsis_core_m_defaults.h>
 
 /* NPCX4 SCFG multi-registers */
 #define NPCX_DEVALT_OFFSET(n)		(0x010 + n)

soc/arm/nuvoton_npcx/npcx7/soc.h

@@ -7,9 +7,7 @@
 #ifndef _NUVOTON_NPCX_SOC_H_
 #define _NUVOTON_NPCX_SOC_H_
 
-/* CMSIS required definitions */
-#define __FPU_PRESENT  CONFIG_CPU_HAS_FPU
-#define __MPU_PRESENT  CONFIG_CPU_HAS_ARM_MPU
+#include <cmsis_core_m_defaults.h>
 
 /* NPCX7 SCFG multi-registers offset */
 #define NPCX_DEVALT_OFFSET(n)		(0x010 + n)

soc/arm/nuvoton_npcx/npcx9/soc.h

@@ -7,9 +7,7 @@
 #ifndef _NUVOTON_NPCX_SOC_H_
 #define _NUVOTON_NPCX_SOC_H_
 
-/* CMSIS required definitions */
-#define __FPU_PRESENT  CONFIG_CPU_HAS_FPU
-#define __MPU_PRESENT  CONFIG_CPU_HAS_ARM_MPU
+#include <cmsis_core_m_defaults.h>
 
 /* NPCX9 SCFG multi-registers */
 #define NPCX_DEVALT_OFFSET(n)		(0x010 + n)

soc/arm/nxp_imx/mcimx6x_m4/Kconfig.series

@@ -11,6 +11,7 @@ config SOC_SERIES_IMX_6X_M4
 	select HAS_IMX_HAL
 	select SOC_FAMILY_IMX
 	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
 	select CLOCK_CONTROL
 	help
 	  Enable support for M4 core of i.MX 6SoloX MCU series

soc/arm/nxp_imx/mcimx7_m4/Kconfig.series

@@ -11,5 +11,6 @@ config SOC_SERIES_IMX7_M4
 	select SOC_FAMILY_IMX
 	select CLOCK_CONTROL
 	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
 	help
 	  Enable support for i.MX7 M4 MCU series

soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.series

@@ -9,5 +9,6 @@ config SOC_SERIES_IMX8MM_M4
 	select CPU_CORTEX_M4
 	select SOC_FAMILY_IMX
 	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
 	help
 	  Enable support for i.MX8MM M4 MCU series

soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.series

@@ -9,5 +9,6 @@ config SOC_SERIES_IMX8MQ_M4
 	select CPU_CORTEX_M4
 	select SOC_FAMILY_IMX
 	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
 	help
 	  Enable support for i.MX8MQ M4 MCU series

soc/arm/nxp_imx/rt/Kconfig.soc

@@ -21,6 +21,7 @@ config SOC_MIMXRT1011
 	select HAS_MCUX_LPUART
 	select HAS_MCUX_GPT
 	select HAS_MCUX_TRNG
+	select CPU_HAS_FPU
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
@@ -47,6 +48,7 @@ config SOC_MIMXRT1015
 	select HAS_MCUX_LPUART
 	select HAS_MCUX_GPT
 	select HAS_MCUX_TRNG
+	select CPU_HAS_FPU
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select CPU_HAS_ARM_MPU
 	select INIT_ENET_PLL
@@ -372,6 +374,7 @@ config SOC_MIMXRT1176_CM4
 	select HAS_MCUX_FLEXSPI
 	select HAS_MCUX_LPUART
 	select HAS_MCUX_GPT
+	select CPU_HAS_FPU
 	select CPU_HAS_ARM_MPU
 	select INIT_ARM_PLL
 	select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
@@ -441,6 +444,7 @@ config SOC_MIMXRT1166_CM4
 	select HAS_MCUX_FLEXSPI
 	select HAS_MCUX_GPT
 	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
 	select INIT_ARM_PLL
 	select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
 	select INIT_VIDEO_PLL

soc/arm/nxp_kinetis/kl2x/Kconfig.series

@@ -9,6 +9,7 @@ config SOC_SERIES_KINETIS_KL2X
 	select CPU_CORTEX_M0PLUS
 	select SOC_FAMILY_KINETIS
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
 	select CLOCK_CONTROL
 	select PLATFORM_SPECIFIC_INIT
 	help

soc/arm/nxp_kinetis/kwx/Kconfig.series

@@ -8,6 +8,7 @@ config SOC_SERIES_KINETIS_KWX
 	select ARM
 	select SOC_FAMILY_KINETIS
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
 	select CLOCK_CONTROL
 	select PLATFORM_SPECIFIC_INIT
 	help

soc/arm/nxp_lpc/lpc11u6x/soc.h

@@ -19,6 +19,7 @@
 #ifndef _ASMLANGUAGE
 #include <zephyr/sys/util.h>
 
+#include <cmsis_core_m_defaults.h>
 
 #endif /* !_ASMLANGUAGE */
 

soc/arm/nxp_lpc/lpc51u68/Kconfig.series

@@ -13,6 +13,7 @@ config SOC_SERIES_LPC51U68
 	select HAS_MCUX_SCTIMER
 	select SOC_FAMILY_LPC
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
 	select PLATFORM_SPECIFIC_INIT
 	help
 	  Enable support for LPC LPC51U68 MCU Series

soc/arm/nxp_lpc/lpc51u68/soc.h

@@ -10,6 +10,8 @@
 #ifndef _ASMLANGUAGE
 #include <zephyr/sys/util.h>
 
+#include <fsl_common.h>
+
 #endif /* !_ASMLANGUAGE*/
 
 #define IOCON_PIO_DIGITAL_EN	0x80u

soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc

@@ -12,6 +12,7 @@ config SOC_LPC54114_M4
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
 	select PLATFORM_SPECIFIC_INIT
 	select CLOCK_CONTROL
 	select HAS_MCUX_IAP_LEGACY

soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc

@@ -35,6 +35,7 @@ config SOC_LPC55S16
 config SOC_LPC55S28
 	bool "SOC_LPC55S28 M33"
 	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_SAU
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
 	select ARMV8_M_DSP

soc/arm/nxp_s32/s32k3/soc.h

@@ -8,6 +8,7 @@
 #define _NXP_S32_S32K_SOC_H_
 
 #include <S32K344.h>
+#include <core_cm7.h>
 
 #if defined(CONFIG_CMSIS_RTOS_V2)
 #include <cmsis_rtos_v2_adapt.h>

soc/arm/quicklogic_eos_s3/Kconfig.soc

@@ -7,4 +7,5 @@ config SOC_EOS_S3
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
 	select EOS_S3_HAL

soc/arm/renesas_ra/common/ra_common_soc.h

@@ -11,6 +11,8 @@
 extern "C" {
 #endif
 
+#include <cmsis_core_m_defaults.h>
+
 #ifdef __cplusplus
 }
 #endif

soc/arm/renesas_smartbond/da1469x/Kconfig.series

@@ -8,6 +8,7 @@ config SOC_SERIES_DA1469X
 	select CPU_HAS_FPU
 	select CPU_HAS_ARM_MPU
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select ARMV8_M_DSP
 	select SOC_FAMILY_SMARTBOND
 	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
 	select CLOCK_CONTROL

soc/arm/rpi_pico/rp2/soc.h

@@ -12,8 +12,6 @@
 #ifndef _RPI_PICO_RP2040_SOC_H_
 #define _RPI_PICO_RP2040_SOC_H_
 
-
-#define __VTOR_PRESENT CONFIG_CPU_CORTEX_M_HAS_VTOR
-#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
+#include <cmsis_core_m_defaults.h>
 
 #endif /* _RPI_PICO_RP2040_SOC_H_ */

soc/arm/silabs_exx32/efm32hg/Kconfig.series

@@ -9,6 +9,7 @@ config SOC_SERIES_EFM32HG
 	select CPU_CORTEX_M0PLUS
 	select SOC_FAMILY_EXX32
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
 	select HAS_SILABS_GECKO
 	select SOC_GECKO_CMU
 	select SOC_GECKO_GPIO

soc/arm/silabs_exx32/efr32mg21/Kconfig.series

@@ -11,6 +11,7 @@ config SOC_SERIES_EFR32MG21
 	select ARMV8_M_DSP
 	select CPU_HAS_FPU
 	select CPU_HAS_ARM_MPU
+	select CPU_HAS_ARM_SAU
 	select SOC_FAMILY_EXX32
 	select SOC_GECKO_HAS_RADIO
 	select SOC_GECKO_SERIES2

soc/arm/st_stm32/stm32mp1/Kconfig.series

@@ -11,6 +11,7 @@ config SOC_SERIES_STM32MP1X
 	select SOC_FAMILY_STM32
 	select HAS_STM32CUBE
 	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
 	select OPENAMP_RSC_TABLE if RAM_CONSOLE
 	help
 	  Enable support for STM32MP1 MPU series

soc/arm/ti_k3/am62x_m4/soc.h

@@ -7,6 +7,8 @@
 #ifndef __SOC_H_
 #define __SOC_H_
 
+#include <cmsis_core_m_defaults.h>
+
 #include <zephyr/drivers/mm/rat.h>
 
 #endif /* __SOC_H */

soc/arm/ti_lm3s6965/soc.h

@@ -15,6 +15,7 @@
 #ifndef _BOARD__H_
 #define _BOARD__H_
 
+#include <cmsis_core_m_defaults.h>
 #include <zephyr/sys/util.h>
 
 /* default system clock */

soc/arm/ti_simplelink/cc13x2_cc26x2/soc.h

@@ -7,6 +7,8 @@
 #ifndef TI_SIMPLELINK_CC13X2_CC26X2_SOC_H_
 #define TI_SIMPLELINK_CC13X2_CC26X2_SOC_H_
 
+#include <zephyr/arch/arm/cortex_m/nvic.h>
+
 /* CMSIS required values */
 typedef enum {
 	Reset_IRQn            = -15,
@@ -27,4 +29,6 @@ typedef enum {
 #define __Vendor_SysTickConfig 0
 #define __FPU_PRESENT          1
 
+#include <core_cm4.h>
+
 #endif /* TI_SIMPLELINK_CC13X2_CC26X2_SOC_H_ */

soc/arm/ti_simplelink/cc32xx/soc.h

@@ -7,6 +7,8 @@
 #ifndef TI_SIMPLELINK_CC32XX_SOC_H_
 #define TI_SIMPLELINK_CC32XX_SOC_H_
 
+#include <zephyr/arch/arm/cortex_m/nvic.h>
+
 #include <inc/hw_types.h>
 #include <driverlib/prcm.h>
 
@@ -38,4 +40,6 @@ typedef enum {
 #define __NVIC_PRIO_BITS               NUM_IRQ_PRIO_BITS
 #define __Vendor_SysTickConfig         0 /* Default to standard SysTick */
 
+#include <core_cm4.h>
+
 #endif /* TI_SIMPLELINK_CC32XX_SOC_H_ */

soc/arm/ti_simplelink/msp432p4xx/Kconfig.series

@@ -11,5 +11,6 @@ config SOC_SERIES_MSP432P4XX
 	select DYNAMIC_INTERRUPTS
 	select SOC_FAMILY_TISIMPLELINK
 	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
 	help
 	  Enable support for TI SimpleLink MSP432P4XX.