soc: arm: fix missing configs & defines
Some SoC have missing feature selections in their Kconfig. Some others are missing includes of CMSIS-Core headers. Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This commit is contained in:
parent
29ffaaa0b6
commit
af3a19106a
41 changed files with 61 additions and 15 deletions
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@ -10,6 +10,7 @@ config SOC_SERIES_APOLLO4X
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select SOC_FAMILY_AMBIQ
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select HAS_SWO
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select AMBIQ_HAL
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@ -7,7 +7,6 @@
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#ifndef _SOC_H_
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#define _SOC_H_
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#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
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#include <cmsis_core_m_defaults.h>
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#endif /* _SOC_H_ */
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@ -11,5 +11,7 @@ config SOC_V2M_MUSCA_S1
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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endchoice
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@ -25,4 +25,6 @@
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void aspeed_print_sysrst_info(void);
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#include <cmsis_core_m_defaults.h>
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#endif /* ZEPHYR_SOC_ARM_ASPEED_AST10X0_SOC_H_*/
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@ -10,6 +10,7 @@ config SOC_SERIES_SAMC21
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select CPU_HAS_ARM_MPU
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select SOC_FAMILY_SAM0
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select PLATFORM_SPECIFIC_INIT
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select ASF
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@ -292,4 +292,6 @@ typedef enum IRQn {
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#define PCIE0_PERST_FE_INTR BIT(1)
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#define PCIE0_PERST_INB_FE_INTR BIT(3)
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#include <core_cm7.h>
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#endif
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@ -9,10 +9,10 @@
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#include <zephyr/sys/util.h>
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#include <zephyr/toolchain.h>
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#include <zephyr/arch/arm/cortex_m/nvic.h>
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#ifndef _ASMLANGUAGE
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/* Interrupt Number Definition */
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typedef enum IRQn {
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/* CORTEX-M7 Processor Exceptions Numbers */
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@ -301,4 +301,6 @@ typedef enum IRQn {
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#define LS_ICFG_PMON_LITE_SW_RESETN 0x482f0120
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#define PCIE_PMON_LITE_SW_RESETN BIT(0)
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#include <core_cm7.h>
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#endif
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@ -12,12 +12,15 @@ config SOC_PSOC6_M0
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select CPU_HAS_ARM_MPU
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config SOC_PSOC6_M4
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bool "SOC_PSOC6_M4"
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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endchoice
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@ -6,6 +6,7 @@ config SOC_SERIES_GD32A50X
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select ARM
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select CPU_CORTEX_M33
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select SOC_FAMILY_GD32_ARM
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select GD32_HAS_AF_PINMUX
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@ -7,6 +7,7 @@ config SOC_SERIES_GD32E50X
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select CPU_CORTEX_M33
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select ARMV8_M_DSP
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select SOC_FAMILY_GD32_ARM
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select GD32_HAS_AFIO_PINMUX
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select GD32_HAS_IRC_40K
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@ -6,6 +6,7 @@ config SOC_SERIES_GD32L23X
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select ARM
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select CPU_CORTEX_M23
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select SOC_FAMILY_GD32_ARM
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select GD32_HAS_AF_PINMUX
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select GD32_HAS_IRC_32K
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@ -8,6 +8,7 @@ config SOC_SERIES_MEC1501X
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select ARM
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select SOC_FAMILY_MEC
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select HAS_PM
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help
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@ -242,6 +242,8 @@ typedef enum {
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MAX_IRQn
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} IRQn_Type;
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#include <core_cm4.h>
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#include <zephyr/sys/util.h>
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/* chip specific register defines */
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@ -7,9 +7,7 @@
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#ifndef _NUVOTON_NPCX_SOC_H_
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#define _NUVOTON_NPCX_SOC_H_
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/* CMSIS required definitions */
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#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
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#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
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#include <cmsis_core_m_defaults.h>
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/* NPCX4 SCFG multi-registers */
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#define NPCX_DEVALT_OFFSET(n) (0x010 + n)
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@ -7,9 +7,7 @@
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#ifndef _NUVOTON_NPCX_SOC_H_
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#define _NUVOTON_NPCX_SOC_H_
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/* CMSIS required definitions */
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#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
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#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
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#include <cmsis_core_m_defaults.h>
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/* NPCX7 SCFG multi-registers offset */
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#define NPCX_DEVALT_OFFSET(n) (0x010 + n)
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@ -7,9 +7,7 @@
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#ifndef _NUVOTON_NPCX_SOC_H_
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#define _NUVOTON_NPCX_SOC_H_
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/* CMSIS required definitions */
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#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
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#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
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#include <cmsis_core_m_defaults.h>
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/* NPCX9 SCFG multi-registers */
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#define NPCX_DEVALT_OFFSET(n) (0x010 + n)
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@ -11,6 +11,7 @@ config SOC_SERIES_IMX_6X_M4
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select HAS_IMX_HAL
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select SOC_FAMILY_IMX
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select CLOCK_CONTROL
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help
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Enable support for M4 core of i.MX 6SoloX MCU series
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@ -11,5 +11,6 @@ config SOC_SERIES_IMX7_M4
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select SOC_FAMILY_IMX
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select CLOCK_CONTROL
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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help
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Enable support for i.MX7 M4 MCU series
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@ -9,5 +9,6 @@ config SOC_SERIES_IMX8MM_M4
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select CPU_CORTEX_M4
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select SOC_FAMILY_IMX
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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help
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Enable support for i.MX8MM M4 MCU series
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@ -9,5 +9,6 @@ config SOC_SERIES_IMX8MQ_M4
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select CPU_CORTEX_M4
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select SOC_FAMILY_IMX
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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help
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Enable support for i.MX8MQ M4 MCU series
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@ -21,6 +21,7 @@ config SOC_MIMXRT1011
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select HAS_MCUX_LPUART
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select HAS_MCUX_GPT
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select HAS_MCUX_TRNG
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ICACHE
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select CPU_HAS_DCACHE
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@ -47,6 +48,7 @@ config SOC_MIMXRT1015
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select HAS_MCUX_LPUART
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select HAS_MCUX_GPT
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select HAS_MCUX_TRNG
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select CPU_HAS_FPU
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select CPU_HAS_ARM_MPU
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select INIT_ENET_PLL
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@ -372,6 +374,7 @@ config SOC_MIMXRT1176_CM4
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select HAS_MCUX_FLEXSPI
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select HAS_MCUX_LPUART
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select HAS_MCUX_GPT
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select INIT_ARM_PLL
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select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
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@ -441,6 +444,7 @@ config SOC_MIMXRT1166_CM4
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select HAS_MCUX_FLEXSPI
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select HAS_MCUX_GPT
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select INIT_ARM_PLL
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select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
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select INIT_VIDEO_PLL
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@ -9,6 +9,7 @@ config SOC_SERIES_KINETIS_KL2X
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select CPU_CORTEX_M0PLUS
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select SOC_FAMILY_KINETIS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select CLOCK_CONTROL
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select PLATFORM_SPECIFIC_INIT
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help
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@ -8,6 +8,7 @@ config SOC_SERIES_KINETIS_KWX
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select ARM
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select SOC_FAMILY_KINETIS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select CLOCK_CONTROL
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select PLATFORM_SPECIFIC_INIT
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help
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@ -19,6 +19,7 @@
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#ifndef _ASMLANGUAGE
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#include <zephyr/sys/util.h>
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#include <cmsis_core_m_defaults.h>
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#endif /* !_ASMLANGUAGE */
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@ -13,6 +13,7 @@ config SOC_SERIES_LPC51U68
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select HAS_MCUX_SCTIMER
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select SOC_FAMILY_LPC
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select PLATFORM_SPECIFIC_INIT
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help
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Enable support for LPC LPC51U68 MCU Series
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@ -10,6 +10,8 @@
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#ifndef _ASMLANGUAGE
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#include <zephyr/sys/util.h>
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#include <fsl_common.h>
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#endif /* !_ASMLANGUAGE*/
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#define IOCON_PIO_DIGITAL_EN 0x80u
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@ -12,6 +12,7 @@ config SOC_LPC54114_M4
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select PLATFORM_SPECIFIC_INIT
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select CLOCK_CONTROL
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select HAS_MCUX_IAP_LEGACY
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@ -35,6 +35,7 @@ config SOC_LPC55S16
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config SOC_LPC55S28
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bool "SOC_LPC55S28 M33"
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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@ -8,6 +8,7 @@
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#define _NXP_S32_S32K_SOC_H_
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#include <S32K344.h>
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#include <core_cm7.h>
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#if defined(CONFIG_CMSIS_RTOS_V2)
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#include <cmsis_rtos_v2_adapt.h>
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@ -7,4 +7,5 @@ config SOC_EOS_S3
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select EOS_S3_HAL
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@ -11,6 +11,8 @@
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extern "C" {
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#endif
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#include <cmsis_core_m_defaults.h>
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#ifdef __cplusplus
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}
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#endif
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@ -8,6 +8,7 @@ config SOC_SERIES_DA1469X
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select CPU_CORTEX_M_HAS_SYSTICK
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select ARMV8_M_DSP
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select SOC_FAMILY_SMARTBOND
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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select CLOCK_CONTROL
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@ -12,8 +12,6 @@
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#ifndef _RPI_PICO_RP2040_SOC_H_
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#define _RPI_PICO_RP2040_SOC_H_
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#define __VTOR_PRESENT CONFIG_CPU_CORTEX_M_HAS_VTOR
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#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
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#include <cmsis_core_m_defaults.h>
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#endif /* _RPI_PICO_RP2040_SOC_H_ */
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@ -9,6 +9,7 @@ config SOC_SERIES_EFM32HG
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select CPU_CORTEX_M0PLUS
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select SOC_FAMILY_EXX32
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select HAS_SILABS_GECKO
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select SOC_GECKO_CMU
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select SOC_GECKO_GPIO
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@ -11,6 +11,7 @@ config SOC_SERIES_EFR32MG21
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select ARMV8_M_DSP
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ARM_SAU
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select SOC_FAMILY_EXX32
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select SOC_GECKO_HAS_RADIO
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select SOC_GECKO_SERIES2
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@ -11,6 +11,7 @@ config SOC_SERIES_STM32MP1X
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select SOC_FAMILY_STM32
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select HAS_STM32CUBE
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select OPENAMP_RSC_TABLE if RAM_CONSOLE
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help
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Enable support for STM32MP1 MPU series
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@ -7,6 +7,8 @@
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#ifndef __SOC_H_
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#define __SOC_H_
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#include <cmsis_core_m_defaults.h>
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#include <zephyr/drivers/mm/rat.h>
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#endif /* __SOC_H */
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@ -15,6 +15,7 @@
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#ifndef _BOARD__H_
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#define _BOARD__H_
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#include <cmsis_core_m_defaults.h>
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#include <zephyr/sys/util.h>
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/* default system clock */
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@ -7,6 +7,8 @@
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#ifndef TI_SIMPLELINK_CC13X2_CC26X2_SOC_H_
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#define TI_SIMPLELINK_CC13X2_CC26X2_SOC_H_
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#include <zephyr/arch/arm/cortex_m/nvic.h>
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/* CMSIS required values */
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typedef enum {
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Reset_IRQn = -15,
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#define __Vendor_SysTickConfig 0
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#define __FPU_PRESENT 1
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#include <core_cm4.h>
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#endif /* TI_SIMPLELINK_CC13X2_CC26X2_SOC_H_ */
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@ -7,6 +7,8 @@
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#ifndef TI_SIMPLELINK_CC32XX_SOC_H_
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#define TI_SIMPLELINK_CC32XX_SOC_H_
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#include <zephyr/arch/arm/cortex_m/nvic.h>
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#include <inc/hw_types.h>
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#include <driverlib/prcm.h>
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#define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS
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#define __Vendor_SysTickConfig 0 /* Default to standard SysTick */
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#include <core_cm4.h>
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#endif /* TI_SIMPLELINK_CC32XX_SOC_H_ */
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@ -11,5 +11,6 @@ config SOC_SERIES_MSP432P4XX
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select DYNAMIC_INTERRUPTS
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select SOC_FAMILY_TISIMPLELINK
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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help
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Enable support for TI SimpleLink MSP432P4XX.
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