xtensa: dc233c: enable userspace support
This massages kconfig and linker script to enable userspace support on dc233c core. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Carles Cufí
parent
0d79481540
commit
a36e39c2a6
3 changed files with 60 additions and 40 deletions
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@ -9,3 +9,4 @@ config SOC_XTENSA_DC233C
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select ARCH_HAS_THREAD_LOCAL_STORAGE
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select CPU_HAS_MMU
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select ARCH_HAS_RESERVED_PAGE_FRAMES if XTENSA_MMU
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select ARCH_HAS_USERSPACE if XTENSA_MMU
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@ -20,7 +20,7 @@
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#include <zephyr/linker/linker-tool.h>
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#define RAMABLE_REGION RAM :sram0_phdr
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#define ROMABLE_REGION rom0_seg :rom0_phdr
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#define ROMABLE_REGION RAM :sram0_phdr
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#ifdef CONFIG_MMU
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#define MMU_PAGE_ALIGN . = ALIGN(CONFIG_MMU_PAGE_SIZE);
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@ -287,6 +287,9 @@ SECTIONS
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_DoubleExceptionVector_text_end = ABSOLUTE(.);
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} >sram0_18_seg :sram0_18_phdr
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#define LIB_OBJ_FUNC_IN_SECT(library, obj_file, func) \
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*##library##:##obj_file##(.literal.##func .text.##func) \
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#ifdef CONFIG_XTENSA_MMU
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.vec_helpers :
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{
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@ -301,48 +304,45 @@ SECTIONS
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* TLB multi-hit exception.
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*/
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*libarch__xtensa__core.a:xtensa-asm2-util.S.obj(.literal)
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*libarch__xtensa__core.a:xtensa-asm2-util.S.obj(.text)
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*libarch__xtensa__core.a:xtensa-asm2-util.S.obj(.iram.text)
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*libarch__xtensa__core.a:xtensa-asm2-util.S.obj(.iram0.text)
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*libarch__xtensa__core.a:xtensa-asm2-util.S.obj(.literal .text)
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*libarch__xtensa__core.a:xtensa-asm2-util.S.obj(.iram.text .iram0.text)
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*libarch__xtensa__core.a:window_vectors.S.obj(.iram.text)
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*libarch__xtensa__core.a:xtensa-asm2.c.obj(.literal.*)
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*libarch__xtensa__core.a:xtensa-asm2.c.obj(.text.*)
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*libarch__xtensa__core.a:crt1.S.obj(.literal .text)
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*libarch__xtensa__core.a:fatal.c.obj(.literal.*)
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*libarch__xtensa__core.a:fatal.c.obj(.text.*)
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*libarch__xtensa__core.a:crt1.S.obj(.literal)
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*libarch__xtensa__core.a:crt1.S.obj(.text)
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*libarch__xtensa__core.a:cpu_idle.c.obj(.literal.*)
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*libarch__xtensa__core.a:cpu_idle.c.obj(.text.*)
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,xtensa-asm2.c.obj,*)
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,fatal.c.obj,*)
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,cpu_idle.c.obj,*)
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*(.text.arch_is_in_isr)
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/* To support backtracing */
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*libarch__xtensa__core.a:xtensa_backtrace.c.obj(.literal.*)
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*libarch__xtensa__core.a:xtensa_backtrace.c.obj(.text.*)
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*libarch__xtensa__core.a:debug_helpers_asm.S.obj(.iram1.literal)
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*libarch__xtensa__core.a:debug_helpers_asm.S.obj(.iram1)
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,xtensa_backtrace.c.obj,*)
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*libkernel.a:fatal.c.obj(.literal.*)
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*libkernel.a:fatal.c.obj(.text.*)
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*libarch__xtensa__core.a:debug_helpers_asm.S.obj(.iram1.literal .iram1)
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/* Userspace related stuff */
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,userspace.S.obj,z_xtensa_do_syscall)
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,xtensa_mmu.c.obj,z_xtensa_swap_update_page_tables)
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/* Below are to speed up execution by avoiding TLB misses
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* on frequently used functions.
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*
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* There is almost 1MB space (due to TLB pinning) so we can
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* be generous.
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*/
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*libkernel.a:sched.c.obj(.literal.*)
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*libkernel.a:sched.c.obj(.text.*)
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*libkernel.a:timeout.c.obj(.literal.*)
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*libkernel.a:timeout.c.obj(.text.*)
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LIB_OBJ_FUNC_IN_SECT(libkernel.a,,*)
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*libdrivers__console.a:(.literal.*)
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*libdrivers__console.a:(.text.*)
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*libdrivers__timer.a:(.literal.*)
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*libdrivers__timer.a:(.text.*)
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LIB_OBJ_FUNC_IN_SECT(libdrivers__console.a,,*)
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LIB_OBJ_FUNC_IN_SECT(libdrivers__timer.a,,*)
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*(.literal.z_vrfy_* .text.z_vrfy_*)
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*(.literal.z_mrsh_* .text.z_mrsh_*)
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*(.literal.z_impl_* .text.z_impl_*)
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*(.literal.z_obj_* .text.z_obj_*)
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*(.literal.k_sys_fatal_error_handler .text.k_sys_fatal_error_handler)
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} >vec_helpers :vec_helpers_phdr
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#endif /* CONFIG_XTENSA_MMU */
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@ -380,7 +380,7 @@ SECTIONS
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_text_end = ABSOLUTE(.);
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_etext = .;
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} >RAM :sram0_phdr
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} >RAMABLE_REGION
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__text_region_end = .;
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.rodata : HDR_MMU_PAGE_ALIGN
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@ -394,7 +394,16 @@ SECTIONS
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. = ALIGN(4);
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#include <snippets-rodata.ld>
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#include <zephyr/linker/kobject-rom.ld>
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} >RAMABLE_REGION
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#include <zephyr/linker/common-rom.ld>
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#include <zephyr/linker/thread-local-storage.ld>
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#include <zephyr/linker/cplusplus-rom.ld>
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.rodata_end : ALIGN(4)
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{
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. = ALIGN(4); /* this table MUST be 4-byte aligned */
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_bss_table_start = ABSOLUTE(.);
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LONG(_bss_start)
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@ -404,19 +413,26 @@ SECTIONS
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MMU_PAGE_ALIGN
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__rodata_region_end = ABSOLUTE(.);
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} >RAM :sram0_phdr
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} >RAMABLE_REGION
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#include <zephyr/linker/common-rom.ld>
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#ifdef CONFIG_USERSPACE
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#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN
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#define APP_SHARED_ALIGN MMU_PAGE_ALIGN
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#include <zephyr/linker/thread-local-storage.ld>
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#include <app_smem.ld>
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#include <zephyr/linker/cplusplus-rom.ld>
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#include <snippets-sections.ld>
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_image_ram_start = _app_smem_start;
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_app_smem_size = _app_smem_end - _app_smem_start;
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_app_smem_num_words = _app_smem_size >> 2;
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_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
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_app_smem_num_words = _app_smem_size >> 2;
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#endif /* CONFIG_USERSPACE */
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.data : HDR_MMU_PAGE_ALIGN
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{
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#ifndef CONFIG_USERSPACE
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_image_ram_start = ABSOLUTE(.);
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#endif
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__data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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@ -438,7 +454,9 @@ SECTIONS
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MMU_PAGE_ALIGN
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__data_end = ABSOLUTE(.);
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} >RAM :sram0_phdr
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} >RAMABLE_REGION
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#include <snippets-sections.ld>
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#include <snippets-data-sections.ld>
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@ -18,7 +18,7 @@ const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = {
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{
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.start = (uint32_t)XCHAL_VECBASE_RESET_VADDR,
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.end = (uint32_t)CONFIG_SRAM_OFFSET,
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.attrs = Z_XTENSA_MMU_X | Z_XTENSA_MMU_CACHED_WB,
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.attrs = Z_XTENSA_MMU_X | Z_XTENSA_MMU_CACHED_WB | Z_XTENSA_MMU_MAP_SHARED,
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.name = "vecbase",
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},
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{
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@ -52,7 +52,8 @@ void arch_xtensa_mmu_post_init(bool is_core0)
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/* Map VECBASE permanently in instr TLB way 4 so we will always have
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* access to exception handlers. Each way 4 TLB covers 1MB (unless
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* ITLBCFG has been changed before this, which should not have
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* happened).
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* happened). Also this needs to be mapped as SHARED so both kernel
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* and userspace can execute code here => same as .text.
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*
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* Note that we don't want to map the first 1MB in data TLB as
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* we want to keep page 0 (0x00000000) unmapped to catch null pointer
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@ -60,7 +61,7 @@ void arch_xtensa_mmu_post_init(bool is_core0)
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*/
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vecbase = ROUND_DOWN(vecbase, MB(1));
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xtensa_itlb_entry_write_sync(
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Z_XTENSA_PTE(vecbase, Z_XTENSA_KERNEL_RING,
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Z_XTENSA_PTE(vecbase, Z_XTENSA_SHARED_RING,
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Z_XTENSA_MMU_X | Z_XTENSA_MMU_CACHED_WT),
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Z_XTENSA_TLB_ENTRY((uint32_t)vecbase, 4));
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}
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