Microchip MEC172X: Rework GPIO definitions to separate package types.
MEC172X has 2 package sizes with additional pins on the -LJ package. This commit separates the package-specific parts into different files. In addition, this patch removes unnecessary package-specific enums in favor of calculated offsets into the desired registers. Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
This commit is contained in:
Jeff Daly
Carles Cufí
parent
7b4f22edd1
commit
83de11d9f3
3 changed files with 44 additions and 508 deletions
17
soc/arm/microchip_mec/mec172x/reg/gpio_pkg_lj.h
Normal file
17
soc/arm/microchip_mec/mec172x/reg/gpio_pkg_lj.h
Normal file
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC172X_GPIO_LJ_H
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#define _MEC172X_GPIO_LJ_H
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#define MCHP_GPIO_PORT_A_BITMAP 0x7FFFFFFFu /* GPIO_0000 - 0036 GIRQ11 */
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#define MCHP_GPIO_PORT_B_BITMAP 0x7FFFFFFFu /* GPIO_0040 - 0076 GIRQ10 */
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#define MCHP_GPIO_PORT_C_BITMAP 0x3FFFFFF7u /* GPIO_0100 - 0136 GIRQ09 */
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#define MCHP_GPIO_PORT_D_BITMAP 0x3F67FFFFu /* GPIO_0140 - 0176 GIRQ08 */
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#define MCHP_GPIO_PORT_E_BITMAP 0x7FFFFFFFu /* GPIO_0200 - 0236 GIRQ12 */
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#define MCHP_GPIO_PORT_F_BITMAP 0x00003F7Fu /* GPIO_0240 - 0276 GIRQ26 */
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#endif /* #ifndef _MEC172X_GPIO_LJ_H */
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21
soc/arm/microchip_mec/mec172x/reg/gpio_pkg_sz.h
Normal file
21
soc/arm/microchip_mec/mec172x/reg/gpio_pkg_sz.h
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC172X_GPIO_SZ_H
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#define _MEC172X_GPIO_SZ_H
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#include <stdint.h>
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#include <stddef.h>
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/* MEC172XH-B0-SZ (144-pin) */
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#define MCHP_GPIO_PORT_A_BITMAP 0x7FFFFF9Du /* GPIO_0000 - 0036 GIRQ11 */
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#define MCHP_GPIO_PORT_B_BITMAP 0x7FFFFFFDu /* GPIO_0040 - 0076 GIRQ10 */
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#define MCHP_GPIO_PORT_C_BITMAP 0x07FFFCF7u /* GPIO_0100 - 0136 GIRQ09 */
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#define MCHP_GPIO_PORT_D_BITMAP 0x272EFFFFu /* GPIO_0140 - 0176 GIRQ08 */
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#define MCHP_GPIO_PORT_E_BITMAP 0x00DE00FFu /* GPIO_0200 - 0236 GIRQ12 */
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#define MCHP_GPIO_PORT_F_BITMAP 0x0000397Fu /* GPIO_0240 - 0276 GIRQ26 */
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#endif /* #ifndef _MEC172X_GPIO_SZ_H */
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@ -10,49 +10,15 @@
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#include <stdint.h>
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#include <stddef.h>
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#if defined(CONFIG_SOC_MEC172X_NSZ)
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#include "gpio_pkg_sz.h"
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#elif defined(CONFIG_SOC_MEC172X_NLJ)
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#include "gpio_pkg_lj.h"
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#endif
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#define NUM_MCHP_GPIO_PORTS 6u
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#define MAX_NUM_MCHP_GPIO (NUM_MCHP_GPIO_PORTS * 32u)
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#define MCHP_GPIO_CTRL_OFS 0u
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#define MCHP_GPIO_PARIN_OFS 0x0300u
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#define MCHP_GPIO_PAROUT_OFS 0x0380u
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#define MCHP_GPIO_LOCK_OFS 0x03e8u
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#define MCHP_GPIO_CTRL2_OFS 0x0500u
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/* MEC172XH-B0-SZ (144-pin) */
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#define MCHP_GPIO_PORT_A_BITMAP 0x7FFFFF9Du /* GPIO_0000 - 0036 GIRQ11 */
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#define MCHP_GPIO_PORT_B_BITMAP 0x7FFFFFFDu /* GPIO_0040 - 0076 GIRQ10 */
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#define MCHP_GPIO_PORT_C_BITMAP 0x07FFFCF7u /* GPIO_0100 - 0136 GIRQ09 */
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#define MCHP_GPIO_PORT_D_BITMAP 0x272EFFFFu /* GPIO_0140 - 0176 GIRQ08 */
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#define MCHP_GPIO_PORT_E_BITMAP 0x00DE00FFu /* GPIO_0200 - 0236 GIRQ12 */
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#define MCHP_GPIO_PORT_F_BITMAP 0x0000397Fu /* GPIO_0240 - 0276 GIRQ26 */
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#define MCHP_GPIO_PORT_A_DRVSTR_BITMAP 0x7FFFFF9Du
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#define MCHP_GPIO_PORT_B_DRVSTR_BITMAP 0x7FFFFFFDu
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#define MCHP_GPIO_PORT_C_DRVSTR_BITMAP 0x07FFFCF7u
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#define MCHP_GPIO_PORT_D_DRVSTR_BITMAP 0x272EFFFFu
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#define MCHP_GPIO_PORT_E_DRVSTR_BITMAP 0x00DE00FFu
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#define MCHP_GPIO_PORT_F_DRVSTR_BITMAP 0x0000397Fu
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/* 32-bit Control register */
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#define MCHP_GPIO_CTRL_MASK 0x0101ffffu
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/* bits[15:0] of Control register */
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#define MCHP_GPIO_CTRL_CFG_MASK 0xffffu
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/* Disable interrupt detect and pad */
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#define MCHP_GPIO_CTRL_DIS_PIN 0x8040u
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#define MCHP_GPIO_CTRL_DFLT 0x8040u
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#define MCHP_GPIO_CTRL_DFLT_MASK 0xffffu
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#define GPIO000_CTRL_DFLT 0x1040u
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#define GPIO062_CTRL_DFLT 0x8240u
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#define GPIO116_CTRL_DFLT 0x0041u
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#define GPIO161_CTRL_DFLT 0x1040u
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#define GPIO162_CTRL_DFLT 0x1040u
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#define GPIO170_CTRL_DFLT 0x0041u
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#define GPIO234_CTRL_DFLT 0x1040u
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/* GPIO Control register field definitions. */
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/* bits[1:0] internal pull up/down selection */
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@ -156,7 +122,6 @@
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* 10b = 8mA
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* 11b = 12mA
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*/
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#define MCHP_GPIO_CTRL2_OFFSET 0x0500u
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#define MCHP_GPIO_CTRL2_SLEW_POS 0
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#define MCHP_GPIO_CTRL2_SLEW_MASK 0x01u
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#define MCHP_GPIO_CTRL2_SLEW_SLOW 0
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@ -173,149 +138,8 @@
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extern "C" {
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#endif
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/* GPIO pin numbers SZ (144-pin) package */
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enum mec_gpio_idx {
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MCHP_GPIO_0000_ID = 0,
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MCHP_GPIO_0002_ID = 2,
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MCHP_GPIO_0003_ID,
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MCHP_GPIO_0004_ID,
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MCHP_GPIO_0007_ID = 7,
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MCHP_GPIO_0010_ID,
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MCHP_GPIO_0011_ID,
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MCHP_GPIO_0012_ID,
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MCHP_GPIO_0013_ID,
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MCHP_GPIO_0014_ID,
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MCHP_GPIO_0015_ID,
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MCHP_GPIO_0016_ID,
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MCHP_GPIO_0017_ID,
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MCHP_GPIO_0020_ID,
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MCHP_GPIO_0021_ID,
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MCHP_GPIO_0022_ID,
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MCHP_GPIO_0023_ID,
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MCHP_GPIO_0024_ID,
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MCHP_GPIO_0025_ID,
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MCHP_GPIO_0026_ID,
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MCHP_GPIO_0027_ID,
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MCHP_GPIO_0030_ID,
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MCHP_GPIO_0031_ID,
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MCHP_GPIO_0032_ID,
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MCHP_GPIO_0033_ID,
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MCHP_GPIO_0034_ID,
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MCHP_GPIO_0035_ID,
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MCHP_GPIO_0036_ID,
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MCHP_GPIO_0040_ID = 32,
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MCHP_GPIO_0042_ID = 34,
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MCHP_GPIO_0043_ID,
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MCHP_GPIO_0044_ID,
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MCHP_GPIO_0045_ID,
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MCHP_GPIO_0046_ID,
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MCHP_GPIO_0047_ID,
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MCHP_GPIO_0050_ID,
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MCHP_GPIO_0051_ID,
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MCHP_GPIO_0052_ID,
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MCHP_GPIO_0053_ID,
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MCHP_GPIO_0054_ID,
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MCHP_GPIO_0055_ID,
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MCHP_GPIO_0056_ID,
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MCHP_GPIO_0057_ID,
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MCHP_GPIO_0060_ID,
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MCHP_GPIO_0061_ID,
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MCHP_GPIO_0062_ID,
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MCHP_GPIO_0063_ID,
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MCHP_GPIO_0064_ID,
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MCHP_GPIO_0065_ID,
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MCHP_GPIO_0066_ID,
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MCHP_GPIO_0067_ID,
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MCHP_GPIO_0070_ID,
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MCHP_GPIO_0071_ID,
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MCHP_GPIO_0072_ID,
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MCHP_GPIO_0073_ID,
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MCHP_GPIO_0074_ID,
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MCHP_GPIO_0075_ID,
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MCHP_GPIO_0076_ID,
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MCHP_GPIO_0100_ID = 64,
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MCHP_GPIO_0101_ID,
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MCHP_GPIO_0102_ID,
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MCHP_GPIO_0104_ID = 68,
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MCHP_GPIO_0105_ID,
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MCHP_GPIO_0106_ID,
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MCHP_GPIO_0107_ID,
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MCHP_GPIO_0112_ID = 74,
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MCHP_GPIO_0113_ID,
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MCHP_GPIO_0114_ID,
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MCHP_GPIO_0115_ID,
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MCHP_GPIO_0116_ID,
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MCHP_GPIO_0117_ID,
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MCHP_GPIO_0120_ID = 80,
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MCHP_GPIO_0121_ID,
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MCHP_GPIO_0122_ID,
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MCHP_GPIO_0123_ID,
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MCHP_GPIO_0124_ID,
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MCHP_GPIO_0125_ID,
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MCHP_GPIO_0126_ID,
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MCHP_GPIO_0127_ID,
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MCHP_GPIO_0130_ID,
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MCHP_GPIO_0131_ID,
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MCHP_GPIO_0132_ID,
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MCHP_GPIO_0140_ID = 96,
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MCHP_GPIO_0141_ID,
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MCHP_GPIO_0142_ID,
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MCHP_GPIO_0143_ID,
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MCHP_GPIO_0144_ID,
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MCHP_GPIO_0145_ID,
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MCHP_GPIO_0146_ID,
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MCHP_GPIO_0147_ID,
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MCHP_GPIO_0150_ID,
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MCHP_GPIO_0151_ID,
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MCHP_GPIO_0152_ID,
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MCHP_GPIO_0153_ID,
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MCHP_GPIO_0154_ID,
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MCHP_GPIO_0155_ID,
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MCHP_GPIO_0156_ID,
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MCHP_GPIO_0157_ID,
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MCHP_GPIO_0161_ID = 113,
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MCHP_GPIO_0162_ID,
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MCHP_GPIO_0165_ID = 117,
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MCHP_GPIO_0170_ID = 120,
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MCHP_GPIO_0171_ID,
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MCHP_GPIO_0175_ID = 125,
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MCHP_GPIO_0200_ID = 128,
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MCHP_GPIO_0201_ID,
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MCHP_GPIO_0202_ID,
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MCHP_GPIO_0203_ID,
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MCHP_GPIO_0204_ID,
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MCHP_GPIO_0205_ID,
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MCHP_GPIO_0206_ID,
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MCHP_GPIO_0207_ID,
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MCHP_GPIO_0221_ID = 145,
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MCHP_GPIO_0222_ID,
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MCHP_GPIO_0223_ID,
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MCHP_GPIO_0224_ID,
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MCHP_GPIO_0226_ID = 150,
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MCHP_GPIO_0227_ID,
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MCHP_GPIO_0240_ID = 160,
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MCHP_GPIO_0241_ID,
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MCHP_GPIO_0242_ID,
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MCHP_GPIO_0243_ID,
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MCHP_GPIO_0244_ID,
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MCHP_GPIO_0245_ID,
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MCHP_GPIO_0246_ID,
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MCHP_GPIO_0254_ID = 172,
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MCHP_GPIO_0255_ID,
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MCHP_GPIO_MAX_ID
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};
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#define MCHP_GPIO_PIN2PORT(pin_id) ((uint32_t)(pin_id) >> 5)
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#define MAX_MCHP_GPIO_BANK 6u
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#define MCHP_GPIO_LOCK5_IDX 0u
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#define MCHP_GPIO_LOCK4_IDX 1u
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#define MCHP_GPIO_LOCK3_IDX 2u
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#define MCHP_GPIO_LOCK2_IDX 3u
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#define MCHP_GPIO_LOCK1_IDX 4u
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#define MCHP_GPIO_LOCK0_IDX 5u
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#define MCHP_GPIO_LOCK_MAX_IDX 6u
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/* Helper functions */
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enum mchp_gpio_pud {
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MCHP_GPIO_NO_PUD = 0,
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@ -393,332 +217,6 @@ enum mchp_gpio_drv_str {
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MCHP_GPIO_DRV_STR_12MA,
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};
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/** @brief GPIO control registers by pin name */
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struct gpio_ctrl_regs {
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volatile uint32_t CTRL_0000;
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uint32_t RSVD1[1];
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volatile uint32_t CTRL_0002;
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volatile uint32_t CTRL_0003;
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volatile uint32_t CTRL_0004;
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uint32_t RSVD2[2];
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volatile uint32_t CTRL_0007;
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volatile uint32_t CTRL_0010;
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volatile uint32_t CTRL_0011;
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volatile uint32_t CTRL_0012;
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volatile uint32_t CTRL_0013;
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volatile uint32_t CTRL_0014;
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volatile uint32_t CTRL_0015;
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volatile uint32_t CTRL_0016;
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volatile uint32_t CTRL_0017;
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volatile uint32_t CTRL_0020;
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volatile uint32_t CTRL_0021;
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volatile uint32_t CTRL_0022;
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volatile uint32_t CTRL_0023;
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volatile uint32_t CTRL_0024;
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volatile uint32_t CTRL_0025;
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volatile uint32_t CTRL_0026;
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volatile uint32_t CTRL_0027;
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volatile uint32_t CTRL_0030;
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volatile uint32_t CTRL_0031;
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volatile uint32_t CTRL_0032;
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volatile uint32_t CTRL_0033;
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volatile uint32_t CTRL_0034;
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volatile uint32_t CTRL_0035;
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volatile uint32_t CTRL_0036;
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uint32_t RSVD3[1];
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volatile uint32_t CTRL_0040;
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uint32_t RSVD4[1];
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volatile uint32_t CTRL_0042;
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volatile uint32_t CTRL_0043;
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volatile uint32_t CTRL_0044;
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volatile uint32_t CTRL_0045;
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volatile uint32_t CTRL_0046;
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volatile uint32_t CTRL_0047;
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volatile uint32_t CTRL_0050;
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volatile uint32_t CTRL_0051;
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volatile uint32_t CTRL_0052;
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volatile uint32_t CTRL_0053;
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volatile uint32_t CTRL_0054;
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volatile uint32_t CTRL_0055;
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volatile uint32_t CTRL_0056;
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volatile uint32_t CTRL_0057;
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volatile uint32_t CTRL_0060;
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volatile uint32_t CTRL_0061;
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volatile uint32_t CTRL_0062;
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volatile uint32_t CTRL_0063;
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volatile uint32_t CTRL_0064;
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volatile uint32_t CTRL_0065;
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volatile uint32_t CTRL_0066;
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volatile uint32_t CTRL_0067;
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volatile uint32_t CTRL_0070;
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volatile uint32_t CTRL_0071;
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volatile uint32_t CTRL_0072;
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volatile uint32_t CTRL_0073;
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volatile uint32_t CTRL_0074;
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volatile uint32_t CTRL_0075;
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volatile uint32_t CTRL_0076;
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uint32_t RSVD5[1];
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volatile uint32_t CTRL_0100;
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volatile uint32_t CTRL_0101;
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volatile uint32_t CTRL_0102;
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uint32_t RSVD6[1];
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volatile uint32_t CTRL_0104;
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volatile uint32_t CTRL_0105;
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volatile uint32_t CTRL_0106;
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volatile uint32_t CTRL_0107;
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uint32_t RSVD7[2];
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volatile uint32_t CTRL_0112;
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volatile uint32_t CTRL_0113;
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volatile uint32_t CTRL_0114;
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volatile uint32_t CTRL_0115;
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volatile uint32_t CTRL_0116;
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volatile uint32_t CTRL_0117;
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volatile uint32_t CTRL_0120;
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volatile uint32_t CTRL_0121;
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volatile uint32_t CTRL_0122;
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volatile uint32_t CTRL_0123;
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volatile uint32_t CTRL_0124;
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volatile uint32_t CTRL_0125;
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volatile uint32_t CTRL_0126;
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volatile uint32_t CTRL_0127;
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volatile uint32_t CTRL_0130;
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volatile uint32_t CTRL_0131;
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volatile uint32_t CTRL_0132;
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uint32_t RSVD9[5];
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volatile uint32_t CTRL_0140;
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volatile uint32_t CTRL_0141;
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volatile uint32_t CTRL_0142;
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volatile uint32_t CTRL_0143;
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volatile uint32_t CTRL_0144;
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volatile uint32_t CTRL_0145;
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volatile uint32_t CTRL_0146;
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volatile uint32_t CTRL_0147;
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volatile uint32_t CTRL_0150;
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volatile uint32_t CTRL_0151;
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volatile uint32_t CTRL_0152;
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volatile uint32_t CTRL_0153;
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volatile uint32_t CTRL_0154;
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volatile uint32_t CTRL_0155;
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volatile uint32_t CTRL_0156;
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volatile uint32_t CTRL_0157;
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uint32_t RSVD10[1];
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volatile uint32_t CTRL_0161;
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volatile uint32_t CTRL_0162;
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uint32_t RSVD11[2];
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volatile uint32_t CTRL_0165;
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uint32_t RSVD12[2];
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volatile uint32_t CTRL_0170;
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volatile uint32_t CTRL_0171;
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uint32_t RSVD13[3];
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volatile uint32_t CTRL_0175;
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uint32_t RSVD14[2];
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volatile uint32_t CTRL_0200;
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volatile uint32_t CTRL_0201;
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volatile uint32_t CTRL_0202;
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volatile uint32_t CTRL_0203;
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volatile uint32_t CTRL_0204;
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volatile uint32_t CTRL_0205;
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volatile uint32_t CTRL_0206;
|
||||
volatile uint32_t CTRL_0207;
|
||||
uint32_t RSVD15[9];
|
||||
volatile uint32_t CTRL_0221;
|
||||
volatile uint32_t CTRL_0222;
|
||||
volatile uint32_t CTRL_0223;
|
||||
volatile uint32_t CTRL_0224;
|
||||
uint32_t RSVD16[1];
|
||||
volatile uint32_t CTRL_0226;
|
||||
volatile uint32_t CTRL_0227;
|
||||
uint32_t RSVD17[8];
|
||||
volatile uint32_t CTRL_0240;
|
||||
volatile uint32_t CTRL_0241;
|
||||
volatile uint32_t CTRL_0242;
|
||||
volatile uint32_t CTRL_0243;
|
||||
volatile uint32_t CTRL_0244;
|
||||
volatile uint32_t CTRL_0245;
|
||||
volatile uint32_t CTRL_0246;
|
||||
uint32_t RSVD18[5];
|
||||
volatile uint32_t CTRL_0254;
|
||||
volatile uint32_t CTRL_0255;
|
||||
};
|
||||
|
||||
/** @brief GPIO Control 2 registers by pin name */
|
||||
struct gpio_ctrl2_regs {
|
||||
volatile uint32_t CTRL2_0000;
|
||||
uint32_t RSVD1[1];
|
||||
volatile uint32_t CTRL2_0002;
|
||||
volatile uint32_t CTRL2_0003;
|
||||
volatile uint32_t CTRL2_0004;
|
||||
uint32_t RSVD2[2];
|
||||
volatile uint32_t CTRL2_0007;
|
||||
volatile uint32_t CTRL2_0010;
|
||||
volatile uint32_t CTRL2_0011;
|
||||
volatile uint32_t CTRL2_0012;
|
||||
volatile uint32_t CTRL2_0013;
|
||||
volatile uint32_t CTRL2_0014;
|
||||
volatile uint32_t CTRL2_0015;
|
||||
volatile uint32_t CTRL2_0016;
|
||||
volatile uint32_t CTRL2_0017;
|
||||
volatile uint32_t CTRL2_0020;
|
||||
volatile uint32_t CTRL2_0021;
|
||||
volatile uint32_t CTRL2_0022;
|
||||
volatile uint32_t CTRL2_0023;
|
||||
volatile uint32_t CTRL2_0024;
|
||||
volatile uint32_t CTRL2_0025;
|
||||
volatile uint32_t CTRL2_0026;
|
||||
volatile uint32_t CTRL2_0027;
|
||||
volatile uint32_t CTRL2_0030;
|
||||
volatile uint32_t CTRL2_0031;
|
||||
volatile uint32_t CTRL2_0032;
|
||||
volatile uint32_t CTRL2_0033;
|
||||
volatile uint32_t CTRL2_0034;
|
||||
volatile uint32_t CTRL2_0035;
|
||||
volatile uint32_t CTRL2_0036;
|
||||
uint32_t RSVD3[1];
|
||||
volatile uint32_t CTRL2_0040;
|
||||
uint32_t RSVD4[1];
|
||||
volatile uint32_t CTRL2_0042;
|
||||
volatile uint32_t CTRL2_0043;
|
||||
volatile uint32_t CTRL2_0044;
|
||||
volatile uint32_t CTRL2_0045;
|
||||
volatile uint32_t CTRL2_0046;
|
||||
volatile uint32_t CTRL2_0047;
|
||||
volatile uint32_t CTRL2_0050;
|
||||
volatile uint32_t CTRL2_0051;
|
||||
volatile uint32_t CTRL2_0052;
|
||||
volatile uint32_t CTRL2_0053;
|
||||
volatile uint32_t CTRL2_0054;
|
||||
volatile uint32_t CTRL2_0055;
|
||||
volatile uint32_t CTRL2_0056;
|
||||
volatile uint32_t CTRL2_0057;
|
||||
volatile uint32_t CTRL2_0060;
|
||||
volatile uint32_t CTRL2_0061;
|
||||
volatile uint32_t CTRL2_0062;
|
||||
volatile uint32_t CTRL2_0063;
|
||||
volatile uint32_t CTRL2_0064;
|
||||
volatile uint32_t CTRL2_0065;
|
||||
volatile uint32_t CTRL2_0066;
|
||||
volatile uint32_t CTRL2_0067;
|
||||
volatile uint32_t CTRL2_0070;
|
||||
volatile uint32_t CTRL2_0071;
|
||||
volatile uint32_t CTRL2_0072;
|
||||
volatile uint32_t CTRL2_0073;
|
||||
volatile uint32_t CTRL2_0074;
|
||||
volatile uint32_t CTRL2_0075;
|
||||
volatile uint32_t CTRL2_0076;
|
||||
uint32_t RSVD5[1];
|
||||
volatile uint32_t CTRL2_0100;
|
||||
volatile uint32_t CTRL2_0101;
|
||||
volatile uint32_t CTRL2_0102;
|
||||
uint32_t RSVD6[1];
|
||||
volatile uint32_t CTRL2_0104;
|
||||
volatile uint32_t CTRL2_0105;
|
||||
volatile uint32_t CTRL2_0106;
|
||||
volatile uint32_t CTRL2_0107;
|
||||
uint32_t RSVD7[2];
|
||||
volatile uint32_t CTRL2_0112;
|
||||
volatile uint32_t CTRL2_0113;
|
||||
volatile uint32_t CTRL2_0114;
|
||||
volatile uint32_t CTRL2_0115;
|
||||
volatile uint32_t CTRL2_0116;
|
||||
volatile uint32_t CTRL2_0117;
|
||||
volatile uint32_t CTRL2_0120;
|
||||
volatile uint32_t CTRL2_0121;
|
||||
volatile uint32_t CTRL2_0122;
|
||||
volatile uint32_t CTRL2_0123;
|
||||
volatile uint32_t CTRL2_0124;
|
||||
volatile uint32_t CTRL2_0125;
|
||||
volatile uint32_t CTRL2_0126;
|
||||
volatile uint32_t CTRL2_0127;
|
||||
volatile uint32_t CTRL2_0130;
|
||||
volatile uint32_t CTRL2_0131;
|
||||
volatile uint32_t CTRL2_0132;
|
||||
uint32_t RSVD9[5];
|
||||
volatile uint32_t CTRL2_0140;
|
||||
volatile uint32_t CTRL2_0141;
|
||||
volatile uint32_t CTRL2_0142;
|
||||
volatile uint32_t CTRL2_0143;
|
||||
volatile uint32_t CTRL2_0144;
|
||||
volatile uint32_t CTRL2_0145;
|
||||
volatile uint32_t CTRL2_0146;
|
||||
volatile uint32_t CTRL2_0147;
|
||||
volatile uint32_t CTRL2_0150;
|
||||
volatile uint32_t CTRL2_0151;
|
||||
volatile uint32_t CTRL2_0152;
|
||||
volatile uint32_t CTRL2_0153;
|
||||
volatile uint32_t CTRL2_0154;
|
||||
volatile uint32_t CTRL2_0155;
|
||||
volatile uint32_t CTRL2_0156;
|
||||
volatile uint32_t CTRL2_0157;
|
||||
uint32_t RSVD10[1];
|
||||
volatile uint32_t CTRL2_0161;
|
||||
volatile uint32_t CTRL2_0162;
|
||||
uint32_t RSVD11[2];
|
||||
volatile uint32_t CTRL2_0165;
|
||||
uint32_t RSVD12[2];
|
||||
volatile uint32_t CTRL2_0170;
|
||||
volatile uint32_t CTRL2_0171;
|
||||
uint32_t RSVD13[3];
|
||||
volatile uint32_t CTRL2_0175;
|
||||
uint32_t RSVD14[2];
|
||||
volatile uint32_t CTRL2_0200;
|
||||
volatile uint32_t CTRL2_0201;
|
||||
volatile uint32_t CTRL2_0202;
|
||||
volatile uint32_t CTRL2_0203;
|
||||
volatile uint32_t CTRL2_0204;
|
||||
volatile uint32_t CTRL2_0205;
|
||||
volatile uint32_t CTRL2_0206;
|
||||
volatile uint32_t CTRL2_0207;
|
||||
uint32_t RSVD15[9];
|
||||
volatile uint32_t CTRL2_0221;
|
||||
volatile uint32_t CTRL2_0222;
|
||||
volatile uint32_t CTRL2_0223;
|
||||
volatile uint32_t CTRL2_0224;
|
||||
uint32_t RSVD16[1];
|
||||
volatile uint32_t CTRL2_0226;
|
||||
volatile uint32_t CTRL2_0227;
|
||||
uint32_t RSVD17[8];
|
||||
volatile uint32_t CTRL2_0240;
|
||||
volatile uint32_t CTRL2_0241;
|
||||
volatile uint32_t CTRL2_0242;
|
||||
volatile uint32_t CTRL2_0243;
|
||||
volatile uint32_t CTRL2_0244;
|
||||
volatile uint32_t CTRL2_0245;
|
||||
volatile uint32_t CTRL2_0246;
|
||||
uint32_t RSVD18[5];
|
||||
volatile uint32_t CTRL2_0254;
|
||||
volatile uint32_t CTRL2_0255;
|
||||
};
|
||||
|
||||
/** @brief GPIO Parallel Input register. 32 GPIO pins per bank */
|
||||
struct gpio_parin_regs {
|
||||
volatile uint32_t PARIN0;
|
||||
volatile uint32_t PARIN1;
|
||||
volatile uint32_t PARIN2;
|
||||
volatile uint32_t PARIN3;
|
||||
volatile uint32_t PARIN4;
|
||||
volatile uint32_t PARIN5;
|
||||
};
|
||||
|
||||
/** @brief GPIO Parallel Output register. 32 GPIO pins per bank */
|
||||
struct gpio_parout_regs {
|
||||
volatile uint32_t PAROUT0;
|
||||
volatile uint32_t PAROUT1;
|
||||
volatile uint32_t PAROUT2;
|
||||
volatile uint32_t PAROUT3;
|
||||
volatile uint32_t PAROUT4;
|
||||
volatile uint32_t PAROUT5;
|
||||
};
|
||||
|
||||
/** @brief GPIO Lock registers. 32 GPIO pins per bank. Write-once bits */
|
||||
struct gpio_lock_regs {
|
||||
volatile uint32_t LOCK5;
|
||||
volatile uint32_t LOCK4;
|
||||
volatile uint32_t LOCK3;
|
||||
volatile uint32_t LOCK2;
|
||||
volatile uint32_t LOCK1;
|
||||
volatile uint32_t LOCK0;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue