soc: arm: npcx: move workaround methods for npcx series to its soc.c
Move workaround methods for npcx series to soc init functions. If there's no workaround for this series, drop its soc.c file directly. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
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6 changed files with 27 additions and 44 deletions
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@ -275,11 +275,6 @@ static int qspi_npcx_fiu_init(const struct device *dev)
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}
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}
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/* Make sure there is no address field (UMA_ADDR_SIZE is zero) in UMA mode */
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX4)) {
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SET_FIELD(inst->UMA_ECTS, NPCX_UMA_ECTS_UMA_ADDR_SIZE, 0);
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}
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return 0;
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}
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@ -145,16 +145,6 @@ void npcx_dbg_freeze_enable(bool enable)
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/* Pin-control driver registration */
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static int npcx_scfg_init(void)
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{
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struct scfg_reg *inst_scfg = HAL_SFCG_INST();
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/*
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* Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
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* for more information. It will be fixed in next chip.
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*/
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
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inst_scfg->DEVCNT |= BIT(7);
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}
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/* Change all pads whose default functionality isn't IO to GPIO */
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for (int i = 0; i < ARRAY_SIZE(def_alts); i++) {
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npcx_pinctrl_alt_sel(&def_alts[i], 0);
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@ -12,10 +12,25 @@
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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static int soc_init(void)
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#define NPCX_FIU_INST_INIT(node_id) DT_REG_ADDR(node_id),
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static uintptr_t fiu_insts[] = {
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DT_FOREACH_STATUS_OKAY(nuvoton_npcx_fiu_qspi, NPCX_FIU_INST_INIT)
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};
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static int soc_npcx4_init(void)
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{
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/*
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* Make sure UMA_ADDR_SIZE field of UMA_ECTS register is zero in npcx4
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* series. There should be no address field in UMA mode by default.
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*/
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for (int i = 0; i < ARRAY_SIZE(fiu_insts); i++) {
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struct fiu_reg *const inst = (struct fiu_reg *)(fiu_insts[i]);
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SET_FIELD(inst->UMA_ECTS, NPCX_UMA_ECTS_UMA_ADDR_SIZE, 0);
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}
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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SYS_INIT(soc_npcx4_init, PRE_KERNEL_1, 0);
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@ -12,10 +12,18 @@
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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static int soc_init(void)
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static int soc_npcx7_init(void)
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{
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struct scfg_reg *inst_scfg = (struct scfg_reg *)
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DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg);
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/*
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* Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
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* for more information. It will be fixed in next chip.
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*/
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inst_scfg->DEVCNT |= BIT(7);
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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SYS_INIT(soc_npcx7_init, PRE_KERNEL_1, 0);
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@ -1,7 +1,3 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_sources(
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soc.c
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)
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@ -1,21 +0,0 @@
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/*
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* Copyright (c) 2021 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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static int soc_init(void)
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{
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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