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soc: arm: npcx: move workaround methods for npcx series to its soc.c

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Move workaround methods for npcx series to soc init functions. If
there's no workaround for this series, drop its soc.c file directly.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Mulin Chao 2023-08-20 19:27:47 -07:00 • committed by Fabio Baltieri
commit f942b44c56
6 changed files with 27 additions and 44 deletions
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5
drivers/flash/flash_npcx_fiu_qspi.c
View file

@ -275,11 +275,6 @@ static int qspi_npcx_fiu_init(const struct device *dev)
}
}
/* Make sure there is no address field (UMA_ADDR_SIZE is zero) in UMA mode */
if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX4)) {
SET_FIELD(inst->UMA_ECTS, NPCX_UMA_ECTS_UMA_ADDR_SIZE, 0);
}
return 0;
}

10
soc/arm/nuvoton_npcx/common/scfg.c
View file

@ -145,16 +145,6 @@ void npcx_dbg_freeze_enable(bool enable)
/* Pin-control driver registration */
static int npcx_scfg_init(void)
{
struct scfg_reg *inst_scfg = HAL_SFCG_INST();
/*
* Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
* for more information. It will be fixed in next chip.
*/
if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
inst_scfg->DEVCNT |= BIT(7);
}
/* Change all pads whose default functionality isn't IO to GPIO */
for (int i = 0; i < ARRAY_SIZE(def_alts); i++) {
npcx_pinctrl_alt_sel(&def_alts[i], 0);

19
soc/arm/nuvoton_npcx/npcx4/soc.c
View file

@ -12,10 +12,25 @@
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
static int soc_init(void)
#define NPCX_FIU_INST_INIT(node_id) DT_REG_ADDR(node_id),
static uintptr_t fiu_insts[] = {
DT_FOREACH_STATUS_OKAY(nuvoton_npcx_fiu_qspi, NPCX_FIU_INST_INIT)
};
static int soc_npcx4_init(void)
{
/*
* Make sure UMA_ADDR_SIZE field of UMA_ECTS register is zero in npcx4
* series. There should be no address field in UMA mode by default.
*/
for (int i = 0; i < ARRAY_SIZE(fiu_insts); i++) {
struct fiu_reg *const inst = (struct fiu_reg *)(fiu_insts[i]);
SET_FIELD(inst->UMA_ECTS, NPCX_UMA_ECTS_UMA_ADDR_SIZE, 0);
}
return 0;
}
SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
SYS_INIT(soc_npcx4_init, PRE_KERNEL_1, 0);

12
soc/arm/nuvoton_npcx/npcx7/soc.c
View file

@ -12,10 +12,18 @@
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
static int soc_init(void)
static int soc_npcx7_init(void)
{
struct scfg_reg *inst_scfg = (struct scfg_reg *)
DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg);
/*
* Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
* for more information. It will be fixed in next chip.
*/
inst_scfg->DEVCNT |= BIT(7);
return 0;
}
SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
SYS_INIT(soc_npcx7_init, PRE_KERNEL_1, 0);

4
soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt
View file

@ -1,7 +1,3 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(${ZEPHYR_BASE}/drivers)
zephyr_sources(
soc.c
)

21
soc/arm/nuvoton_npcx/npcx9/soc.c
View file

@ -1,21 +0,0 @@
/*
* Copyright (c) 2021 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
static int soc_init(void)
{
return 0;
}
SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);