soc: nxp_s32: introduce support for S32K1 devices

Introduce support for NXP S32K1 family of 32-bit MCUs, and
particularly for S32K146 devices. S32K1 share a fair amount of
similarities with Kinetis family, so most of the peripheral drivers
can be reused.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles 2023-11-16 21:48:32 +07:00 committed by Anas Nashif
commit 91293187d8
13 changed files with 801 additions and 1 deletions

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#include <OsIf.h>
#include <OsIf_Cfg_TypesDef.h>
#if defined(CONFIG_SOC_SERIES_S32K1XX)
/* Aliases needed to build with different SoC-specific HAL versions */
#define CPXNUM CPxNUM
#define MSCM_CPXNUM_CPN_MASK MSCM_CPxNUM_CPN_MASK
#endif
/* Required by OsIf timer initialization but not used with Zephyr, so no values configured */
static const OsIf_ConfigType osif_config;
const OsIf_ConfigType *const OsIf_apxPredefinedConfig[OSIF_MAX_COREIDX_SUPPORTED] = {

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# Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
zephyr_sources(soc.c)
zephyr_sources_ifdef(CONFIG_ARM_MPU nxp_mpu_regions.c)
zephyr_sources_ifdef(CONFIG_NXP_S32_FLASH_CONFIG flash_configuration.c)
zephyr_linker_sources_ifdef(CONFIG_NXP_S32_FLASH_CONFIG ROM_START SORT_KEY 0x1 flash_config.ld)

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# NXP S32K146
# Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_S32K146
config SOC
default "s32k146"
config FPU
default y
endif # SOC_S32K146

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# NXP S32K1XX MCU series
# Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_S32K1XX
config SOC_SERIES
default "s32k1"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 80000000
config NUM_IRQS
default 239 if CPU_CORTEX_M4
default 47 if CPU_CORTEX_M0PLUS
if !XIP
config FLASH_SIZE
default 0
config FLASH_BASE_ADDRESS
default 0
endif
# The S32K1xx have 8 MPU regions, which is not enough for both HW stack protection
# and userspace. Only enable HW stack protection if userspace is not enabled.
config HW_STACK_PROTECTION
default y if !USERSPACE
source "soc/arm/nxp_s32/s32k1/Kconfig.defconfig.s32k1*"
endif # SOC_SERIES_S32K1XX

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# NXP S32K1XX MCU series
# Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_S32K1XX
bool "NXP S32K1XX MCU series"
select ARM
select SOC_FAMILY_NXP_S32
select HAS_NXP_S32_HAL
select HAS_MCUX
select CPU_HAS_NXP_MPU
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
select MPU_ALLOW_FLASH_WRITE if !XIP
select CLOCK_CONTROL
select HAS_MCUX_LPUART
help
Enable support for NXP S32K1XX MCU series.

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# NXP S32K1XX MCUs line
# Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0
choice
prompt "NXP S32K1XX MCU selection"
depends on SOC_SERIES_S32K1XX
config SOC_S32K116
bool "S32K116"
select CPU_CORTEX_M0PLUS
config SOC_S32K118
bool "S32K118"
select CPU_CORTEX_M0PLUS
config SOC_S32K142
bool "S32K142"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
config SOC_S32K142W
bool "S32K142W"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
config SOC_S32K144
bool "S32K144"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
config SOC_S32K144W
bool "S32K144W"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
config SOC_S32K146
bool "S32K146"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
config SOC_S32K148
bool "S32K148"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
endchoice
if SOC_SERIES_S32K1XX
config SOC_PART_NUMBER_FS32K116LAT0MFMT
bool
config SOC_PART_NUMBER_FS32K116LAT0MLFR
bool
config SOC_PART_NUMBER_FS32K116LAT0MLFT
bool
config SOC_PART_NUMBER_FS32K116LIT0VFMT
bool
config SOC_PART_NUMBER_FS32K116LIT0VLFT
bool
config SOC_PART_NUMBER_FS32K118LAT0MLFR
bool
config SOC_PART_NUMBER_FS32K118LAT0MLFT
bool
config SOC_PART_NUMBER_FS32K118LAT0MLHR
bool
config SOC_PART_NUMBER_FS32K118LAT0MLHT
bool
config SOC_PART_NUMBER_FS32K118LIT0VLFT
bool
config SOC_PART_NUMBER_FS32K142HAT0MLFT
bool
config SOC_PART_NUMBER_FS32K142HAT0MLHT
bool
config SOC_PART_NUMBER_FS32K142HAT0MLLR
bool
config SOC_PART_NUMBER_FS32K142HAT0MLLT
bool
config SOC_PART_NUMBER_FS32K142HVT0VLHT
bool
config SOC_PART_NUMBER_FS32K142UAT0VLFT
bool
config SOC_PART_NUMBER_FS32K142UAT0VLHR
bool
config SOC_PART_NUMBER_FS32K142UAT0VLHT
bool
config SOC_PART_NUMBER_FS32K142UAT0VLLR
bool
config SOC_PART_NUMBER_FS32K142UAT0VLLT
bool
config SOC_PART_NUMBER_FS32K142UIT0VLHT
bool
config SOC_PART_NUMBER_FS32K142WAT0WLFT
bool
config SOC_PART_NUMBER_FS32K142WAT0WLHT
bool
config SOC_PART_NUMBER_FS32K144HAT0MLFT
bool
config SOC_PART_NUMBER_FS32K144HAT0MLHR
bool
config SOC_PART_NUMBER_FS32K144HAT0MLHT
bool
config SOC_PART_NUMBER_FS32K144HAT0MLLR
bool
config SOC_PART_NUMBER_FS32K144HAT0MLLT
bool
config SOC_PART_NUMBER_FS32K144HAT0MMHR
bool
config SOC_PART_NUMBER_FS32K144HAT0MMHT
bool
config SOC_PART_NUMBER_FS32K144HVT0VLHR
bool
config SOC_PART_NUMBER_FS32K144HVT0VLHT
bool
config SOC_PART_NUMBER_FS32K144HXT0VLHT
bool
config SOC_PART_NUMBER_FS32K144HXT0VLLT
bool
config SOC_PART_NUMBER_FS32K144UAT0VLFT
bool
config SOC_PART_NUMBER_FS32K144UAT0VLHR
bool
config SOC_PART_NUMBER_FS32K144UAT0VLHT
bool
config SOC_PART_NUMBER_FS32K144UAT0VLLT
bool
config SOC_PART_NUMBER_FS32K144UAT0VMHR
bool
config SOC_PART_NUMBER_FS32K144UAT0VMHT
bool
config SOC_PART_NUMBER_FS32K144UIT0VLHT
bool
config SOC_PART_NUMBER_FS32K144ULT0VLHT
bool
config SOC_PART_NUMBER_FS32K144ULT0VLLR
bool
config SOC_PART_NUMBER_FS32K144ULT0VLLT
bool
config SOC_PART_NUMBER_FS32K144WAT0WLFT
bool
config SOC_PART_NUMBER_FS32K144WAT0WLHT
bool
config SOC_PART_NUMBER_FS32K146HAT0MLHR
bool
config SOC_PART_NUMBER_FS32K146HAT0MLHT
bool
config SOC_PART_NUMBER_FS32K146HAT0MLLR
bool
config SOC_PART_NUMBER_FS32K146HAT0MLLT
bool
config SOC_PART_NUMBER_FS32K146HAT0MLQR
bool
config SOC_PART_NUMBER_FS32K146HAT0MLQT
bool
config SOC_PART_NUMBER_FS32K146HAT0MMHR
bool
config SOC_PART_NUMBER_FS32K146HAT0MMHT
bool
config SOC_PART_NUMBER_FS32K146HVT0VLHT
bool
config SOC_PART_NUMBER_FS32K146HXT0VLLT
bool
config SOC_PART_NUMBER_FS32K146UAT0VLHR
bool
config SOC_PART_NUMBER_FS32K146UAT0VLHT
bool
config SOC_PART_NUMBER_FS32K146UAT0VLLR
bool
config SOC_PART_NUMBER_FS32K146UAT0VLLT
bool
config SOC_PART_NUMBER_FS32K146UAT0VLQR
bool
config SOC_PART_NUMBER_FS32K146UAT0VLQT
bool
config SOC_PART_NUMBER_FS32K146UAT0VMHR
bool
config SOC_PART_NUMBER_FS32K146UAT0VMHT
bool
config SOC_PART_NUMBER_FS32K146UIT0VLLT
bool
config SOC_PART_NUMBER_FS32K146ULT0VLLT
bool
config SOC_PART_NUMBER_FS32K148HAT0MLLR
bool
config SOC_PART_NUMBER_FS32K148HAT0MLLT
bool
config SOC_PART_NUMBER_FS32K148HAT0MLQR
bool
config SOC_PART_NUMBER_FS32K148HAT0MLQT
bool
config SOC_PART_NUMBER_FS32K148HAT0MLUT
bool
config SOC_PART_NUMBER_FS32K148HAT0MMHT
bool
config SOC_PART_NUMBER_FS32K148UGT0VLQT
bool
config SOC_PART_NUMBER_FS32K148UIT0VLQT
bool
config SOC_PART_NUMBER_FS32K148UJT0VLLT
bool
config SOC_PART_NUMBER_FS32K148UJT0VLQT
bool
config SOC_PART_NUMBER_FS32K148UJT0VLUT
bool
config SOC_PART_NUMBER_FS32K148UJT0VMHR
bool
config SOC_PART_NUMBER_FS32K148UJT0VMHT
bool
config SOC_PART_NUMBER_S32K1XX
string
default "FS32K116LAT0MFMT" if SOC_PART_NUMBER_FS32K116LAT0MFMT
default "FS32K116LAT0MLFR" if SOC_PART_NUMBER_FS32K116LAT0MLFR
default "FS32K116LAT0MLFT" if SOC_PART_NUMBER_FS32K116LAT0MLFT
default "FS32K116LIT0VFMT" if SOC_PART_NUMBER_FS32K116LIT0VFMT
default "FS32K116LIT0VLFT" if SOC_PART_NUMBER_FS32K116LIT0VLFT
default "FS32K118LAT0MLFR" if SOC_PART_NUMBER_FS32K118LAT0MLFR
default "FS32K118LAT0MLFT" if SOC_PART_NUMBER_FS32K118LAT0MLFT
default "FS32K118LAT0MLHR" if SOC_PART_NUMBER_FS32K118LAT0MLHR
default "FS32K118LAT0MLHT" if SOC_PART_NUMBER_FS32K118LAT0MLHT
default "FS32K118LIT0VLFT" if SOC_PART_NUMBER_FS32K118LIT0VLFT
default "FS32K142HAT0MLFT" if SOC_PART_NUMBER_FS32K142HAT0MLFT
default "FS32K142HAT0MLHT" if SOC_PART_NUMBER_FS32K142HAT0MLHT
default "FS32K142HAT0MLLR" if SOC_PART_NUMBER_FS32K142HAT0MLLR
default "FS32K142HAT0MLLT" if SOC_PART_NUMBER_FS32K142HAT0MLLT
default "FS32K142HVT0VLHT" if SOC_PART_NUMBER_FS32K142HVT0VLHT
default "FS32K142UAT0VLFT" if SOC_PART_NUMBER_FS32K142UAT0VLFT
default "FS32K142UAT0VLHR" if SOC_PART_NUMBER_FS32K142UAT0VLHR
default "FS32K142UAT0VLHT" if SOC_PART_NUMBER_FS32K142UAT0VLHT
default "FS32K142UAT0VLLR" if SOC_PART_NUMBER_FS32K142UAT0VLLR
default "FS32K142UAT0VLLT" if SOC_PART_NUMBER_FS32K142UAT0VLLT
default "FS32K142UIT0VLHT" if SOC_PART_NUMBER_FS32K142UIT0VLHT
default "FS32K142WAT0WLFT" if SOC_PART_NUMBER_FS32K142WAT0WLFT
default "FS32K142WAT0WLHT" if SOC_PART_NUMBER_FS32K142WAT0WLHT
default "FS32K144HAT0MLFT" if SOC_PART_NUMBER_FS32K144HAT0MLFT
default "FS32K144HAT0MLHR" if SOC_PART_NUMBER_FS32K144HAT0MLHR
default "FS32K144HAT0MLHT" if SOC_PART_NUMBER_FS32K144HAT0MLHT
default "FS32K144HAT0MLLR" if SOC_PART_NUMBER_FS32K144HAT0MLLR
default "FS32K144HAT0MLLT" if SOC_PART_NUMBER_FS32K144HAT0MLLT
default "FS32K144HAT0MMHR" if SOC_PART_NUMBER_FS32K144HAT0MMHR
default "FS32K144HAT0MMHT" if SOC_PART_NUMBER_FS32K144HAT0MMHT
default "FS32K144HVT0VLHR" if SOC_PART_NUMBER_FS32K144HVT0VLHR
default "FS32K144HVT0VLHT" if SOC_PART_NUMBER_FS32K144HVT0VLHT
default "FS32K144HXT0VLHT" if SOC_PART_NUMBER_FS32K144HXT0VLHT
default "FS32K144HXT0VLLT" if SOC_PART_NUMBER_FS32K144HXT0VLLT
default "FS32K144UAT0VLFT" if SOC_PART_NUMBER_FS32K144UAT0VLFT
default "FS32K144UAT0VLHR" if SOC_PART_NUMBER_FS32K144UAT0VLHR
default "FS32K144UAT0VLHT" if SOC_PART_NUMBER_FS32K144UAT0VLHT
default "FS32K144UAT0VLLT" if SOC_PART_NUMBER_FS32K144UAT0VLLT
default "FS32K144UAT0VMHR" if SOC_PART_NUMBER_FS32K144UAT0VMHR
default "FS32K144UAT0VMHT" if SOC_PART_NUMBER_FS32K144UAT0VMHT
default "FS32K144UIT0VLHT" if SOC_PART_NUMBER_FS32K144UIT0VLHT
default "FS32K144ULT0VLHT" if SOC_PART_NUMBER_FS32K144ULT0VLHT
default "FS32K144ULT0VLLR" if SOC_PART_NUMBER_FS32K144ULT0VLLR
default "FS32K144ULT0VLLT" if SOC_PART_NUMBER_FS32K144ULT0VLLT
default "FS32K144WAT0WLFT" if SOC_PART_NUMBER_FS32K144WAT0WLFT
default "FS32K144WAT0WLHT" if SOC_PART_NUMBER_FS32K144WAT0WLHT
default "FS32K146HAT0MLHR" if SOC_PART_NUMBER_FS32K146HAT0MLHR
default "FS32K146HAT0MLHT" if SOC_PART_NUMBER_FS32K146HAT0MLHT
default "FS32K146HAT0MLLR" if SOC_PART_NUMBER_FS32K146HAT0MLLR
default "FS32K146HAT0MLLT" if SOC_PART_NUMBER_FS32K146HAT0MLLT
default "FS32K146HAT0MLQR" if SOC_PART_NUMBER_FS32K146HAT0MLQR
default "FS32K146HAT0MLQT" if SOC_PART_NUMBER_FS32K146HAT0MLQT
default "FS32K146HAT0MMHR" if SOC_PART_NUMBER_FS32K146HAT0MMHR
default "FS32K146HAT0MMHT" if SOC_PART_NUMBER_FS32K146HAT0MMHT
default "FS32K146HVT0VLHT" if SOC_PART_NUMBER_FS32K146HVT0VLHT
default "FS32K146HXT0VLLT" if SOC_PART_NUMBER_FS32K146HXT0VLLT
default "FS32K146UAT0VLHR" if SOC_PART_NUMBER_FS32K146UAT0VLHR
default "FS32K146UAT0VLHT" if SOC_PART_NUMBER_FS32K146UAT0VLHT
default "FS32K146UAT0VLLR" if SOC_PART_NUMBER_FS32K146UAT0VLLR
default "FS32K146UAT0VLLT" if SOC_PART_NUMBER_FS32K146UAT0VLLT
default "FS32K146UAT0VLQR" if SOC_PART_NUMBER_FS32K146UAT0VLQR
default "FS32K146UAT0VLQT" if SOC_PART_NUMBER_FS32K146UAT0VLQT
default "FS32K146UAT0VMHR" if SOC_PART_NUMBER_FS32K146UAT0VMHR
default "FS32K146UAT0VMHT" if SOC_PART_NUMBER_FS32K146UAT0VMHT
default "FS32K146UIT0VLLT" if SOC_PART_NUMBER_FS32K146UIT0VLLT
default "FS32K146ULT0VLLT" if SOC_PART_NUMBER_FS32K146ULT0VLLT
default "FS32K148HAT0MLLR" if SOC_PART_NUMBER_FS32K148HAT0MLLR
default "FS32K148HAT0MLLT" if SOC_PART_NUMBER_FS32K148HAT0MLLT
default "FS32K148HAT0MLQR" if SOC_PART_NUMBER_FS32K148HAT0MLQR
default "FS32K148HAT0MLQT" if SOC_PART_NUMBER_FS32K148HAT0MLQT
default "FS32K148HAT0MLUT" if SOC_PART_NUMBER_FS32K148HAT0MLUT
default "FS32K148HAT0MMHT" if SOC_PART_NUMBER_FS32K148HAT0MMHT
default "FS32K148UGT0VLQT" if SOC_PART_NUMBER_FS32K148UGT0VLQT
default "FS32K148UIT0VLQT" if SOC_PART_NUMBER_FS32K148UIT0VLQT
default "FS32K148UJT0VLLT" if SOC_PART_NUMBER_FS32K148UJT0VLLT
default "FS32K148UJT0VLQT" if SOC_PART_NUMBER_FS32K148UJT0VLQT
default "FS32K148UJT0VLUT" if SOC_PART_NUMBER_FS32K148UJT0VLUT
default "FS32K148UJT0VMHR" if SOC_PART_NUMBER_FS32K148UJT0VMHR
default "FS32K148UJT0VMHT" if SOC_PART_NUMBER_FS32K148UJT0VMHT
help
This string holds the full part number of the SoC. It is a hidden option
that you should not set directly. The part number selection choice defines
the default value for this string.
config WDOG_INIT
bool
default y
config NXP_S32_FLASH_CONFIG
bool "NXP S32 flash configuration field"
default y if XIP && !BOOTLOADER_MCUBOOT
help
Include the 16-byte flash configuration field that stores default
protection settings (loaded on reset) and security information that
allows the MCU to restrict access to the FTFx module.
if NXP_S32_FLASH_CONFIG
config NXP_S32_FLASH_CONFIG_OFFSET
hex "NXP S32 flash configuration field offset"
default 0x400
config NXP_S32_FLASH_CONFIG_FSEC
hex "Flash security byte (FSEC)"
range 0 0xff
default 0xfe
help
Configures the reset value of the FSEC register, which includes
backdoor key access, mass erase, factory access, and flash security
options.
config NXP_S32_FLASH_CONFIG_FOPT
hex "Flash nonvolatile option byte (FOPT)"
range 0 0xff
default 0xff
help
Configures the reset value of the FOPT register, which includes boot,
NMI, and EzPort options.
config NXP_S32_FLASH_CONFIG_FEPROT
hex "EEPROM protection byte (FEPROT)"
range 0 0xff
default 0xff
help
Configures the reset value of the FEPROT register for FlexNVM
devices. For program flash only devices, this byte is reserved.
config NXP_S32_FLASH_CONFIG_FDPROT
hex "Data flash protection byte (FDPROT)"
range 0 0xff
default 0xff
help
Configures the reset value of the FDPROT register for FlexNVM
devices. For program flash only devices, this byte is reserved.
endif # NXP_S32_FLASH_CONFIG
endif # SOC_SERIES_S32K1XX

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/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
. = CONFIG_NXP_S32_FLASH_CONFIG_OFFSET;
KEEP(*(.kinetis_flash_config))
KEEP(*(".kinetis_flash_config.*"))

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/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/linker/sections.h>
uint8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
/* Backdoor Comparison Key (unused) */
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected */
0xFF, 0xFF, 0xFF, 0xFF,
/* Flash security register (FSEC) enables/disables backdoor key access,
* mass erase, factory access, and flash security
*/
CONFIG_NXP_S32_FLASH_CONFIG_FSEC,
/* Flash nonvolatile option register (FOPT) enables/disables NMI,
* EzPort, and boot options
*/
CONFIG_NXP_S32_FLASH_CONFIG_FOPT,
/* EEPROM protection register (FEPROT) for FlexNVM devices */
CONFIG_NXP_S32_FLASH_CONFIG_FEPROT,
/* Data flash protection register (FDPROT) for FlexNVM devices */
CONFIG_NXP_S32_FLASH_CONFIG_FDPROT,
};

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/*
* Copyright 2023 NXP
*
* Based on soc/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c, which is:
* Copyright (c) 2017 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <zephyr/arch/arm/mpu/nxp_mpu.h>
static const struct nxp_mpu_region mpu_regions[] = {
/* Region 0 */
MPU_REGION_ENTRY("DEBUGGER",
0,
0xFFFFFFFF,
REGION_DEBUGGER_AND_DEVICE_ATTR),
/* Region 1 */
MPU_REGION_ENTRY("BACKGROUND_0",
0,
CONFIG_SRAM_BASE_ADDRESS-1,
REGION_BACKGROUND_ATTR),
/* Region 2 */
MPU_REGION_ENTRY("BACKGROUND_1",
CONFIG_SRAM_BASE_ADDRESS +
(CONFIG_SRAM_SIZE * 1024),
0xFFFFFFFF,
REGION_BACKGROUND_ATTR),
#if defined(CONFIG_XIP)
/* Region 3 */
MPU_REGION_ENTRY("SRAM",
CONFIG_SRAM_BASE_ADDRESS,
(CONFIG_SRAM_BASE_ADDRESS +
(CONFIG_SRAM_SIZE * 1024) - 1),
REGION_RAM_ATTR),
/* Region 4 */
MPU_REGION_ENTRY("FLASH",
CONFIG_FLASH_BASE_ADDRESS,
(CONFIG_FLASH_BASE_ADDRESS +
(CONFIG_FLASH_SIZE * 1024) - 1),
REGION_FLASH_ATTR),
#else
/* Region 3 */
MPU_REGION_ENTRY("SRAM",
CONFIG_SRAM_BASE_ADDRESS,
(CONFIG_SRAM_BASE_ADDRESS +
(CONFIG_SRAM_SIZE * 1024) - 1),
REGION_FLASH_ATTR),
#endif
};
const struct nxp_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
.sram_region = 3,
};

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/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* @file
* NXP S32K1 SOC specific helpers for pinctrl driver
*/
#ifndef ZEPHYR_SOC_ARM_NXP_S32_S32K1_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_S32_S32K1_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
typedef uint32_t pinctrl_soc_pin_t;
#define Z_PINCTRL_KINETIS_PINCFG(node_id) \
(PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \
PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
#define Z_PINCTRL_KINETIS_PCR_MASK \
(PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_PFE_MASK | \
PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_KINETIS_PINCFG(group),
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_NXP_S32_S32K1_PINCTRL_SOC_H_ */

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/*
* Copyright 2023 NXP
*
* Based on zephyr/soc/arm/nxp_kinetis/ke1xf/soc.c, which is:
* Copyright (c) 2019-2021 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/sys/barrier.h>
#include <cmsis_core.h>
#include <OsIf.h>
#if defined(CONFIG_WDOG_INIT)
#define WDOG_UPDATE_KEY 0xD928C520U
void z_arm_watchdog_init(void)
{
/*
* NOTE: DO NOT SINGLE STEP THROUGH THIS SECTION!!! Watchdog
* reconfiguration must take place within 128 bus clocks from
* unlocking. Single stepping through the code will cause the
* watchdog to close the unlock window again.
*/
if ((IP_WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U) {
IP_WDOG->CNT = WDOG_UPDATE_KEY;
} else {
IP_WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU;
IP_WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU;
}
while (!(IP_WDOG->CS & WDOG_CS_ULK_MASK)) {
;
}
IP_WDOG->TOVAL = 0xFFFFU;
IP_WDOG->CS = (uint32_t) ((IP_WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
/* Wait for new configuration to take effect */
while (!(IP_WDOG->CS & WDOG_CS_RCS_MASK)) {
;
}
}
#endif /* CONFIG_WDOG_INIT */
static int soc_init(void)
{
#if !defined(CONFIG_ARM_MPU)
uint32_t tmp;
/*
* Disable memory protection and clear slave port errors.
* Note that the S32K1xx does not implement the optional Arm MPU but
* instead the Soc includes its own NXP MPU module.
*/
tmp = IP_MPU->CESR;
tmp &= ~MPU_CESR_VLD_MASK;
tmp |= MPU_CESR_SPERR0_MASK | MPU_CESR_SPERR1_MASK
| MPU_CESR_SPERR2_MASK | MPU_CESR_SPERR3_MASK;
IP_MPU->CESR = tmp;
#endif /* !CONFIG_ARM_MPU */
#if defined(CONFIG_DCACHE) && defined(CONFIG_ICACHE)
/* Invalidate all ways */
IP_LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
IP_LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;
/* Wait until the command completes */
while (IP_LMEM->PCCCR & LMEM_PCCCR_GO_MASK) {
;
}
/* Enable cache */
IP_LMEM->PCCCR |= (LMEM_PCCCR_ENCACHE_MASK);
barrier_isync_fence_full();
#endif
OsIf_Init(NULL);
return 0;
}
SYS_INIT(soc_init, PRE_KERNEL_1, 0);

View file

@ -0,0 +1,39 @@
/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _NXP_S32_S32K1_SOC_H_
#define _NXP_S32_S32K1_SOC_H_
#include <fsl_port.h>
#if defined(CONFIG_SOC_S32K116)
#include <S32K116.h>
#elif defined(CONFIG_SOC_S32K118)
#include <S32K118.h>
#elif defined(CONFIG_SOC_S32K142)
#include <S32K142.h>
#elif defined(CONFIG_SOC_S32K142W)
#include <S32K142W.h>
#elif defined(CONFIG_SOC_S32K144)
#include <S32K144.h>
#elif defined(CONFIG_SOC_S32K144W)
#include <S32K144W.h>
#elif defined(CONFIG_SOC_S32K146)
#include <S32K146.h>
#elif defined(CONFIG_SOC_S32K148)
#include <S32K148.h>
#else
#error "SoC not supported"
#endif
#if defined(CONFIG_CMSIS_RTOS_V2)
#include <cmsis_rtos_v2_adapt.h>
#endif
/* GPIO setting for the Port Mux Register */
#define PORT_MUX_GPIO kPORT_MuxAsGpio
#endif /* _NXP_S32_S32K1_SOC_H_ */

View file

@ -193,7 +193,7 @@ manifest:
groups:
- hal
- name: hal_nxp
revision: 1ed023da7f5541b78099b5a030507a2839ce554f
revision: 2796169ee23dc838311b65758806eb94546a7bc2
path: modules/hal/nxp
groups:
- hal