soc: arm: nxp_imx: rt11xx: add support for CONFIG_ETH_MCUX_RMII_EXT_CLK
ENET_REF_CLK as an input during rt11xx clock initialization. Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
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2 changed files with 14 additions and 1 deletions
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@ -38,8 +38,9 @@
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group3 {
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pinmux = <&iomuxc_gpio_disp_b1_11_enet_1g_ref_clk1>;
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drive-strength = "high";
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slew-rate = "slow";
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slew-rate = "fast";
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input-enable;
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bias-pull-down;
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};
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};
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@ -402,10 +402,16 @@ static ALWAYS_INLINE void clock_init(void)
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rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2;
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rootCfg.div = 10;
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CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
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#if CONFIG_ETH_MCUX_RMII_EXT_CLK
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/* Set ENET_REF_CLK as an input driven by PHY */
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IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U);
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IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U);
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#else
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/* Set ENET_REF_CLK as an output driven by ENET1_CLK_ROOT */
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IOMUXC_GPR->GPR4 |= (IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U) |
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IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U));
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#endif
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet1g), okay)
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/*
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* 50 MHz clock for 10/100Mbit RMII PHY -
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@ -414,11 +420,17 @@ static ALWAYS_INLINE void clock_init(void)
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rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2;
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rootCfg.div = 10;
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CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
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#if CONFIG_ETH_MCUX_RMII_EXT_CLK
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/* Set ENET1G_REF_CLK as an input driven by PHY */
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IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U);
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IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U);
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#else
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/* Set ENET1G_REF_CLK as an output driven by ENET2_CLK_ROOT */
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IOMUXC_GPR->GPR5 |= (IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U) |
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IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U));
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#endif
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#endif
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#endif
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#ifdef CONFIG_PTP_CLOCK_MCUX
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/* 24MHz PTP clock */
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