soc: arm: lpc55xxx: Updated clock init
Updated the clock init to reflect the sdk also updated the clock frequencies to reflect the respective soc clock values, this file originally contained unexpected clock values, updated comments to reflect changes and got rid of doxygen style comments Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
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2 changed files with 105 additions and 36 deletions
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@ -1,6 +1,6 @@
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# LPC LPC55XXX Series
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# Copyright (c) 2019, NXP
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# Copyright 2019, 2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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choice
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@ -120,6 +120,14 @@ config SOC_PART_NUMBER_LPC55XXX
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config INIT_PLL0
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bool "Initialize PLL0"
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config INIT_PLL1
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bool "Initialize PLL1"
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default "y"
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depends on !SOC_LPC55S06
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help
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In the LPC55XXX Family, this is currently being used to set the
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core clock value at it's highest frequency which clocks at 150MHz.
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config SECOND_CORE_MCUX
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bool "LPC55xxx's second core"
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depends on HAS_MCUX
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@ -35,6 +35,13 @@
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#include <fsl_vref.h>
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#endif
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/* System clock frequency */
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extern uint32_t SystemCoreClock;
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/*Should be in the range of 12MHz to 32MHz */
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static uint32_t ExternalClockFrequency;
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#define CTIMER_CLOCK_SOURCE(node_id) \
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TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source))
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#define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val)
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@ -44,13 +51,25 @@
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#ifdef CONFIG_INIT_PLL0
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const pll_setup_t pll0Setup = {
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.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(2U) |
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SYSCON_PLL0CTRL_SELP(31U),
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SYSCON_PLL0CTRL_SELP(31U),
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.pllndec = SYSCON_PLL0NDEC_NDIV(125U),
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.pllpdec = SYSCON_PLL0PDEC_PDIV(8U),
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.pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(3072U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
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.pllRate = 24576000U,
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.flags = PLL_SETUPFLAG_WAITLOCK}
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;
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.flags = PLL_SETUPFLAG_WAITLOCK
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};
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#endif
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#ifdef CONFIG_INIT_PLL1
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const pll_setup_t pll1Setup = {
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.pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) |
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SYSCON_PLL1CTRL_SELP(31U),
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.pllndec = SYSCON_PLL1NDEC_NDIV(8U),
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.pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
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.pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
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.pllRate = 150000000U,
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.flags = PLL_SETUPFLAG_WAITLOCK
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};
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#endif
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/**
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@ -61,6 +80,7 @@ const pll_setup_t pll0Setup = {
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static ALWAYS_INLINE void clock_init(void)
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{
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ExternalClockFrequency = 0;
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#if defined(CONFIG_SOC_LPC55S36)
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/* Power Management Controller initialization */
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@ -70,50 +90,91 @@ static ALWAYS_INLINE void clock_init(void)
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#if defined(CONFIG_SOC_LPC55S06) || defined(CONFIG_SOC_LPC55S16) || \
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defined(CONFIG_SOC_LPC55S28) || defined(CONFIG_SOC_LPC55S36) || \
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defined(CONFIG_SOC_LPC55S69_CPU0)
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/*!< Set up the clock sources */
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/*!< Configure FRO192M */
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/*!< Ensure FRO is on */
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/* Set up the clock sources */
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/* Configure FRO192M */
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/* Ensure FRO is on */
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POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
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/*!< Set up FRO to the 12 MHz, just for sure */
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/* Set up FRO to the 12 MHz, to ensure we can change the clock freq */
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CLOCK_SetupFROClocking(12000000U);
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/*!< Switch to FRO 12MHz first to ensure we can change the clock */
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/* Switch to FRO 12MHz first to ensure we can change the clock */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
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/* Enable FRO HF(96MHz) output */
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CLOCK_SetupFROClocking(96000000U);
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#ifdef CONFIG_INIT_PLL0
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/*!< Ensure XTAL16M is on */
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PMC->PDRUNCFGCLR0 |= PMC_PDRUNCFG0_PDEN_XTAL32M_MASK;
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PMC->PDRUNCFGCLR0 |= PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK;
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/*!< Ensure CLK_IN is on */
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/* Ensure CLK_IN is on */
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SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;
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ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
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/*!< Switch PLL0 clock source selector to XTAL16M */
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CLOCK_AttachClk(kEXT_CLK_to_PLL0);
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/*!< Configure PLL to the desired values */
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CLOCK_SetPLL0Freq(&pll0Setup);
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CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);
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CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 1U, false);
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/* Setting the Core Clock to either 96MHz or in the case of using PLL, 150MHz */
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#if defined(CONFIG_SOC_LPC55S06) || !defined(CONFIG_INIT_PLL1)
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SystemCoreClock = 96000000U;
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#else
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SystemCoreClock = 150000000U;
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#endif
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/* These functions must be called before increasing to a higher frequency
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* Additionally, CONFIG_TRUSTED_EXECUTION_NONSECURE is being used
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* since the non-secure SOCs should not have access to the flash
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* as this will cause a secure fault to occur
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*/
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#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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/* Set Voltage for one of the fastest clock outputs: System clock output */
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POWER_SetVoltageForFreq(SystemCoreClock);
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/*!< Set FLASH wait states for core */
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CLOCK_SetFLASHAccessCyclesForFreq(96000000U);
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CLOCK_SetFLASHAccessCyclesForFreq(SystemCoreClock);
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#endif /* !CONFIG_TRUSTED_EXECUTION_NONSECURE */
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#if defined(CONFIG_INIT_PLL0) || defined(CONFIG_INIT_PLL1)
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/* Configure XTAL32M */
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ExternalClockFrequency = 16000000U;
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CLOCK_SetupExtClocking(ExternalClockFrequency);
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#endif
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
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#if defined(CONFIG_SOC_LPC55S06) || !defined(CONFIG_INIT_PLL1)
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/* Enable FRO HF(SystemCoreClock) output (Default expected value 96MHz) */
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CLOCK_SetupFROClocking(SystemCoreClock);
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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/* Switch MAIN_CLK to FRO_HF */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
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#else
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/* Switch PLL1 clock source selector to XTAL32M */
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CLOCK_AttachClk(kEXT_CLK_to_PLL1);
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/* Ensure PLL1 is on */
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POWER_DisablePD(kPDRUNCFG_PD_PLL1);
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/* Configure PLL to the desired values */
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CLOCK_SetPLL1Freq(&pll1Setup);
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/* Switch MAIN_CLK to FRO_HF */
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CLOCK_AttachClk(kPLL1_to_MAIN_CLK);
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#endif /* CONFIG_SOC_LPC55S06 || !CONFIG_INIT_PLL1 */
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#ifdef CONFIG_INIT_PLL0
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/* Switch PLL0 clock source selector to XTAL32M */
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CLOCK_AttachClk(kEXT_CLK_to_PLL0);
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/* Configure PLL to the desired values */
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CLOCK_SetPLL0Freq(&pll0Setup);
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#if defined(CONFIG_SOC_LPC55S36)
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CLOCK_SetClkDiv(kCLOCK_DivPllClk, 0U, true);
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CLOCK_SetClkDiv(kCLOCK_DivPllClk, 1U, false);
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#else
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CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);
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CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 1U, false);
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#endif /* CONFIG_SOC_LPC55S36 */
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#endif /* CONFIG_INIT_PLL0 */
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/* Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
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/* Enables the clock for the I/O controller.: Enable Clock. */
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CLOCK_EnableClock(kCLOCK_Iocon);
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CLOCK_EnableClock(kCLOCK_Iocon);
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_usart, okay)
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#if defined(CONFIG_SOC_LPC55S36)
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@ -250,11 +311,11 @@ DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
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#if defined(CONFIG_SOC_LPC55S36) && defined(CONFIG_PWM)
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/* Set the Submodule Clocks for FlexPWM */
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SYSCON->PWM0SUBCTL |=
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(SYSCON_PWM0SUBCTL_CLK0_EN_MASK | SYSCON_PWM0SUBCTL_CLK1_EN_MASK |
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SYSCON_PWM0SUBCTL_CLK2_EN_MASK);
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(SYSCON_PWM0SUBCTL_CLK0_EN_MASK | SYSCON_PWM0SUBCTL_CLK1_EN_MASK |
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SYSCON_PWM0SUBCTL_CLK2_EN_MASK);
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SYSCON->PWM1SUBCTL |=
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(SYSCON_PWM1SUBCTL_CLK0_EN_MASK | SYSCON_PWM1SUBCTL_CLK1_EN_MASK |
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SYSCON_PWM1SUBCTL_CLK2_EN_MASK);
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(SYSCON_PWM1SUBCTL_CLK0_EN_MASK | SYSCON_PWM1SUBCTL_CLK1_EN_MASK |
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SYSCON_PWM1SUBCTL_CLK2_EN_MASK);
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(adc0), nxp_lpc_lpadc, okay)
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* SystemInit unconditionally enables the trace clock.
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* Disable the trace clock unless SWO is used
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*/
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SYSCON->TRACECLKDIV = 0x4000000;
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SYSCON->TRACECLKDIV = 0x4000000;
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#endif
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}
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