board: add cy8ckit 062 pioneer

Tested with hello_world and blinky projects
Signed-off-by: David Ullmann <davidl.ullmann@gmail.com>

CODEOWNERS

@@ -111,6 +111,7 @@
 /boards/arm/cc26x2r1_launchxl/            @bwitherspoon
 /boards/arm/cc3220sf_launchxl/            @vanti
 /boards/arm/cy8ckit_062_ble/              @ifyall @npal-cy
+/boards/arm/cy8ckit_062s4/                @DaWei8823
 /boards/arm/cy8ckit_062_wifi_bt/          @ifyall @npal-cy
 /boards/arm/cy8cproto_062_4343w/          @ifyall @npal-cy
 /boards/arm/disco_l475_iot1/              @erwango

boards/arm/cy8ckit_062s4/Kconfig.board

@@ -0,0 +1,6 @@
+# Copyright (c) 2023 David Ullmann
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_CY8CKIT_062S4_M4
+	bool "PSoC 62S4 pioneer kit"
+	depends on SOC_CY8C6244LQI_S4D92

boards/arm/cy8ckit_062s4/Kconfig.defconfig

@@ -0,0 +1,10 @@
+# Copyright (c) 2023 David Ullmann
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_CY8CKIT_062S4_M4
+
+config BOARD
+	default "cy8ckit_062s4_m4" if BOARD_CY8CKIT_062S4_M4
+
+
+endif #BOARD_CY8CKIT_062S4_M4

boards/arm/cy8ckit_062s4/board.cmake

@@ -0,0 +1,5 @@
+# Copyright (c) 2023 David Ullmann
+# spdx-license-identifier: apache-2.0
+
+board_runner_args(pyocd "--target=cy8c6xxa")
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.dts

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 David Ullmann
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <infineon/psoc6/mpns/CY8C6244LQI_S4D92.dtsi>
+
+/ {
+	model = "Infineon PSoC 62S4 Pioneer Kit";
+	compatible ="cypress,psoc6";
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart2;
+		zephyr,shell-uart = &uart2;
+	};
+
+	aliases {
+		led0 = &user_led;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		user_led: led_0 {
+			label = "LED_0";
+			gpios = <&gpio_prt2 5 GPIO_ACTIVE_HIGH>;
+		};
+
+	};
+
+};
+
+&p3_1_scb2_uart_tx {
+	drive-push-pull;
+};
+
+&p3_0_scb2_uart_rx {
+	input-enable;
+};
+
+
+uart2: &scb2 {
+	compatible = "infineon,cat1-uart";
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&p3_0_scb2_uart_rx &p3_1_scb2_uart_tx>;
+	pinctrl-names = "default";
+};
+
+&gpio_prt3 {
+	status = "okay";
+};
+
+&gpio_prt2 {
+	status = "okay";
+};

boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.yaml

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2023 David Ullmann
+
+identifier: cy8ckit_062s4_m4
+name: CY8CKIT-062S4 PSoC 62S4
+type: mcu
+arch: arm
+ram: 128
+flash: 256
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio

boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4_defconfig

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2023 David Ullmann
+
+CONFIG_SOC_SERIES_PSOC_62=y
+CONFIG_BOARD_CY8CKIT_062S4_M4=y
+CONFIG_SOC_CY8C6244LQI_S4D92=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+
+CONFIG_PINCTRL=y
+CONFIG_SOC_PSOC6_CM0P_IMAGE_SLEEP=y
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_XIP=y

boards/arm/cy8ckit_062s4/doc/index.rst

@@ -0,0 +1,115 @@
+.. _cy8ckit_062s4:
+
+[INFINEON PSoC 62S4 Pioneer Kit]
+################################
+
+Overview
+********
+The PSOC 62S$ Pioneer kit has a CY8C62x4 MCU, which is an ultra-low-power PSoC device specifically designed for battery-operated analog
+sensing applications. It includes a 150-MHz Arm® Cortex®-M4 CPU as the primary application processor, a 100-MHz Arm® Cortex®-M0+ CPU that
+supports low-power operations, up to 256 KB Flash and 128 KB SRAM, programmable analog sensing,
+CapSense™ touch-sensing, and programmable digital peripherals.
+
+The board features an onboard
+programmer/debugger (KitProg3), a 512-Mbit Quad SPI NOR flash, a micro-B connector for USB device
+interface, a thermistor, an ambient light sensor, a 5-segment CapSense™ slider, two CapSense™ buttons, two
+user LEDs, and a push button. The board supports operating voltages from 1.8 V to 3.3 V for PSoC™ 6 MCU.
+
+.. figure::img/cy8ckit_062s4.png
+   :width: 800px
+   :align: center
+   :alt: Board Name
+
+   Board Name (Credit: <owner>)
+
+Hardware
+********
+
+`CY8CKIT 062S4 Pioneer Kit Website`_
+`CY8CKIT 062S4 Pioneer Kit Guide`_
+`CY8CKIT 062S4 Pioneer Kit Schematic`_
+`CY8CKIT 062S4 Pioneer Kit Technical Reference Manual`_
+`CY8CKIT 062S4 Pioneer Kit Datasheet`_
+
+Supported Features
+==================
+
+The board configuration supports the following hardware features:
+
++-----------+------------+-----------------------+
+| Interface | Controller | Driver/Component      |
++===========+============+=======================+
+| NVIC      | on-chip    | nested vectored       |
+|           |            | interrupt controller  |
++-----------+------------+-----------------------+
+| SYSTICK   | on-chip    | system clock          |
++-----------+------------+-----------------------+
+| PINCTRL   | on-chip    | pin control           |
++-----------+------------+-----------------------+
+| UART      | on-chip    | serial port-polling;  |
++-----------+------------+-----------------------+
+
+The default configuration can be found in the Kconfig
+:zephyr_file:`boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4_defconfig`.
+
+Clock Configuration
+===================
+
++-----------+------------+-----------------------+
+| Clock     | Source     | Output Frequency      |
++===========+============+=======================+
+| FLL       | IMO        | 100.0 MHz             |
++-----------+------------+-----------------------+
+| PLL       | IMO        | 48.0 MHz              |
++-----------+------------+-----------------------+
+| CLK_HF0   | CLK_PATH0  | 100.0 MHz             |
++-----------+------------+-----------------------+
+
+Fetch Binary Blobs
+==================
+
+.. code-block:: console
+
+   west blobs fetch hal_infineon
+
+
+Build and flash hello world sample
+**********************************
+
+
+.. code-block:: console
+
+   cd zephyr/samples/hello_world
+   west build -p auto -b cy8ckit_062s4_m4 --pristine
+   west flash
+   picocom /dev/ttyACM0 -b 115200
+
+OpenOCD Installation
+====================
+
+To get the OpenOCD package, it is required that you
+
+1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox
+2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox
+   export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts
+3. Add the OpenOCD executable file's path to west flash/debug.
+4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd
+5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd
+
+References
+**********
+
+.. _CY8CKIT 062S4 Pioneer Kit Guide:
+    https://www.infineon.com/dgdl/Infineon-CY8CKIT_062S4_PSoC62S4_pioneer_kit_guide-UserManual-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017e962f98992207
+
+.. _CY8CKIT 062S4 Pioneer Kit Website:
+    https://www.infineon.com/cms/en/product/evaluation-boards/cy8ckit-062s4/?redirId=VL1508&utm_medium=referral&utm_source=cypress&utm_campaign=202110_globe_en_all_integration-dev_kit
+
+.. _CY8CKIT 062S4 Pioneer Kit Schematic:
+    https://www.infineon.com/dgdl/Infineon-CY8CKIT-062S4_PSoC_62S4_Pioneer_Kit_Schematic-PCBDesignData-v01_00-EN.pdf?fileId=8ac78c8c7d710014017d7153484d2081
+
+.. _CY8CKIT 062S4 Pioneer Kit Technical Reference Manual:
+    https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C61X4CY8C62X4_REGISTERS_TECHNICAL_REFERENCE_MANUAL_(TRM)_PSOC_61_PSOC_62_MCU-AdditionalTechnicalInformation-v03_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0fb34f0627a7
+
+.. _CY8CKIT 062S4 Pioneer Kit Datasheet:
+   https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_CY8C62X4-DataSheet-v12_00-EN.pdf?fileId=8ac78c8c7ddc01d7017ddd026d585901

dts/arm/infineon/psoc6/mpns/CY8C6244LQI_S4D92.dtsi

@@ -8,7 +8,7 @@
 #include <arm/armv7-m.dtsi>
 #include "../psoc6_04/psoc6_04.68-qfn.dtsi"
 
-/delete-node/ &scb3;
+/delete-node/ &flash1;
 
 &nvic {
 	arm,num-irq-priority-bits = <3>;

soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_04

@@ -0,0 +1,37 @@
+# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+# Copyright (c) David Ullmann
+# SPDX-License-Identifier: Apache-2.0
+
+# Infineon PSoC6_04 based MCU default configuration
+
+if SOC_DIE_PSOC6_04
+
+config NUM_IRQS
+	default 16 if CPU_CORTEX_M0PLUS
+	default 175 if CPU_CORTEX_M4
+
+config SOC
+	default "CY8C6244AZI_S4D92" if SOC_CY8C6244AZI_S4D92
+	default "CY8C6244LQI_S4D92" if SOC_CY8C6244LQI_S4D92
+	default "CY8C6244AZI_S4D93" if SOC_CY8C6244AZI_S4D93
+	default "CY8C6244AZI_S4D82" if SOC_CY8C6244AZI_S4D82
+	default "CY8C6244LQI_S4D82" if SOC_CY8C6244LQI_S4D82
+	default "CY8C6244AZI_S4D83" if SOC_CY8C6244AZI_S4D83
+	default "CY8C6244AZI_S4D62" if SOC_CY8C6244AZI_S4D62
+	default "CY8C6244LQI_S4D62" if SOC_CY8C6244LQI_S4D62
+	default "CY8C6244AZI_S4D12" if SOC_CY8C6244AZI_S4D12
+	default "CY8C6244LQI_S4D12" if SOC_CY8C6244LQI_S4D12
+	default "CY8C6144AZI_S4F92" if SOC_CY8C6144AZI_S4F92
+	default "CY8C6144LQI_S4F92" if SOC_CY8C6144LQI_S4F92
+	default "CY8C6144AZI_S4F93" if SOC_CY8C6144AZI_S4F93
+	default "CY8C6144AZI_S4F82" if SOC_CY8C6144AZI_S4F82
+	default "CY8C6144LQI_S4F82" if SOC_CY8C6144LQI_S4F82
+	default "CY8C6144AZI_S4F83" if SOC_CY8C6144AZI_S4F83
+	default "CY8C6144AZI_S4F62" if SOC_CY8C6144AZI_S4F62
+	default "CY8C6144LQI_S4F62" if SOC_CY8C6144LQI_S4F62
+	default "CY8C6144AZI_S4F12" if SOC_CY8C6144AZI_S4F12
+	default "CY8C6144LQI_S4F12" if SOC_CY8C6144LQI_S4F12
+
+
+endif # SOC_DIE_PSOC6_04

soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_04

@@ -0,0 +1,125 @@
+# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Infineon PSoC6_04 series MCUs
+
+config SOC_CY8C6244AZI_S4D92
+	bool "CY8C6244AZI_S4D92"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	depends on SOC_SERIES_PSOC_62
+
+config SOC_CY8C6244LQI_S4D92
+	bool "CY8C6244LQI_S4D92"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	depends on SOC_SERIES_PSOC_62
+
+config SOC_CY8C6244AZI_S4D93
+	bool "CY8C6244AZI_S4D93"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_TQFP
+	depends on SOC_SERIES_PSOC_62
+
+config SOC_CY8C6244AZI_S4D82
+	bool "CY8C6244AZI_S4D82"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	depends on SOC_SERIES_PSOC_62
+
+config SOC_CY8C6244LQI_S4D82
+	bool "CY8C6244LQI_S4D82"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	depends on SOC_SERIES_PSOC_62
+
+config SOC_CY8C6244AZI_S4D83
+	bool "CY8C6244AZI_S4D83"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_TQFP
+	depends on SOC_SERIES_PSOC_62
+
+config SOC_CY8C6244AZI_S4D62
+	bool "CY8C6244AZI_S4D62"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	depends on SOC_SERIES_PSOC_62
+
+config SOC_CY8C6244LQI_S4D62
+	bool "CY8C6244LQI_S4D62"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	depends on SOC_SERIES_PSOC_62
+
+config SOC_CY8C6244AZI_S4D12
+	bool "CY8C6244AZI_S4D12"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	depends on SOC_SERIES_PSOC_62
+
+config SOC_CY8C6244LQI_S4D12
+	bool "CY8C6244LQI_S4D12"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	depends on SOC_SERIES_PSOC_62
+
+config SOC_CY8C6144AZI_S4F92
+	bool "CY8C6144AZI_S4F92"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	depends on SOC_SERIES_PSOC_61
+
+config SOC_CY8C6144LQI_S4F92
+	bool "CY8C6144LQI_S4F92"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	depends on SOC_SERIES_PSOC_61
+
+config SOC_CY8C6144AZI_S4F93
+	bool "CY8C6144AZI_S4F93"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_TQFP
+	depends on SOC_SERIES_PSOC_61
+
+config SOC_CY8C6144AZI_S4F82
+	bool "CY8C6144AZI_S4F82"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	depends on SOC_SERIES_PSOC_61
+
+config SOC_CY8C6144LQI_S4F82
+	bool "CY8C6144LQI_S4F82"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	depends on SOC_SERIES_PSOC_61
+
+config SOC_CY8C6144AZI_S4F83
+	bool "CY8C6144AZI_S4F83"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_TQFP
+	depends on SOC_SERIES_PSOC_61
+
+config SOC_CY8C6144AZI_S4F62
+	bool "CY8C6144AZI_S4F62"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	depends on SOC_SERIES_PSOC_61
+
+config SOC_CY8C6144LQI_S4F62
+	bool "CY8C6144LQI_S4F62"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	depends on SOC_SERIES_PSOC_61
+
+config SOC_CY8C6144AZI_S4F12
+	bool "CY8C6144AZI_S4F12"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	depends on SOC_SERIES_PSOC_61
+
+config SOC_CY8C6144LQI_S4F12
+	bool "CY8C6144LQI_S4F12"
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	depends on SOC_SERIES_PSOC_61