boards: x86: Add boards and SoCs for Intel ISH

Adds new boards and SoCs for the Intel Sensor Hub (ISH).

Signed-off-by: Dong Wang <dong.d.wang@intel.com>

boards/x86/intel_ish/Kconfig.board

@@ -0,0 +1,16 @@
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_INTEL_ISH_5_4_1
+	bool "Intel ISH 5.4.1 board"
+	depends on SOC_INTEL_ISH_5_4_1
+
+config BOARD_INTEL_ISH_5_6_0
+	bool "Intel ISH 5.6.0 board"
+	depends on SOC_INTEL_ISH_5_6_0
+
+config BOARD_INTEL_ISH_5_8_0
+	bool "Intel ISH 5.8.0 board"
+	depends on SOC_INTEL_ISH_5_8_0

boards/x86/intel_ish/Kconfig.defconfig

@@ -0,0 +1,25 @@
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_INTEL_ISH_5_4_1 || BOARD_INTEL_ISH_5_6_0 || BOARD_INTEL_ISH_5_8_0
+
+config BOARD
+	default "intel_ish_5_4_1" if BOARD_INTEL_ISH_5_4_1
+	default "intel_ish_5_6_0" if BOARD_INTEL_ISH_5_6_0
+	default "intel_ish_5_8_0" if BOARD_INTEL_ISH_5_8_0
+
+if TEST
+config TEST_EXTRA_STACK_SIZE
+	int
+	default 1024
+endif # TEST
+
+config HPET_TIMER
+	default y
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 2048 if HPET_TIMER # HPET is 32768 HZ
+
+endif # BOARD_INTEL_ISH_5_4_1 || BOARD_INTEL_ISH_5_6_0 || BOARD_INTEL_ISH_5_8_0

boards/x86/intel_ish/doc/index.rst

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+.. _intel_ish:
+
+Intel Integrated Sensor Hub (ISH)
+#################################
+
+Overview
+********
+Intel Integrated Sensor Hub (ISH) is a lower-power/always-on co-processor
+inside many Intel Processors. It helps offload sensor processing tasks from
+the core processor for better power saving.
+
+Hardware
+********
+
+- LMT MinuteIA Core, with
+  . 16KB instruction cache and 16KB data cache.
+  . 640KB SRAM space for code and data - implemented as L2 SRAM.
+  . 8KB AON RF space for code resident during deep D0i2/3 PG states.
+- Interface-to-Sensor peripherals (I2C, SPI, UART, I3C, GPIO, DMA).
+- Inter Process Communications (IPC) to core processor and other IP processors.
+
+.. include:: ../../../../soc/x86/intel_ish/doc/supported_features.txt
+
+Programming and Debugging
+*************************
+Use the following procedures for booting an ISH image on a ADL RVP board
+for Chrome.
+
+.. contents::
+   :depth: 1
+   :local:
+   :backlinks: top
+
+Build Zephyr application
+========================
+
+#. Build a Zephyr application; for instance, to build the ``hello_world``
+   application for ISH 5.4.1 on Intel ADL Processor:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: intel_ish_5_4_1
+      :goals: build
+
+   .. note::
+
+      A Zephyr image file named :file:`ish_fw.bin` is automatically
+      created in the build directory after the application is built.
+
+Run ish_fw.bin on ADL RVP board for Chrome
+==========================================
+
+# Power on the ADL RVP board.
+
+# Log in Chrome OS. (Note: the user must have root access right.)
+
+# Re-mount the root filesystem as read-write:
+
+   .. code-block:: console
+
+   $ mount -o remount,rw /
+
+  If re-mount fails, execute below commands to Remove rootfs verification:
+
+   .. code-block:: console
+
+   $ /usr/share/vboot/bin/make_dev_ssd.sh --remove_rootfs_verification --partitions
+   $ reboot
+
+# Go to the ISH firmware direcoty:
+
+   .. code-block:: console
+
+   $ cd /lib/firmware/intel
+
+  Relace the file adlrvp_ish.bin with zephyr image built out, ish_fw.bin.
+
+# Reboot, then observe zephyr log output via ISH UART0.

boards/x86/intel_ish/intel_ish_5_4_1.dts

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "intel/intel_ish5.dtsi"
+
+/ {
+	model = "intel_ish_5_4_1";
+	compatible = "intel,ish_5_4_1";
+
+	chosen {
+		zephyr,sram = &sram;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+};

boards/x86/intel_ish/intel_ish_5_4_1.yaml

@@ -0,0 +1,13 @@
+identifier: intel_ish_5_4_1
+name: Intel ISH 5.4.1 SoC
+type: mcu
+arch: x86
+toolchain:
+  - zephyr
+ram: 640
+supported:
+  - serial
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/x86/intel_ish/intel_ish_5_4_1_defconfig

@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_FAMILY_INTEL_ISH=y
+CONFIG_SOC_SERIES_INTEL_ISH5=y
+CONFIG_SOC_INTEL_ISH_5_4_1=y
+CONFIG_BOARD_INTEL_ISH_5_4_1=y
+
+# uart & console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y

boards/x86/intel_ish/intel_ish_5_6_0.dts

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "intel/intel_ish5.dtsi"
+
+/ {
+	model = "intel_ish_5_6_0";
+	compatible = "intel,ish_5_6_0";
+
+	chosen {
+		zephyr,sram = &sram;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+};

boards/x86/intel_ish/intel_ish_5_6_0.yaml

@@ -0,0 +1,13 @@
+identifier: intel_ish_5_6_0
+name: Intel ISH 5.6.0 SoC
+type: mcu
+arch: x86
+toolchain:
+  - zephyr
+ram: 640
+supported:
+  - serial
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/x86/intel_ish/intel_ish_5_6_0_defconfig

@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_FAMILY_INTEL_ISH=y
+CONFIG_SOC_SERIES_INTEL_ISH5=y
+CONFIG_SOC_INTEL_ISH_5_6_0=y
+CONFIG_BOARD_INTEL_ISH_5_6_0=y
+
+# uart & console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y

boards/x86/intel_ish/intel_ish_5_8_0.dts

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "intel/intel_ish5_8.dtsi"
+
+/ {
+	model = "intel_ish_5_8_0";
+	compatible = "intel,ish_5_8_0";
+
+	chosen {
+		zephyr,sram = &sram;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+};

boards/x86/intel_ish/intel_ish_5_8_0.yaml

@@ -0,0 +1,13 @@
+identifier: intel_ish_5_8_0
+name: Intel ISH 5.8.0 SoC
+type: mcu
+arch: x86
+toolchain:
+  - zephyr
+ram: 640
+supported:
+  - serial
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/x86/intel_ish/intel_ish_5_8_0_defconfig

@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_FAMILY_INTEL_ISH=y
+CONFIG_SOC_SERIES_INTEL_ISH5=y
+CONFIG_SOC_INTEL_ISH_5_8_0=y
+CONFIG_BOARD_INTEL_ISH_5_8_0=y
+
+# uart & console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y

dts/bindings/cpu/intel,ish.yaml

@@ -0,0 +1,9 @@
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: INTEL ISH CPU
+
+compatible: "intel,ish"
+
+include: cpu.yaml

dts/x86/intel/intel_ish5.dtsi

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <mem.h>
+
+/ {
+	chosen {
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu0@0 {
+			device_type = "cpu";
+			compatible = "intel,ish";
+			reg = <0>;
+		};
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		reg = <0xfec00000 0x100000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
+	sram: memory@ff200000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0xff200000 DT_SIZE_K(640)>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		hpet: hpet@4700000{
+			compatible = "intel,hpet";
+			reg = <0x04700000 0x400>;
+			interrupt-parent = <&intc>;
+			interrupts = <14 IRQ_TYPE_FIXED_LEVEL_HIGH 2>;
+			status = "okay";
+		};
+
+		uart0: uart@8100000 {
+			compatible = "intel,sedi-uart";
+			reg = <0x08100000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <23 IRQ_TYPE_LOWEST_EDGE_RISING 6>;
+			current-speed = <115200>;
+			status = "okay";
+		};
+	};
+};

dts/x86/intel/intel_ish5_8.dtsi

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <intel/intel_ish5.dtsi>
+
+&hpet {
+	interrupts = <17 IRQ_TYPE_FIXED_LEVEL_HIGH 2>;
+
+	status = "okay";
+};
+
+&uart0 {
+	interrupts = <28 IRQ_TYPE_LOWEST_EDGE_RISING 6>;
+
+	status = "okay";
+};

soc/x86/intel_ish/CMakeLists.txt

@@ -0,0 +1,7 @@
+# Intel ISH SoC family
+#
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})

soc/x86/intel_ish/Kconfig

@@ -0,0 +1,13 @@
+# Intel ISH family configuration options
+#
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_INTEL_ISH
+	bool "Intel ISH SoC family"
+	select X86
+	select X86_NO_SPECULATIVE_VULNERABILITIES
+	select IOAPIC
+	select LOAPIC
+	select CPU_HAS_FPU

soc/x86/intel_ish/Kconfig.defconfig

@@ -0,0 +1,30 @@
+# Intel ISH family default configuration options
+#
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_INTEL_ISH
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 32768 if HPET_TIMER
+
+config SOC_FAMILY
+	string
+	default "intel_ish"
+
+config X86_VERY_EARLY_CONSOLE
+	default n
+
+config SRAM_OFFSET
+	hex
+	default 0x0
+
+# Target platforms are not PC-compatible
+# (e.g. without BIOS, ACPI, CMOS, etc.).
+config X86_PC_COMPATIBLE
+	default n
+
+endif # SOC_FAMILY_INTEL_ISH
+
+rsource "*/Kconfig.defconfig.series"

soc/x86/intel_ish/Kconfig.soc

@@ -0,0 +1,8 @@
+# Intel ISH family selection
+#
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+rsource "*/Kconfig.series"
+rsource "*/Kconfig.soc"

soc/x86/intel_ish/doc/supported_features.txt

@@ -0,0 +1,7 @@
+Supported Features
+==================
+
+In addition to the standard architecture devices (HPET, local and I/O APICs,
+etc.), Zephyr supports the following ISH-specific SoC devices:
+
+* HSUART

soc/x86/intel_ish/intel_ish5/CMakeLists.txt

@@ -0,0 +1,10 @@
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_cc_option(-march=pentium -mtune=i486)
+
+zephyr_sources(soc.c)
+
+include(../utils/build_ish_firmware.cmake)

soc/x86/intel_ish/intel_ish5/Kconfig.defconfig.series

@@ -0,0 +1,18 @@
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_INTEL_ISH5
+
+config SOC_SERIES
+	string
+	default "intel_ish5"
+
+config SOC
+	string
+	default "intel_ish_5_4_1" if SOC_INTEL_ISH_5_4_1
+	default "intel_ish_5_6_0" if SOC_INTEL_ISH_5_6_0
+	default "intel_ish_5_8_0" if SOC_INTEL_ISH_5_8_0
+
+endif # SOC_SERIES_INTEL_ISH5

soc/x86/intel_ish/intel_ish5/Kconfig.series

@@ -0,0 +1,8 @@
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_INTEL_ISH5
+	bool "Intel ISH5 SoC"
+	select SOC_FAMILY_INTEL_ISH

soc/x86/intel_ish/intel_ish5/Kconfig.soc

@@ -0,0 +1,19 @@
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+	prompt "Intel ISH5 SoCs"
+	depends on SOC_SERIES_INTEL_ISH5
+
+config SOC_INTEL_ISH_5_4_1
+	bool "Intel ISH 5.4.1 SoC"
+
+config SOC_INTEL_ISH_5_6_0
+	bool "Intel ISH 5.6.0 SoC"
+
+config SOC_INTEL_ISH_5_8_0
+	bool "Intel ISH 5.8.0 SoC"
+
+endchoice

soc/x86/intel_ish/intel_ish5/linker.ld

@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/x86/memory.ld>
+#include <zephyr/arch/x86/ia32/linker.ld>

soc/x86/intel_ish/intel_ish5/soc.c

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/init.h>
+#include "soc.h"
+
+#if defined(CONFIG_HPET_TIMER)
+#include "sedi_driver_hpet.h"
+#endif
+
+static int intel_ish_init(void)
+{
+#if defined(CONFIG_HPET_TIMER)
+	sedi_hpet_set_min_delay(HPET_CMP_MIN_DELAY);
+#endif
+
+	return 0;
+}
+
+SYS_INIT(intel_ish_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/x86/intel_ish/intel_ish5/soc.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2023, Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __SOC_H_
+#define __SOC_H_
+
+#include <zephyr/sys/util.h>
+
+#ifndef _ASMLANGUAGE
+#include <zephyr/device.h>
+#include <zephyr/random/rand32.h>
+
+#ifdef CONFIG_HPET_TIMER
+#include "sedi_driver_hpet.h"
+
+#define HPET_USE_CUSTOM_REG_ACCESS_FUNCS
+
+/* COUNTER_CLK_PERIOD (CLK_PERIOD_REG) is in picoseconds (1e-12 sec) */
+#define HPET_COUNTER_CLK_PERIOD		(1000000000000ULL)
+
+#define HPET_CMP_MIN_DELAY		(5)
+
+__pinned_func
+static inline void hpet_timer_comparator_set(uint64_t next)
+{
+	sedi_hpet_set_comparator(HPET_0, next);
+}
+
+#endif  /*CONFIG_HPET_TIMER */
+
+#endif  /* !_ASMLANGUAGE */
+
+/* ISH specific DMA channel direction */
+#define IMR_TO_MEMORY (DMA_CHANNEL_DIRECTION_PRIV_START)
+#define MEMORY_TO_IMR (DMA_CHANNEL_DIRECTION_PRIV_START + 1)
+
+#endif /* __SOC_H_ */

soc/x86/intel_ish/utils/build_ish_firmware.cmake

@@ -0,0 +1,10 @@
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+  COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_LIST_DIR}/build_ish_firmware.py
+  ARGS -k ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin
+  -o ${PROJECT_BINARY_DIR}/ish_fw.bin
+)

soc/x86/intel_ish/utils/build_ish_firmware.py

@@ -0,0 +1,102 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-"
+
+# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+"""Script to pack EC binary with manifest header.
+
+Package ecos main FW binary (kernel) and AON task binary into final EC binary
+image with a manifest header, ISH shim loader will parse this header and load
+each binaries into right memory location.
+"""
+
+import argparse
+import struct
+import os
+
+MANIFEST_ENTRY_SIZE = 0x80
+HEADER_SIZE = 0x1000
+PAGE_SIZE = 0x1000
+
+def parseargs():
+    parser = argparse.ArgumentParser(allow_abbrev=False)
+    parser.add_argument("-k", "--kernel",
+                        help="EC kernel binary to pack, \
+                        usually ec.RW.bin or ec.RW.flat.",
+                        required=True)
+    parser.add_argument("-a", "--aon",
+                        help="EC aontask binary to pack, \
+                        usually ish_aontask.bin.",
+                        required=False)
+    parser.add_argument("-o", "--output",
+                        help="Output flash binary file")
+
+    return parser.parse_args()
+
+def gen_manifest(ext_id, comp_app_name, code_offset, module_size):
+    """Returns a binary blob that represents a manifest entry"""
+    m = bytearray(MANIFEST_ENTRY_SIZE)
+
+    # 4 bytes of ASCII encode ID (little endian)
+    struct.pack_into('<4s', m, 0, ext_id)
+    # 8 bytes of ASCII encode ID (little endian)
+    struct.pack_into('<8s', m, 32, comp_app_name)
+    # 4 bytes of code offset (little endian)
+    struct.pack_into('<I', m, 96, code_offset)
+    # 2 bytes of module in page size increments (little endian)
+    struct.pack_into('<H', m, 100, module_size)
+
+    return m
+
+def roundup_page(size):
+    """Returns roundup-ed page size from size of bytes"""
+    return int(size / PAGE_SIZE) + (size % PAGE_SIZE > 0)
+
+def main():
+    args = parseargs()
+    print("    Packing EC image file for ISH")
+
+    with open(args.output, 'wb') as f:
+        kernel_size = os.path.getsize(args.kernel)
+
+        if args.aon is not None:
+            aon_size = os.path.getsize(args.aon)
+
+        print("      kernel binary size:", kernel_size)
+        kern_rdup_pg_size = roundup_page(kernel_size)
+        # Add manifest for main ISH binary
+        f.write(gen_manifest(b'ISHM', b'ISH_KERN', HEADER_SIZE, kern_rdup_pg_size))
+
+        if args.aon is not None:
+            print("      AON binary size:   ", aon_size)
+            aon_rdup_pg_size = roundup_page(aon_size)
+            # Add manifest for aontask binary
+            f.write(gen_manifest(b'ISHM', b'AON_TASK',
+                                 (HEADER_SIZE + kern_rdup_pg_size * PAGE_SIZE -
+                                  MANIFEST_ENTRY_SIZE), aon_rdup_pg_size))
+
+        # Add manifest that signals end of manifests
+        f.write(gen_manifest(b'ISHE', b'', 0, 0))
+
+        # Pad the remaining HEADER with 0s
+        if args.aon is not None:
+            f.write(b'\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 3)))
+        else:
+            f.write(b'\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 2)))
+
+        # Append original kernel image
+        with open(args.kernel, 'rb') as in_file:
+            f.write(in_file.read())
+            # Filling padings due to size round up as pages
+            f.write(b'\x00' * (kern_rdup_pg_size * PAGE_SIZE - kernel_size))
+
+            if args.aon is not None:
+                # Append original aon image
+                with open(args.aon, 'rb') as in_file:
+                    f.write(in_file.read())
+                # Filling padings due to size round up as pages
+                f.write(b'\x00' * (aon_rdup_pg_size * PAGE_SIZE - aon_size))
+
+if __name__ == '__main__':
+    main()