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boards: mr_canhubk3: enable LPUART serial driver

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Reuse existing MCUX-based shim driver for LPUART that is compatible with
the hardware block in S32K344. DMA is not yet supported.

Use the board's debug connector (P6 / LPUART2) as default console.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Arguelles 2023-05-26 00:00:00 +00:00 • committed by Mahesh Mahadevan
commit 405160ca62
7 changed files with 259 additions and 1 deletions
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7
boards/arm/mr_canhubk3/Kconfig.defconfig
View file

@ -6,4 +6,11 @@ if BOARD_MR_CANHUBK3
config BOARD
default "mr_canhubk3"
if SERIAL
config UART_CONSOLE
default y
endif # SERIAL
endif # BOARD_MR_CANHUBK3

78
boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi
View file

@ -7,11 +7,87 @@
#include <nxp/s32/S32K344-172MQFP-pinctrl.h>
&pinctrl {
eirq0_default: eirq0_default {
group1 {
pinmux = <PTD15_EIRQ31>;
input-enable;
};
};
lpuart0_default: lpuart0_default {
group1 {
pinmux = <PTA3_LPUART0_TX_O>, <PTA1_LPUART0_RTS>;
output-enable;
};
group2 {
pinmux = <PTA2_LPUART0_RX>, <PTA0_LPUART0_CTS>;
input-enable;
};
};
lpuart1_default: lpuart1_default {
group1 {
pinmux = <PTC7_LPUART1_TX_O>, <PTE6_LPUART1_RTS>;
output-enable;
};
group2 {
pinmux = <PTC6_LPUART1_RX>, <PTE2_LPUART1_CTS>;
input-enable;
};
};
lpuart2_default: lpuart2_default {
group1 {
pinmux = <PTA9_LPUART2_TX_O>;
output-enable;
};
group2 {
pinmux = <PTA8_LPUART2_RX>;
input-enable;
};
};
lpuart9_default: lpuart9_default {
group1 {
pinmux = <PTB3_LPUART9_TX_O>;
output-enable;
};
group2 {
pinmux = <PTB2_LPUART9_RX>;
input-enable;
};
};
lpuart10_default: lpuart10_default {
group1 {
pinmux = <PTC13_LPUART10_TX_O>;
output-enable;
};
group2 {
pinmux = <PTC12_LPUART10_RX>;
input-enable;
};
};
lpuart13_default: lpuart13_default {
group1 {
pinmux = <PTB18_LPUART13_TX_O>;
output-enable;
};
group2 {
pinmux = <PTB19_LPUART13_RX>;
input-enable;
};
};
lpuart14_default: lpuart14_default {
group1 {
pinmux = <PTB20_LPUART14_TX_O>;
output-enable;
};
group2 {
pinmux = <PTB21_LPUART14_RX>;
input-enable;
};
};
};

39
boards/arm/mr_canhubk3/mr_canhubk3.dts
View file

@ -19,6 +19,8 @@
zephyr,itcm = &itcm;
zephyr,dtcm = &dtcm;
zephyr,code-partition = &code_partition;
zephyr,console = &lpuart2;
zephyr,shell-uart = &lpuart2;
};
aliases {
@ -93,3 +95,40 @@
pinctrl-names = "default";
status = "okay";
};
&lpuart0 {
pinctrl-0 = <&lpuart0_default>;
pinctrl-names = "default";
};
&lpuart1 {
pinctrl-0 = <&lpuart1_default>;
pinctrl-names = "default";
};
&lpuart2 {
pinctrl-0 = <&lpuart2_default>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&lpuart9 {
pinctrl-0 = <&lpuart9_default>;
pinctrl-names = "default";
};
&lpuart10 {
pinctrl-0 = <&lpuart10_default>;
pinctrl-names = "default";
};
&lpuart13 {
pinctrl-0 = <&lpuart13_default>;
pinctrl-names = "default";
};
&lpuart14 {
pinctrl-0 = <&lpuart14_default>;
pinctrl-names = "default";
};

1
boards/arm/mr_canhubk3/mr_canhubk3.yaml
View file

@ -11,3 +11,4 @@ toolchain:
- zephyr
supported:
- gpio
- uart

4
boards/arm/mr_canhubk3/mr_canhubk3_defconfig
View file

@ -20,3 +20,7 @@ CONFIG_NOCACHE_MEMORY=y
# Drivers
CONFIG_PINCTRL=y
CONFIG_SERIAL=y
# Serial console
CONFIG_CONSOLE=y

129
dts/arm/nxp/nxp_s32k344_m7.dtsi
View file

@ -6,6 +6,7 @@
#include <arm/armv7-m.dtsi>
#include <mem.h>
#include <zephyr/dt-bindings/clock/nxp_s32k344_clock.h>
/ {
cpus {
@ -286,6 +287,134 @@
status = "disabled";
};
};
lpuart0: uart@40328000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40328000 0x4000>;
interrupts = <141 0>;
clocks = <&clock NXP_S32_LPUART0_CLK>;
status = "disabled";
};
lpuart1: uart@4032c000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x4032c000 0x4000>;
interrupts = <142 0>;
clocks = <&clock NXP_S32_LPUART1_CLK>;
status = "disabled";
};
lpuart2: uart@40330000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40330000 0x4000>;
interrupts = <143 0>;
clocks = <&clock NXP_S32_LPUART2_CLK>;
status = "disabled";
};
lpuart3: uart@40334000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40334000 0x4000>;
interrupts = <144 0>;
clocks = <&clock NXP_S32_LPUART3_CLK>;
status = "disabled";
};
lpuart4: uart@40338000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40338000 0x4000>;
interrupts = <145 0>;
clocks = <&clock NXP_S32_LPUART4_CLK>;
status = "disabled";
};
lpuart5: uart@4033c000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x4033c000 0x4000>;
interrupts = <146 0>;
clocks = <&clock NXP_S32_LPUART5_CLK>;
status = "disabled";
};
lpuart6: uart@40340000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40340000 0x4000>;
interrupts = <147 0>;
clocks = <&clock NXP_S32_LPUART6_CLK>;
status = "disabled";
};
lpuart7: uart@40344000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40344000 0x4000>;
interrupts = <148 0>;
clocks = <&clock NXP_S32_LPUART7_CLK>;
status = "disabled";
};
lpuart8: uart@4048c000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x4048c000 0x4000>;
interrupts = <149 0>;
clocks = <&clock NXP_S32_LPUART8_CLK>;
status = "disabled";
};
lpuart9: uart@40490000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40490000 0x4000>;
interrupts = <150 0>;
clocks = <&clock NXP_S32_LPUART9_CLK>;
status = "disabled";
};
lpuart10: uart@40494000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40494000 0x4000>;
interrupts = <151 0>;
clocks = <&clock NXP_S32_LPUART10_CLK>;
status = "disabled";
};
lpuart11: uart@40498000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40498000 0x4000>;
interrupts = <152 0>;
clocks = <&clock NXP_S32_LPUART11_CLK>;
status = "disabled";
};
lpuart12: uart@4049c000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x4049c000 0x4000>;
interrupts = <153 0>;
clocks = <&clock NXP_S32_LPUART12_CLK>;
status = "disabled";
};
lpuart13: uart@404a0000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x404a0000 0x4000>;
interrupts = <154 0>;
clocks = <&clock NXP_S32_LPUART13_CLK>;
status = "disabled";
};
lpuart14: uart@404a4000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x404a4000 0x4000>;
interrupts = <155 0>;
clocks = <&clock NXP_S32_LPUART14_CLK>;
status = "disabled";
};
lpuart15: uart@404a8000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x404a8000 0x4000>;
interrupts = <156 0>;
clocks = <&clock NXP_S32_LPUART15_CLK>;
status = "disabled";
};
};
};

2
soc/arm/nxp_s32/s32k/Kconfig.series
View file

@ -14,5 +14,7 @@ config SOC_SERIES_S32K3_M7
select PLATFORM_SPECIFIC_INIT if XIP
select USE_DT_CODE_PARTITION if XIP
select CLOCK_CONTROL
select HAS_MCUX
select HAS_MCUX_LPUART
help
Enable support for NXP S32K3 MCUs family on Cortex-M7 cores