nxp_s32: enable clock control for S32ZE
Enable clock control driver for NXP S32ZE SoCs and add clock sources definitions for devicetree. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles
Fabio Baltieri
parent
0e765a9ef8
commit
7fca0aa8a6
5 changed files with 318 additions and 19 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright 2022 NXP
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -80,6 +80,25 @@
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soc {
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interrupt-parent = <&gic>;
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clock: clock-controller@40030000 {
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compatible = "nxp,s32-clock";
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reg = <0x40030000 0x10000>,
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<0x40200000 0x10000>,
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<0x40210000 0x10000>,
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<0x40220000 0x10000>,
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<0x40260000 0x10000>,
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<0x40270000 0x10000>,
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<0x40830000 0x10000>,
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<0x41030000 0x10000>,
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<0x41830000 0x10000>,
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<0x42030000 0x10000>,
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<0x42830000 0x10000>,
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<0x44030000 0x10000>,
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<0x440a0000 0x10000>;
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#clock-cells = <1>;
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status = "okay";
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};
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gic: interrupt-controller@47800000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x47800000 0x10000>,
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297
include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h
Normal file
297
include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h
Normal file
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@ -0,0 +1,297 @@
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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_
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#define NXP_S32_FIRC_CLK 1U
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#define NXP_S32_FXOSC_CLK 2U
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#define NXP_S32_SIRC_CLK 3U
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#define NXP_S32_COREPLL_CLK 4U
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#define NXP_S32_PERIPHPLL_CLK 5U
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#define NXP_S32_DDRPLL_CLK 6U
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#define NXP_S32_LFAST0_PLL_CLK 7U
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#define NXP_S32_LFAST1_PLL_CLK 8U
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#define NXP_S32_COREPLL_PHI0_CLK 9U
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#define NXP_S32_COREPLL_DFS0_CLK 10U
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#define NXP_S32_COREPLL_DFS1_CLK 11U
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#define NXP_S32_COREPLL_DFS2_CLK 12U
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#define NXP_S32_COREPLL_DFS3_CLK 13U
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#define NXP_S32_COREPLL_DFS4_CLK 14U
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#define NXP_S32_COREPLL_DFS5_CLK 15U
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#define NXP_S32_PERIPHPLL_PHI0_CLK 16U
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#define NXP_S32_PERIPHPLL_PHI1_CLK 17U
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#define NXP_S32_PERIPHPLL_PHI2_CLK 18U
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#define NXP_S32_PERIPHPLL_PHI3_CLK 19U
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#define NXP_S32_PERIPHPLL_PHI4_CLK 20U
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#define NXP_S32_PERIPHPLL_PHI5_CLK 21U
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#define NXP_S32_PERIPHPLL_PHI6_CLK 22U
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#define NXP_S32_PERIPHPLL_DFS0_CLK 23U
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#define NXP_S32_PERIPHPLL_DFS1_CLK 24U
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#define NXP_S32_PERIPHPLL_DFS2_CLK 25U
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#define NXP_S32_PERIPHPLL_DFS3_CLK 26U
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#define NXP_S32_PERIPHPLL_DFS4_CLK 27U
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#define NXP_S32_PERIPHPLL_DFS5_CLK 28U
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#define NXP_S32_DDRPLL_PHI0_CLK 29U
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#define NXP_S32_LFAST0_PLL_PH0_CLK 30U
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#define NXP_S32_LFAST1_PLL_PH0_CLK 31U
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#define NXP_S32_ETH_RGMII_REF_CLK 32U
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#define NXP_S32_ETH_EXT_TS_CLK 33U
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#define NXP_S32_ETH0_EXT_RX_CLK 34U
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#define NXP_S32_ETH0_EXT_TX_CLK 35U
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#define NXP_S32_ETH1_EXT_RX_CLK 36U
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#define NXP_S32_ETH1_EXT_TX_CLK 37U
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#define NXP_S32_LFAST0_EXT_REF_CLK 38U
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#define NXP_S32_LFAST1_EXT_REF_CLK 39U
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#define NXP_S32_DDR_CLK 40U
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#define NXP_S32_P0_SYS_CLK 41U
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#define NXP_S32_P1_SYS_CLK 42U
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#define NXP_S32_P1_SYS_DIV2_CLK 43U
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#define NXP_S32_P1_SYS_DIV4_CLK 44U
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#define NXP_S32_P2_SYS_CLK 45U
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#define NXP_S32_CORE_M33_CLK 46U
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#define NXP_S32_P2_SYS_DIV2_CLK 47U
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#define NXP_S32_P2_SYS_DIV4_CLK 48U
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#define NXP_S32_P3_SYS_CLK 49U
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#define NXP_S32_CE_SYS_DIV2_CLK 50U
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#define NXP_S32_CE_SYS_DIV4_CLK 51U
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#define NXP_S32_P3_SYS_DIV2_NOC_CLK 52U
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#define NXP_S32_P3_SYS_DIV4_CLK 53U
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#define NXP_S32_P4_SYS_CLK 54U
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#define NXP_S32_P4_SYS_DIV2_CLK 55U
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#define NXP_S32_HSE_SYS_DIV2_CLK 56U
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#define NXP_S32_P5_SYS_CLK 57U
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#define NXP_S32_P5_SYS_DIV2_CLK 58U
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#define NXP_S32_P5_SYS_DIV4_CLK 59U
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#define NXP_S32_P2_MATH_CLK 60U
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#define NXP_S32_P2_MATH_DIV3_CLK 61U
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#define NXP_S32_GLB_LBIST_CLK 62U
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#define NXP_S32_RTU0_CORE_CLK 63U
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#define NXP_S32_RTU0_CORE_DIV2_CLK 64U
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#define NXP_S32_RTU1_CORE_CLK 65U
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#define NXP_S32_RTU1_CORE_DIV2_CLK 66U
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#define NXP_S32_P0_PSI5_S_UTIL_CLK 67U
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#define NXP_S32_P4_PSI5_S_UTIL_CLK 68U
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#define NXP_S32_ADC0_CLK 70U
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#define NXP_S32_ADC1_CLK 71U
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#define NXP_S32_CE_EDMA_CLK 72U
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#define NXP_S32_CE_PIT0_CLK 73U
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#define NXP_S32_CE_PIT1_CLK 74U
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#define NXP_S32_CE_PIT2_CLK 75U
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#define NXP_S32_CE_PIT3_CLK 76U
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#define NXP_S32_CE_PIT4_CLK 77U
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#define NXP_S32_CE_PIT5_CLK 78U
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#define NXP_S32_CLKOUT0_CLK 79U
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#define NXP_S32_CLKOUT1_CLK 80U
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#define NXP_S32_CLKOUT2_CLK 81U
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#define NXP_S32_CLKOUT3_CLK 82U
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#define NXP_S32_CLKOUT4_CLK 83U
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#define NXP_S32_CTU_CLK 84U
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#define NXP_S32_DMACRC0_CLK 85U
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#define NXP_S32_DMACRC1_CLK 86U
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#define NXP_S32_DMACRC4_CLK 87U
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#define NXP_S32_DMACRC5_CLK 88U
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#define NXP_S32_DMAMUX0_CLK 89U
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#define NXP_S32_DMAMUX1_CLK 90U
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#define NXP_S32_DMAMUX4_CLK 91U
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#define NXP_S32_DMAMUX5_CLK 92U
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#define NXP_S32_EDMA0_CLK 93U
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#define NXP_S32_EDMA1_CLK 94U
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#define NXP_S32_EDMA3_CLK 95U
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#define NXP_S32_EDMA4_CLK 96U
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#define NXP_S32_EDMA5_CLK 97U
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#define NXP_S32_ETH0_TX_MII_CLK 98U
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#define NXP_S32_ENET0_CLK 99U
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#define NXP_S32_P3_CAN_PE_CLK 100U
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#define NXP_S32_FLEXCAN0_CLK 101U
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#define NXP_S32_FLEXCAN1_CLK 102U
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#define NXP_S32_FLEXCAN2_CLK 103U
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#define NXP_S32_FLEXCAN3_CLK 104U
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#define NXP_S32_FLEXCAN4_CLK 105U
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#define NXP_S32_FLEXCAN5_CLK 106U
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#define NXP_S32_FLEXCAN6_CLK 107U
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#define NXP_S32_FLEXCAN7_CLK 108U
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#define NXP_S32_FLEXCAN8_CLK 109U
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#define NXP_S32_FLEXCAN9_CLK 110U
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#define NXP_S32_FLEXCAN10_CLK 111U
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#define NXP_S32_FLEXCAN11_CLK 112U
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#define NXP_S32_FLEXCAN12_CLK 113U
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#define NXP_S32_FLEXCAN13_CLK 114U
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#define NXP_S32_FLEXCAN14_CLK 115U
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#define NXP_S32_FLEXCAN15_CLK 116U
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#define NXP_S32_FLEXCAN16_CLK 117U
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#define NXP_S32_FLEXCAN17_CLK 118U
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#define NXP_S32_FLEXCAN18_CLK 119U
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#define NXP_S32_FLEXCAN19_CLK 120U
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#define NXP_S32_FLEXCAN20_CLK 121U
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#define NXP_S32_FLEXCAN21_CLK 122U
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#define NXP_S32_FLEXCAN22_CLK 123U
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#define NXP_S32_FLEXCAN23_CLK 124U
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#define NXP_S32_P0_FR_PE_CLK 125U
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#define NXP_S32_FRAY0_CLK 126U
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#define NXP_S32_FRAY1_CLK 127U
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#define NXP_S32_GTM_CLK 128U
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#define NXP_S32_IIIC0_CLK 129U
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#define NXP_S32_IIIC1_CLK 130U
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#define NXP_S32_IIIC2_CLK 131U
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#define NXP_S32_P0_LIN_BAUD_CLK 132U
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#define NXP_S32_LIN0_CLK 133U
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#define NXP_S32_LIN1_CLK 134U
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#define NXP_S32_LIN2_CLK 135U
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#define NXP_S32_P1_LIN_BAUD_CLK 136U
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#define NXP_S32_LIN3_CLK 137U
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#define NXP_S32_LIN4_CLK 138U
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#define NXP_S32_LIN5_CLK 139U
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#define NXP_S32_P4_LIN_BAUD_CLK 140U
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#define NXP_S32_LIN6_CLK 141U
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#define NXP_S32_LIN7_CLK 142U
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#define NXP_S32_LIN8_CLK 143U
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#define NXP_S32_P5_LIN_BAUD_CLK 144U
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#define NXP_S32_LIN9_CLK 145U
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#define NXP_S32_LIN10_CLK 146U
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#define NXP_S32_LIN11_CLK 147U
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#define NXP_S32_MSCDSPI_CLK 148U
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#define NXP_S32_MSCLIN_CLK 149U
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#define NXP_S32_NANO_CLK 150U
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#define NXP_S32_P0_CLKOUT_SRC_CLK 151U
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#define NXP_S32_P0_CTU_PER_CLK 152U
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#define NXP_S32_P0_DSPI_MSC_CLK 153U
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#define NXP_S32_P0_EMIOS_LCU_CLK 154U
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#define NXP_S32_P0_GTM_CLK 155U
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#define NXP_S32_P0_GTM_NOC_CLK 156U
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#define NXP_S32_P0_GTM_TS_CLK 157U
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#define NXP_S32_P0_LIN_CLK 158U
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#define NXP_S32_P0_NANO_CLK 159U
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#define NXP_S32_P0_PSI5_125K_CLK 160U
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#define NXP_S32_P0_PSI5_189K_CLK 161U
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#define NXP_S32_P0_PSI5_S_BAUD_CLK 162U
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#define NXP_S32_P0_PSI5_S_CORE_CLK 163U
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#define NXP_S32_P0_PSI5_S_TRIG0_CLK 164U
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#define NXP_S32_P0_PSI5_S_TRIG1_CLK 165U
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#define NXP_S32_P0_PSI5_S_TRIG2_CLK 166U
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#define NXP_S32_P0_PSI5_S_TRIG3_CLK 167U
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#define NXP_S32_P0_PSI5_S_UART_CLK 168U
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#define NXP_S32_P0_PSI5_S_WDOG0_CLK 169U
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#define NXP_S32_P0_PSI5_S_WDOG1_CLK 170U
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#define NXP_S32_P0_PSI5_S_WDOG2_CLK 171U
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#define NXP_S32_P0_PSI5_S_WDOG3_CLK 172U
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#define NXP_S32_P0_REG_INTF_2X_CLK 173U
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#define NXP_S32_P0_REG_INTF_CLK 174U
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#define NXP_S32_P1_CLKOUT_SRC_CLK 175U
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#define NXP_S32_P1_DSPI60_CLK 176U
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#define NXP_S32_ETH_TS_CLK 177U
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#define NXP_S32_ETH_TS_DIV4_CLK 178U
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#define NXP_S32_ETH0_REF_RMII_CLK 179U
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#define NXP_S32_ETH0_RX_MII_CLK 180U
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#define NXP_S32_ETH0_RX_RGMII_CLK 181U
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#define NXP_S32_ETH0_TX_RGMII_CLK 182U
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#define NXP_S32_ETH0_TX_RGMII_LPBK_CLK 183U
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#define NXP_S32_ETH1_REF_RMII_CLK 184U
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#define NXP_S32_ETH1_RX_MII_CLK 185U
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#define NXP_S32_ETH1_RX_RGMII_CLK 186U
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#define NXP_S32_ETH1_TX_MII_CLK 187U
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#define NXP_S32_ETH1_TX_RGMII_CLK 188U
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#define NXP_S32_ETH1_TX_RGMII_LPBK_CLK 189U
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#define NXP_S32_P1_LFAST0_REF_CLK 190U
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#define NXP_S32_P1_LFAST1_REF_CLK 191U
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#define NXP_S32_P1_LFAST_DFT_CLK 192U
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#define NXP_S32_P1_NETC_AXI_CLK 193U
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#define NXP_S32_P1_LIN_CLK 194U
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#define NXP_S32_P1_REG_INTF_CLK 195U
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#define NXP_S32_P2_DBG_ATB_CLK 196U
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#define NXP_S32_P2_REG_INTF_CLK 197U
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#define NXP_S32_P3_AES_CLK 198U
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#define NXP_S32_P3_CLKOUT_SRC_CLK 199U
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#define NXP_S32_P3_DBG_TS_CLK 200U
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#define NXP_S32_P3_REG_INTF_CLK 201U
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#define NXP_S32_P3_SYS_MON1_CLK 202U
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#define NXP_S32_P3_SYS_MON2_CLK 203U
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#define NXP_S32_P3_SYS_MON3_CLK 204U
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#define NXP_S32_P4_CLKOUT_SRC_CLK 205U
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#define NXP_S32_P4_DSPI60_CLK 206U
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#define NXP_S32_P4_EMIOS_LCU_CLK 207U
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#define NXP_S32_P4_LIN_CLK 208U
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#define NXP_S32_P4_PSI5_125K_CLK 209U
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#define NXP_S32_P4_PSI5_189K_CLK 210U
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#define NXP_S32_P4_PSI5_S_BAUD_CLK 211U
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#define NXP_S32_P4_PSI5_S_CORE_CLK 212U
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#define NXP_S32_P4_PSI5_S_TRIG0_CLK 213U
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#define NXP_S32_P4_PSI5_S_TRIG1_CLK 214U
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#define NXP_S32_P4_PSI5_S_TRIG2_CLK 215U
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#define NXP_S32_P4_PSI5_S_TRIG3_CLK 216U
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#define NXP_S32_P4_PSI5_S_UART_CLK 217U
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#define NXP_S32_P4_PSI5_S_WDOG0_CLK 218U
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#define NXP_S32_P4_PSI5_S_WDOG1_CLK 219U
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#define NXP_S32_P4_PSI5_S_WDOG2_CLK 220U
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#define NXP_S32_P4_PSI5_S_WDOG3_CLK 221U
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#define NXP_S32_P4_QSPI0_2X_CLK 222U
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#define NXP_S32_P4_QSPI0_1X_CLK 223U
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#define NXP_S32_P4_QSPI1_2X_CLK 224U
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#define NXP_S32_P4_QSPI1_1X_CLK 225U
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#define NXP_S32_P4_REG_INTF_2X_CLK 226U
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#define NXP_S32_P4_REG_INTF_CLK 227U
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#define NXP_S32_P4_SDHC_IP_CLK 228U
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#define NXP_S32_P4_SDHC_IP_DIV2_CLK 229U
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#define NXP_S32_P5_DIPORT_CLK 230U
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#define NXP_S32_P5_AE_CLK 231U
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#define NXP_S32_P5_CANXL_PE_CLK 232U
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#define NXP_S32_P5_CANXL_CHI_CLK 233U
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#define NXP_S32_P5_CLKOUT_SRC_CLK 234U
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#define NXP_S32_P5_LIN_CLK 235U
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#define NXP_S32_P5_REG_INTF_CLK 236U
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#define NXP_S32_P6_REG_INTF_CLK 237U
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#define NXP_S32_PIT0_CLK 238U
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#define NXP_S32_PIT1_CLK 239U
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#define NXP_S32_PIT4_CLK 240U
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#define NXP_S32_PIT5_CLK 241U
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#define NXP_S32_P0_PSI5_1US_CLK 242U
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#define NXP_S32_PSI5_0_CLK 243U
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#define NXP_S32_P4_PSI5_1US_CLK 244U
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#define NXP_S32_PSI5_1_CLK 245U
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#define NXP_S32_PSI5S_0_CLK 246U
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#define NXP_S32_PSI5S_1_CLK 247U
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#define NXP_S32_QSPI0_CLK 248U
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#define NXP_S32_QSPI1_CLK 249U
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#define NXP_S32_RTU0_CORE_MON1_CLK 250U
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#define NXP_S32_RTU0_CORE_MON2_CLK 251U
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#define NXP_S32_RTU0_CORE_DIV2_MON1_CLK 252U
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#define NXP_S32_RTU0_CORE_DIV2_MON2_CLK 253U
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#define NXP_S32_RTU0_CORE_DIV2_MON3_CLK 254U
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#define NXP_S32_RTU0_REG_INTF_CLK 255U
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#define NXP_S32_RTU1_CORE_MON1_CLK 256U
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#define NXP_S32_RTU1_CORE_MON2_CLK 257U
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#define NXP_S32_RTU1_CORE_DIV2_MON1_CLK 258U
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#define NXP_S32_RTU1_CORE_DIV2_MON2_CLK 259U
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#define NXP_S32_RTU1_CORE_DIV2_MON3_CLK 260U
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#define NXP_S32_RTU1_REG_INTF_CLK 261U
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#define NXP_S32_P4_SDHC_CLK 262U
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#define NXP_S32_RXLUT_CLK 263U
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#define NXP_S32_SDHC0_CLK 264U
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#define NXP_S32_SINC_CLK 265U
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#define NXP_S32_SIPI0_CLK 266U
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#define NXP_S32_SIPI1_CLK 267U
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#define NXP_S32_SIUL2_0_CLK 268U
|
||||
#define NXP_S32_SIUL2_1_CLK 269U
|
||||
#define NXP_S32_SIUL2_4_CLK 270U
|
||||
#define NXP_S32_SIUL2_5_CLK 271U
|
||||
#define NXP_S32_P0_DSPI_CLK 272U
|
||||
#define NXP_S32_SPI0_CLK 273U
|
||||
#define NXP_S32_SPI1_CLK 274U
|
||||
#define NXP_S32_P1_DSPI_CLK 275U
|
||||
#define NXP_S32_SPI2_CLK 276U
|
||||
#define NXP_S32_SPI3_CLK 277U
|
||||
#define NXP_S32_SPI4_CLK 278U
|
||||
#define NXP_S32_P4_DSPI_CLK 279U
|
||||
#define NXP_S32_SPI5_CLK 280U
|
||||
#define NXP_S32_SPI6_CLK 281U
|
||||
#define NXP_S32_SPI7_CLK 282U
|
||||
#define NXP_S32_P5_DSPI_CLK 283U
|
||||
#define NXP_S32_SPI8_CLK 284U
|
||||
#define NXP_S32_SPI9_CLK 285U
|
||||
#define NXP_S32_SRX0_CLK 286U
|
||||
#define NXP_S32_SRX1_CLK 287U
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_ */
|
||||
|
|
@ -14,5 +14,6 @@ config SOC_SERIES_S32ZE_R52
|
|||
select VFP_DP_D16
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
select SOC_FAMILY_NXP_S32
|
||||
select CLOCK_CONTROL
|
||||
help
|
||||
Enable support for NXP S32Z/E MCUs family on Cortex-R52 cores.
|
||||
|
|
|
|||
|
|
@ -26,14 +26,6 @@ config SOC_PART_NUMBER_S32ZE_R52
|
|||
that you should not set directly. The part number selection choice defines
|
||||
the default value for this string.
|
||||
|
||||
config INIT_CLOCK_AT_BOOT_TIME
|
||||
bool "Initialize clocks at boot time"
|
||||
default y
|
||||
help
|
||||
Initialize clocks at boot time with the configuration generated through the
|
||||
driver's configurator, instead of using the default SoC clock configuration
|
||||
at reset.
|
||||
|
||||
config NXP_S32_RTU_INDEX
|
||||
int
|
||||
range 0 1
|
||||
|
|
|
|||
|
|
@ -12,11 +12,6 @@
|
|||
|
||||
#include <OsIf.h>
|
||||
|
||||
#ifdef CONFIG_INIT_CLOCK_AT_BOOT_TIME
|
||||
#include <Clock_Ip.h>
|
||||
#include <Clock_Ip_Cfg.h>
|
||||
#endif
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
/* enable peripheral port access at EL1 and EL0 */
|
||||
|
|
@ -47,11 +42,6 @@ static int soc_init(void)
|
|||
{
|
||||
OsIf_Init(NULL);
|
||||
|
||||
#ifdef CONFIG_INIT_CLOCK_AT_BOOT_TIME
|
||||
/* Initialize clocks with tool generated code */
|
||||
Clock_Ip_Init(Clock_Ip_aClockConfig);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue