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soc: xtensa: intel_adsp: cavs: fix power_down_cavs() signature

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The second argument 'uint32_t *hpsram_pg_mask' must be a cached
pointer and this needs to be reflected in function prototype.

Fixes sparse warning:
/zep_workspace/zephyr/soc/xtensa/intel_adsp/cavs/power.c:106:63:
warning: incorrect type in argument 2 (different address spaces)

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit is contained in:
Kai Vehmanen 2023-08-29 13:51:54 +03:00 • committed by Carles Cufí
commit ffd2121c65
1 changed files with 2 additions and 2 deletions
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4
soc/xtensa/intel_adsp/cavs/power.c
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@ -69,7 +69,7 @@ static struct core_state core_desc[CONFIG_MP_MAX_NUM_CPUS] = {{0}};
* @param hpsram_pg_mask pointer to memory segments power gating mask
* (each bit corresponds to one ebb)
*/
extern void power_down_cavs(bool disable_lpsram, uint32_t *hpsram_pg_mask);
extern void power_down_cavs(bool disable_lpsram, uint32_t __sparse_cache * hpsram_pg_mask);
static inline void __sparse_cache *uncache_to_cache(void *address)
{
@ -95,7 +95,7 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
};
struct imr_layout *imr_layout = (struct imr_layout *)L3_MEM_BASE_ADDR;
__ASSERT_NO_MSG(arch_xtensa_is_ptr_uncached(L3_MEM_BASE_ADDR));
__ASSERT_NO_MSG(arch_xtensa_is_ptr_uncached((void *)L3_MEM_BASE_ADDR));
imr_layout->imr_state.header = hdr;
#ifdef CONFIG_ADSP_POWER_DOWN_HPSRAM