michaelh/zephyr
1
0
Fork 0
Code Releases Activity

dai: intel: dmic: Combine PDM registers definitions

Browse source 
All PDM controllers have the same set of registers. Their definitions have
been merged to simplify the code.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
This commit is contained in:
Adrian Warecki 2023-05-05 16:06:19 +02:00 • committed by Anas Nashif
commit d7672af838
4 changed files with 28 additions and 80 deletions
Download patch file Download diff file Expand all files Collapse all files

53
drivers/dai/intel/dmic/dmic.c
View file

@ -237,18 +237,9 @@ static void dai_dmic_stop_fifo_packers(struct dai_intel_dmic *dmic,
int fifo_index)
{
/* Stop FIFO packers and set FIFO initialize bits */
switch (fifo_index) {
case 0:
dai_dmic_update_bits(dmic, OUTCONTROL0,
OUTCONTROL_SIP | OUTCONTROL_FINIT,
OUTCONTROL_FINIT);
break;
case 1:
dai_dmic_update_bits(dmic, OUTCONTROL1,
OUTCONTROL_SIP | OUTCONTROL_FINIT,
OUTCONTROL_FINIT);
break;
}
dai_dmic_update_bits(dmic, fifo_index * PDM_CHANNEL_REGS_SIZE + OUTCONTROL,
OUTCONTROL_SIP | OUTCONTROL_FINIT,
OUTCONTROL_FINIT);
}
/* On DMIC IRQ event trace the status register that contains the status and
@ -261,19 +252,19 @@ static void dai_dmic_irq_handler(const void *data)
uint32_t val1;
/* Trace OUTSTAT0 register */
val0 = dai_dmic_read(dmic, OUTSTAT0);
val1 = dai_dmic_read(dmic, OUTSTAT1);
val0 = dai_dmic_read(dmic, OUTSTAT);
val1 = dai_dmic_read(dmic, OUTSTAT + PDM_CHANNEL_REGS_SIZE);
LOG_DBG("dmic_irq_handler(), OUTSTAT0 = 0x%x, OUTSTAT1 = 0x%x", val0, val1);
if (val0 & OUTSTAT_ROR) {
LOG_ERR("dmic_irq_handler(): full fifo A or PDM overrun");
dai_dmic_write(dmic, OUTSTAT0, val0);
dai_dmic_write(dmic, OUTSTAT, val0);
dai_dmic_stop_fifo_packers(dmic, 0);
}
if (val1 & OUTSTAT_ROR) {
LOG_ERR("dmic_irq_handler(): full fifo B or PDM overrun");
dai_dmic_write(dmic, OUTSTAT1, val1);
dai_dmic_write(dmic, OUTSTAT + PDM_CHANNEL_REGS_SIZE, val1);
dai_dmic_stop_fifo_packers(dmic, 1);
}
}
@ -556,7 +547,7 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
/* enable port */
key = k_spin_lock(&dmic->lock);
LOG_DBG("dmic_start()");
LOG_DBG("dmic_start(), dai_index = %d", dmic->dai_config_params.dai_index);
dmic->startcount = 0;
/* Compute unmute ramp gain update coefficient. */
@ -567,27 +558,13 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
dai_dmic_sync_prepare(dmic);
switch (dmic->dai_config_params.dai_index) {
case 0:
LOG_INF("dmic_start(), dmic->fifo_a");
/* Clear FIFO A initialize, Enable interrupts to DSP,
* Start FIFO A packer.
*/
dai_dmic_update_bits(
dmic,
OUTCONTROL0,
OUTCONTROL_FINIT | OUTCONTROL_SIP,
OUTCONTROL_SIP);
break;
case 1:
LOG_INF("dmic_start(), dmic->fifo_b");
/* Clear FIFO B initialize, Enable interrupts to DSP,
* Start FIFO B packer.
*/
dai_dmic_update_bits(dmic, OUTCONTROL1,
OUTCONTROL_FINIT | OUTCONTROL_SIP,
OUTCONTROL_SIP);
}
/* Clear FIFO initialize, Enable interrupts to DSP,
* Start FIFO packer.
*/
dai_dmic_update_bits(dmic,
dmic->dai_config_params.dai_index * PDM_CHANNEL_REGS_SIZE + OUTCONTROL,
OUTCONTROL_FINIT | OUTCONTROL_SIP,
OUTCONTROL_SIP);
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
#ifdef CONFIG_SOC_SERIES_INTEL_ACE

7
drivers/dai/intel/dmic/dmic_nhlt.c
View file

@ -532,10 +532,9 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
val = (out_control[dmic->dai_config_params.dai_index] &
~(OUTCONTROL_TIE | OUTCONTROL_SIP | OUTCONTROL_FCI)) |
OUTCONTROL_FINIT;
if (dmic->dai_config_params.dai_index == 0)
dai_dmic_write(dmic, OUTCONTROL0, val);
else
dai_dmic_write(dmic, OUTCONTROL1, val);
dai_dmic_write(dmic, dmic->dai_config_params.dai_index * PDM_CHANNEL_REGS_SIZE +
OUTCONTROL, val);
LOG_INF("dmic_set_config_nhlt(): OUTCONTROL%d = %08x",
dmic->dai_config_params.dai_index, val);

24
soc/xtensa/intel_adsp/ace/include/dmic_regs.h
View file

@ -70,13 +70,13 @@
*/
/* Control registers for packers */
#define OUTCONTROL0 0x0000
#define OUTCONTROL 0x0000
/* Status Register for FIFO interface */
#define OUTSTAT0 0x0004
#define OUTSTAT 0x0004
/* Data read/Write port for FIFO */
#define OUTDATA0 0x0008
#define OUTDATA 0x0008
/* (crossed out) 000Ch LOCAL_OFFS Offset Counter
* (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
@ -84,23 +84,9 @@
* 001Ch - 00FFh Reserved space for extensions
*/
/* Offset to PDM Secondary Channel */
#define PDM_CHANNEL_REGS_SIZE 0x100
/* PDM Secondary Channel */
/* Control registers for packers */
#define OUTCONTROL1 0x0100
/* Status Register for FIFO interface */
#define OUTSTAT1 0x0104
/* Data read/Write port for FIFO */
#define OUTDATA1 0x0108
/* (crossed out) 010Ch LOCAL_OFFS Offset Counter
* (crossed out) 0110h LOCAL_TSC0 64-bit Wall Clock timestamp
* (crossed out) 0118h LOCAL_SAMPLE0 64-bit Sample Count
* 011Ch - 0FFFh Reserved space for extensions
*/
#define GLOBAL_CAPABILITIES 0x200

24
soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h
View file

@ -67,13 +67,13 @@
*/
/* Control registers for packers */
#define OUTCONTROL0 0x0000
#define OUTCONTROL 0x0000
/* Status Register for FIFO interface */
#define OUTSTAT0 0x0004
#define OUTSTAT 0x0004
/* Data read/Write port for FIFO */
#define OUTDATA0 0x0008
#define OUTDATA 0x0008
/* (crossed out) 000Ch LOCAL_OFFS Offset Counter
* (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
@ -81,23 +81,9 @@
* 001Ch - 00FFh Reserved space for extensions
*/
/* Offset to PDM Secondary Channel */
#define PDM_CHANNEL_REGS_SIZE 0x100
/* PDM Secondary Channel */
/* Control registers for packers */
#define OUTCONTROL1 0x0100
/* Status Register for FIFO interface */
#define OUTSTAT1 0x0104
/* Data read/Write port for FIFO */
#define OUTDATA1 0x0108
/* (crossed out) 010Ch LOCAL_OFFS Offset Counter
* (crossed out) 0110h LOCAL_TSC0 64-bit Wall Clock timestamp
* (crossed out) 0118h LOCAL_SAMPLE0 64-bit Sample Count
* 011Ch - 0FFFh Reserved space for extensions
*/
#define GLOBAL_CAPABILITIES 0x200