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soc: nxp_s32: add LPSPI to S32K344

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Reuse existing NXP LPSPI binding for this SoC since the hardware block
for this device is the same as the one supported for other NXP devices.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles 2023-07-06 17:49:58 -03:00 • committed by Carles Cufí
commit c7200cac00
2 changed files with 61 additions and 0 deletions
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60
dts/arm/nxp/nxp_s32k344_m7.dtsi
View file

@ -529,6 +529,66 @@
#io-channel-cells = <1>;
status = "disabled";
};
lpspi0: spi@40358000 {
compatible = "nxp,imx-lpspi";
reg = <0x40358000 0x4000>;
interrupts = <165 0>;
clocks = <&clock NXP_S32_LPSPI0_CLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
lpspi1: spi@4035c000 {
compatible = "nxp,imx-lpspi";
reg = <0x4035c000 0x4000>;
interrupts = <166 0>;
clocks = <&clock NXP_S32_LPSPI1_CLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
lpspi2: spi@40360000 {
compatible = "nxp,imx-lpspi";
reg = <0x40360000 0x4000>;
interrupts = <167 0>;
clocks = <&clock NXP_S32_LPSPI2_CLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
lpspi3: spi@40364000 {
compatible = "nxp,imx-lpspi";
reg = <0x40364000 0x4000>;
interrupts = <168 0>;
clocks = <&clock NXP_S32_LPSPI3_CLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
lpspi4: spi@404bc000 {
compatible = "nxp,imx-lpspi";
reg = <0x404bc000 0x4000>;
interrupts = <169 0>;
clocks = <&clock NXP_S32_LPSPI4_CLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
lpspi5: spi@404c0000 {
compatible = "nxp,imx-lpspi";
reg = <0x404c0000 0x4000>;
interrupts = <170 0>;
clocks = <&clock NXP_S32_LPSPI5_CLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};

1
soc/arm/nxp_s32/s32k/Kconfig.series
View file

@ -18,5 +18,6 @@ config SOC_SERIES_S32K3_M7
select HAS_MCUX_LPUART
select HAS_MCUX_FLEXCAN
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
help
Enable support for NXP S32K3 MCUs family on Cortex-M7 cores