soc: arm: nxp_s32: s32k1: fix code cache init
Currently Code Cache cannot be enabled because its initialization is guarded by Kconfig options which depend on CPU core cache support, but S32K14x devices has a SoC specific L1 cache controller. Hence, introduce a SoC-specific symbol to enable Code Cache. Note that the cache controller is not available for S32K11x devices. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
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2 changed files with 12 additions and 1 deletions
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@ -20,36 +20,42 @@ config SOC_S32K142
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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config SOC_S32K142W
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bool "S32K142W"
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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config SOC_S32K144
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bool "S32K144"
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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config SOC_S32K144W
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bool "S32K144W"
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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config SOC_S32K146
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bool "S32K146"
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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config SOC_S32K148
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bool "S32K148"
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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endchoice
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@ -431,4 +437,9 @@ config NXP_S32_FLASH_CONFIG_FDPROT
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endif # NXP_S32_FLASH_CONFIG
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config NXP_S32_ENABLE_CODE_CACHE
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bool "Code cache"
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default y
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depends on HAS_MCUX_CACHE
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endif # SOC_SERIES_S32K1XX
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@ -63,7 +63,7 @@ static int soc_init(void)
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IP_MPU->CESR = tmp;
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#endif /* !CONFIG_ARM_MPU */
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#if defined(CONFIG_DCACHE) && defined(CONFIG_ICACHE)
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#if defined(CONFIG_HAS_MCUX_CACHE) && defined(CONFIG_NXP_S32_ENABLE_CODE_CACHE)
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/* Invalidate all ways */
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IP_LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
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IP_LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;
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