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nxp: s32ze: take exceptions in Arm mode

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Cortex-R52 supports both Arm and Thumb-2 mode, but Zephyr's ASM
code for Armv-8 Aarch32 is written for Arm mode only. This Soc
has a general purpose register that can set the core TEINIT signal
to change the mode exceptions are taken before booting up the core.
The debugger startup scripts or firmware booting up the core may
configure this bit to Thumb mode, as is the case of the NXP S32 debug
probe startup scripts for S32ZE.

Due to above reason, clear SCTLR.TE bit at reset so that TEINIT value
is ignored and exceptions are always taken into Arm mode, compatible
with current Zephyr ASM code. At least until taking execeptions in Thumb
mode is supported in Zephyr.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles 2023-09-28 16:38:12 +07:00 • committed by Martí Bolívar
commit a7bda08960
1 changed files with 6 additions and 0 deletions
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6
soc/arm/nxp_s32/s32ze/soc.c
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@ -21,6 +21,12 @@ void z_arm_platform_init(void)
barrier_dsync_fence_full();
barrier_isync_fence_full();
/*
* Take exceptions in Arm mode because Zephyr ASM code for Cortex-R Aarch32
* is written for Arm
*/
__set_SCTLR(__get_SCTLR() & ~SCTLR_TE_Msk);
if (IS_ENABLED(CONFIG_ICACHE)) {
if (!(__get_SCTLR() & SCTLR_I_Msk)) {
L1C_InvalidateICacheAll();