drivers: mdio: Add xmc4xxx mdio drivers
Add mdio drivers for xmc4xxx SoCs. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
This commit is contained in:
parent
201167bdb1
commit
d540407fc8
12 changed files with 295 additions and 0 deletions
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@ -10,3 +10,4 @@ zephyr_library_sources_ifdef(CONFIG_MDIO_NXP_S32_GMAC mdio_nxp_s32_gmac.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_ADIN2111 mdio_adin2111.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_GPIO mdio_gpio.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_NXP_ENET mdio_nxp_enet.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_INFINEON_XMC4XXX mdio_xmc4xxx.c)
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@ -31,6 +31,7 @@ source "drivers/mdio/Kconfig.nxp_s32_gmac"
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source "drivers/mdio/Kconfig.adin2111"
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source "drivers/mdio/Kconfig.gpio"
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source "drivers/mdio/Kconfig.nxp_enet"
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source "drivers/mdio/Kconfig.xmc4xxx"
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config MDIO_INIT_PRIORITY
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int "Init priority"
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9
drivers/mdio/Kconfig.xmc4xxx
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9
drivers/mdio/Kconfig.xmc4xxx
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@ -0,0 +1,9 @@
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# Copyright (c) 2023 SLB
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# SPDX-License-Identifier: Apache-2.0
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config MDIO_INFINEON_XMC4XXX
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bool "Infineon XMC4XXX MDIO driver"
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default y
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depends on DT_HAS_INFINEON_XMC4XXX_MDIO_ENABLED
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help
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Enable Infineon XMC4XXX MDIO driver.
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@ -31,6 +31,8 @@ LOG_MODULE_REGISTER(mdio_shell, CONFIG_LOG_DEFAULT_LEVEL);
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#define DT_DRV_COMPAT zephyr_mdio_gpio
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#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_enet_mdio)
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#define DT_DRV_COMPAT nxp_enet_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(infineon_xmc4xxx_mdio)
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#define DT_DRV_COMPAT infineon_xmc4xxx_mdio
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#else
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#error "No known devicetree compatible match for MDIO shell"
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#endif
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185
drivers/mdio/mdio_xmc4xxx.c
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185
drivers/mdio/mdio_xmc4xxx.c
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@ -0,0 +1,185 @@
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/*
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* Copyright (c) 2023 SLB
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT infineon_xmc4xxx_mdio
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#include <errno.h>
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#include <soc.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/mdio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <xmc_scu.h>
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#include <xmc_eth_mac.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(mdio_xmc4xxx, CONFIG_MDIO_LOG_LEVEL);
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#define MDIO_TRANSFER_TIMEOUT_US 250000
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#define MAX_MDC_FREQUENCY 2500000u /* 400ns period */
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#define MIN_MDC_FREQUENCY 1000000u /* 1us period */
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struct mdio_xmc4xxx_clock_divider {
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uint8_t divider;
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uint8_t reg_val;
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};
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static const struct mdio_xmc4xxx_clock_divider mdio_clock_divider[] = {
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{.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
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{.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
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{.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
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};
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struct mdio_xmc4xxx_dev_data {
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struct k_mutex mutex;
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uint32_t reg_value_gmii_address;
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};
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struct mdio_xmc4xxx_dev_config {
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ETH_GLOBAL_TypeDef *const regs;
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const struct pinctrl_dev_config *pcfg;
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uint8_t mdi_port_ctrl;
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};
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static int mdio_xmc4xxx_transfer(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr,
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uint8_t is_write, uint16_t data_write, uint16_t *data_read)
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{
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const struct mdio_xmc4xxx_dev_config *const dev_cfg = dev->config;
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ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs;
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struct mdio_xmc4xxx_dev_data *const dev_data = dev->data;
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uint32_t reg;
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int ret = 0;
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k_mutex_lock(&dev_data->mutex, K_FOREVER);
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if ((regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) != 0) {
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ret = -EBUSY;
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goto finish;
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}
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reg = dev_data->reg_value_gmii_address;
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if (is_write) {
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reg |= ETH_GMII_ADDRESS_MW_Msk;
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regs->GMII_DATA = data_write;
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}
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regs->GMII_ADDRESS = reg | ETH_GMII_ADDRESS_MB_Msk |
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FIELD_PREP(ETH_GMII_ADDRESS_PA_Msk, phy_addr) |
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FIELD_PREP(ETH_GMII_ADDRESS_MR_Msk, reg_addr);
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if (!WAIT_FOR((regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) == 0,
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MDIO_TRANSFER_TIMEOUT_US, k_msleep(5))) {
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LOG_WRN("mdio transfer timedout");
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ret = -ETIMEDOUT;
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goto finish;
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}
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if (!is_write && data_read != NULL) {
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*data_read = regs->GMII_DATA;
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}
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finish:
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k_mutex_unlock(&dev_data->mutex);
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return ret;
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}
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static int mdio_xmc4xxx_read(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr,
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uint16_t *data)
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{
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return mdio_xmc4xxx_transfer(dev, phy_addr, reg_addr, 0, 0, data);
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}
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static int mdio_xmc4xxx_write(const struct device *dev, uint8_t phy_addr,
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uint8_t reg_addr, uint16_t data)
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{
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return mdio_xmc4xxx_transfer(dev, phy_addr, reg_addr, 1, data, NULL);
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}
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static void mdio_xmc4xxx_bus_enable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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/* this will enable the clock for ETH, which generates to MDIO clk */
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XMC_ETH_MAC_Enable(NULL);
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}
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static void mdio_xmc4xxx_bus_disable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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XMC_ETH_MAC_Disable(NULL);
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}
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static int mdio_xmc4xxx_set_clock_divider(const struct device *dev)
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{
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struct mdio_xmc4xxx_dev_data *dev_data = dev->data;
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uint32_t eth_mac_clk = XMC_SCU_CLOCK_GetEthernetClockFrequency();
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for (int i = 0; i < ARRAY_SIZE(mdio_clock_divider); i++) {
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uint8_t divider = mdio_clock_divider[i].divider;
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uint8_t reg_val = mdio_clock_divider[i].reg_val;
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uint32_t mdc_clk = eth_mac_clk / divider;
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if (mdc_clk > MIN_MDC_FREQUENCY && mdc_clk < MAX_MDC_FREQUENCY) {
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LOG_DBG("Using MDC clock divider %d", divider);
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LOG_DBG("MDC clock %dHz", mdc_clk);
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dev_data->reg_value_gmii_address =
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FIELD_PREP(ETH_GMII_ADDRESS_CR_Msk, reg_val);
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return 0;
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}
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}
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return -EINVAL;
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}
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static int mdio_xmc4xxx_initialize(const struct device *dev)
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{
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const struct mdio_xmc4xxx_dev_config *dev_cfg = dev->config;
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struct mdio_xmc4xxx_dev_data *dev_data = dev->data;
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XMC_ETH_MAC_PORT_CTRL_t port_ctrl = {0};
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int ret;
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k_mutex_init(&dev_data->mutex);
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ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret != 0) {
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return ret;
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}
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ret = mdio_xmc4xxx_set_clock_divider(dev);
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if (ret != 0) {
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LOG_ERR("Error setting MDIO clock divider");
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return -EINVAL;
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}
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port_ctrl.mdio = dev_cfg->mdi_port_ctrl;
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ETH0_CON->CON = port_ctrl.raw;
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return ret;
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}
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static const struct mdio_driver_api mdio_xmc4xxx_driver_api = {
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.read = mdio_xmc4xxx_read,
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.write = mdio_xmc4xxx_write,
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.bus_enable = mdio_xmc4xxx_bus_enable,
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.bus_disable = mdio_xmc4xxx_bus_disable,
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};
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PINCTRL_DT_INST_DEFINE(0);
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static const struct mdio_xmc4xxx_dev_config mdio_xmc4xxx_dev_config_0 = {
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.regs = (ETH_GLOBAL_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(0)),
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
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.mdi_port_ctrl = DT_INST_ENUM_IDX(0, mdi_port_ctrl),
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};
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static struct mdio_xmc4xxx_dev_data mdio_xmc4xxx_dev_data_0;
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DEVICE_DT_INST_DEFINE(0, &mdio_xmc4xxx_initialize, NULL, &mdio_xmc4xxx_dev_data_0,
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&mdio_xmc4xxx_dev_config_0, POST_KERNEL,
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CONFIG_MDIO_INIT_PRIORITY, &mdio_xmc4xxx_driver_api);
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@ -425,4 +425,27 @@
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/omit-if-no-ref/ i2c_scl_dout1_p1_10_u0c0: i2c_scl_dout1_p1_10_u0c0 {
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pinmux = <XMC4XXX_PINMUX_SET(1, 10, 2)>;
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};
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/omit-if-no-ref/ eth_p0_9_mdo: ebu_p0_9_mdo {
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pinmux = <XMC4XXX_PINMUX_SET(0, 9, 0)>;
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hwctrl = "periph1";
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};
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/omit-if-no-ref/ eth_p1_11_mdo: ebu_p1_11_mdo {
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pinmux = <XMC4XXX_PINMUX_SET(1, 11, 0)>;
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hwctrl = "periph1";
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};
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/omit-if-no-ref/ eth_p2_0_mdo: ebu_p2_0_mdo {
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pinmux = <XMC4XXX_PINMUX_SET(2, 0, 0)>;
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hwctrl = "periph1";
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};
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/omit-if-no-ref/ eth_p0_9_mdio: eth_p0_9_mdio {
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pinmux = <XMC4XXX_PINMUX_SET(0, 9, 0)>;
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};
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/omit-if-no-ref/ eth_p2_0_mdio: eth_p2_0_mdio {
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pinmux = <XMC4XXX_PINMUX_SET(2, 0, 0)>;
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};
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/omit-if-no-ref/ eth_p1_11_mdio: eth_p1_11_mdio {
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pinmux = <XMC4XXX_PINMUX_SET(1, 11, 0)>;
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};
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};
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/omit-if-no-ref/ i2c_scl_dout1_p3_9_u2c0: i2c_scl_dout1_p3_9_u2c0 {
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pinmux = <XMC4XXX_PINMUX_SET(3, 9, 1)>;
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};
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/omit-if-no-ref/ eth_p0_9_mdo: eth_p0_9_mdo {
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pinmux = <XMC4XXX_PINMUX_SET(0, 9, 0)>;
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hwctrl = "periph1";
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};
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/omit-if-no-ref/ eth_p1_11_mdo: eth_p1_11_mdo {
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pinmux = <XMC4XXX_PINMUX_SET(1, 11, 0)>;
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hwctrl = "periph1";
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};
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/omit-if-no-ref/ eth_p2_0_mdo: eth_p2_0_mdo {
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pinmux = <XMC4XXX_PINMUX_SET(2, 0, 0)>;
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hwctrl = "periph1";
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};
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/omit-if-no-ref/ eth_p0_9_mdio: eth_p0_9_mdio {
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pinmux = <XMC4XXX_PINMUX_SET(0, 9, 0)>;
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};
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/omit-if-no-ref/ eth_p2_0_mdio: eth_p2_0_mdio {
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pinmux = <XMC4XXX_PINMUX_SET(2, 0, 0)>;
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};
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/omit-if-no-ref/ eth_p1_11_mdio: eth_p1_11_mdio {
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pinmux = <XMC4XXX_PINMUX_SET(1, 11, 0)>;
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};
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};
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@ -236,6 +236,17 @@
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interrupts = <0 1>;
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status = "disabled";
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};
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ethernet@5000c000 {
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reg = <0x5000C000 0x3FFF>;
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mdio: mdio {
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compatible = "infineon,xmc4xxx-mdio";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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};
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31
dts/bindings/mdio/infineon,xmc4xxx-mdio.yaml
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31
dts/bindings/mdio/infineon,xmc4xxx-mdio.yaml
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# Copyright (c) 2023 SLB
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# SPDX-License-Identifier: Apache-2.0
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description: Infineon xmc4xxx Family MDIO Driver node
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compatible: "infineon,xmc4xxx-mdio"
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include:
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- name: mdio-controller.yaml
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- name: pinctrl-device.yaml
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properties:
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mdi-port-ctrl:
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description: |
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The MDIO input is connected to several port/pins via a mux.
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This is not handled by pinctrl because the mux is located at the
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peripheral and not GPIO. The possible connections are defined by
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an enum.
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type: string
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enum:
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- "P0_9"
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- "P2_0"
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- "P1_11"
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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@ -55,4 +55,9 @@ config HAS_XMCLIB_WDT
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help
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Enable XMCLIB WDT
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config HAS_XMCLIB_ETH
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bool
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help
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Enable XMCLIB Ethernet MAC
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endif # HAS_XMCLIB
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@ -21,5 +21,6 @@ config SOC_SERIES_XMC_4XXX
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select HAS_XMCLIB_I2C
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select HAS_XMCLIB_CCU
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select HAS_XMCLIB_WDT
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select HAS_XMCLIB_ETH
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help
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Enable support for XMC 4xxx MCU series
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@ -37,6 +37,9 @@ void z_arm_platform_init(void)
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#endif
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#ifdef CONFIG_PWM_XMC4XXX_CCU8
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| XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_CCU
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#endif
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#ifdef CONFIG_ETH_XMC4XXX
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| XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_ETH
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#endif
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);
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