boards: mimxrt595: add CONFIG_MIPI_DPHY_CLK_SRC
Give option in soc.c to initialize the MIPI DPHY clock from the default AUX1_PLL, or from the FRO using CONFIG_MIPI_DPHY_CLK_SRC_FRO. Signed-off-by: Derek Snell <derek.snell@nxp.com>
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3f2ded3455
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2 changed files with 22 additions and 1 deletions
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@ -141,4 +141,16 @@ config FLEXCOMM0_CLK_SRC_FRO
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endchoice
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choice MIPI_DPHY_CLK_SRC
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prompt "Clock source for MIPI DPHY"
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default MIPI_DPHY_CLK_SRC_AUX1_PLL
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config MIPI_DPHY_CLK_SRC_AUX1_PLL
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bool "AUX1_PLL is source of MIPI_DPHY clock"
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config MIPI_DPHY_CLK_SRC_FRO
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bool "FRO 192/96M is source of MIPI_DPHY clock"
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endchoice
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endif # SOC_SERIES_IMX_RT5XX
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@ -462,12 +462,21 @@ void __weak imxrt_pre_init_display_interface(void)
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* We set the divider of the PFD3 output of the SYSPLL, which has a
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* fixed multiplied of 18, and use this output frequency for the DPHY.
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*/
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#ifdef CONFIG_MIPI_DPHY_CLK_SRC_AUX1_PLL
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/* Note: AUX1 PLL clock is system pll clock * 18 / pfd.
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* system pll clock is configured at 528MHz by default.
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*/
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CLOCK_AttachClk(kAUX1_PLL_to_MIPI_DPHY_CLK);
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CLOCK_InitSysPfd(kCLOCK_Pfd3,
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((CLOCK_GetSysPllFreq() * 18ull) /
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((unsigned long long)(DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock)))));
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CLOCK_SetClkDiv(kCLOCK_DivDphyClk, 1);
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#elif defined(CONFIG_MIPI_DPHY_CLK_SRC_FRO)
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CLOCK_AttachClk(kFRO_DIV1_to_MIPI_DPHY_CLK);
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CLOCK_SetClkDiv(kCLOCK_DivDphyClk,
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(CLK_FRO_CLK / DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock)));
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#endif
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/* Clear DSI control reset (Note that DPHY reset is cleared later)*/
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RESET_ClearPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn);
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}
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