soc: nxp_s32: generalize pinctrl header for all family
Unify the pinctrl_soc.h header for all the NXP S32 family by using the HAL macros that expose the features supported on specific devices. This approach still need a different binding for each device to expose in DT different properties and allowed values. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Arguelles
Mahesh Mahadevan
parent
8a47dd5ff8
commit
00125a4d1e
3 changed files with 148 additions and 152 deletions
148
soc/arm/nxp_s32/common/pinctrl_soc.h
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148
soc/arm/nxp_s32/common/pinctrl_soc.h
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/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h>
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#include <zephyr/sys/util_macro.h>
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#include <zephyr/types.h>
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#include <Siul2_Port_Ip.h>
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/** @cond INTERNAL_HIDDEN */
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/** @brief Type for NXP S32 pin configuration. */
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typedef Siul2_Port_Ip_PinSettingsConfig pinctrl_soc_pin_t;
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#if defined(SIUL2_PORT_IP_MULTIPLE_SIUL2_INSTANCES)
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#define NXP_S32_SIUL2_IDX(n) \
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n == 0 ? IP_SIUL2_0 : (n == 1 ? IP_SIUL2_1 : ( \
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n == 3 ? IP_SIUL2_3 : (n == 4 ? IP_SIUL2_4 : ( \
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n == 5 ? IP_SIUL2_5 : (NULL)))))
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#else
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#define NXP_S32_SIUL2_IDX(n) (n == 0 ? IP_SIUL2 : NULL)
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#endif
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#define NXP_S32_INPUT_BUFFER(group) \
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COND_CODE_1(DT_PROP(group, input_enable), (PORT_INPUT_BUFFER_ENABLED), \
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(PORT_INPUT_BUFFER_DISABLED))
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#define NXP_S32_OUTPUT_BUFFER(group) \
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COND_CODE_1(DT_PROP(group, output_enable), (PORT_OUTPUT_BUFFER_ENABLED), \
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(PORT_OUTPUT_BUFFER_DISABLED))
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#define NXP_S32_INPUT_MUX_REG(group, val) \
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COND_CODE_1(DT_PROP(group, input_enable), (NXP_S32_PINMUX_GET_IMCR_IDX(val)), \
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(0U))
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#define NXP_S32_INPUT_MUX(group, val) \
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COND_CODE_1(DT_PROP(group, input_enable), \
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((Siul2_Port_Ip_PortInputMux)NXP_S32_PINMUX_GET_IMCR_SSS(val)), \
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(PORT_INPUT_MUX_NO_INIT))
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#define NXP_S32_PULL_SEL(group) \
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COND_CODE_1(DT_PROP(group, bias_pull_up), (PORT_INTERNAL_PULL_UP_ENABLED), \
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(COND_CODE_1(DT_PROP(group, bias_pull_down), \
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(PORT_INTERNAL_PULL_DOWN_ENABLED), (PORT_INTERNAL_PULL_NOT_ENABLED))))
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#if defined(SIUL2_PORT_IP_HAS_ONEBIT_SLEWRATE)
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#define NXP_S32_SLEW_RATE(group) \
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COND_CODE_1(DT_NODE_HAS_PROP(group, slew_rate), \
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(UTIL_CAT(PORT_SLEW_RATE_, DT_STRING_UPPER_TOKEN(group, slew_rate))), \
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(PORT_SLEW_RATE_FASTEST))
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#else
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#define NXP_S32_SLEW_RATE(group) \
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COND_CODE_1(DT_NODE_HAS_PROP(group, slew_rate), \
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(UTIL_CAT(PORT_SLEW_RATE_CONTROL, DT_PROP(group, slew_rate))), \
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(PORT_SLEW_RATE_CONTROL0))
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#endif
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#define NXP_S32_DRIVE_STRENGTH(group) \
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COND_CODE_1(DT_PROP(group, nxp_drive_strength), \
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(PORT_DRIVE_STRENTGTH_ENABLED), (PORT_DRIVE_STRENTGTH_DISABLED))
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#define NXP_S32_INVERT(group) \
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COND_CODE_1(DT_PROP(group, nxp_invert), \
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(PORT_INVERT_ENABLED), (PORT_INVERT_DISABLED))
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/* To enable open drain both OBE and ODE bits need to be set */
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#define NXP_S32_OPEN_DRAIN(group) \
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(DT_PROP(group, drive_open_drain) && DT_PROP(group, output_enable) ? \
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(PORT_OPEN_DRAIN_ENABLED) : (PORT_OPEN_DRAIN_DISABLED))
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/* Only a single input mux is configured, the rest is not used */
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#define NXP_S32_INPUT_MUX_NO_INIT \
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[1 ... (FEATURE_SIUL2_MAX_NUMBER_OF_INPUT-1)] = PORT_INPUT_MUX_NO_INIT
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#define NXP_S32_PINMUX_INIT(group, val) \
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.base = NXP_S32_SIUL2_IDX(NXP_S32_PINMUX_GET_SIUL2_IDX(val)), \
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.pinPortIdx = NXP_S32_PINMUX_GET_MSCR_IDX(val), \
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.mux = (Siul2_Port_Ip_PortMux)NXP_S32_PINMUX_GET_MSCR_SSS(val), \
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.inputMux = { \
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NXP_S32_INPUT_MUX(group, val), \
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NXP_S32_INPUT_MUX_NO_INIT \
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}, \
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.inputMuxReg = { \
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NXP_S32_INPUT_MUX_REG(group, val) \
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}, \
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.inputBuffer = NXP_S32_INPUT_BUFFER(group), \
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.outputBuffer = NXP_S32_OUTPUT_BUFFER(group), \
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.pullConfig = NXP_S32_PULL_SEL(group), \
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.safeMode = PORT_SAFE_MODE_DISABLED, \
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.slewRateCtrlSel = NXP_S32_SLEW_RATE(group), \
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.initValue = PORT_PIN_LEVEL_NOTCHANGED_U8, \
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IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_DRIVE_STRENGTH, \
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(.driveStrength = NXP_S32_DRIVE_STRENGTH(group),)) \
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IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_INVERT_DATA, \
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(.invert = NXP_S32_INVERT(group),)) \
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IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_OPEN_DRAIN, \
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(.openDrain = NXP_S32_OPEN_DRAIN(group),)) \
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IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_INPUT_FILTER, \
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(.inputFilter = PORT_INPUT_FILTER_DISABLED,)) \
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IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_RECEIVER_SELECT, \
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(.receiverSel = PORT_RECEIVER_ENABLE_SINGLE_ENDED,)) \
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IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_HYSTERESIS, \
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(.hysteresis = PORT_HYSTERESIS_DISABLED,)) \
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IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_ANALOG_PAD_CONTROL, \
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(.analogPadControl = PORT_ANALOG_PAD_CONTROL_DISABLED,)) \
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IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_TERMINATION_RESISTOR, \
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(.terminationResistor = PORT_TERMINATION_RESISTOR_DISABLED,)) \
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IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_CURRENT_REFERENCE_CONTROL, \
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(.currentReferenceControl = PORT_CURRENT_REFERENCE_CONTROL_DISABLED,)) \
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IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_RX_CURRENT_BOOST, \
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(.rxCurrentBoost = PORT_RX_CURRENT_BOOST_DISABLED,)) \
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IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_PULL_KEEPER, \
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(.pullKeep = PORT_PULL_KEEP_DISABLED,))
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/**
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* @brief Utility macro to initialize each pin.
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*
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*
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* @param group Group node identifier.
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* @param prop Property name.
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* @param idx Property entry index.
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*/
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#define Z_PINCTRL_STATE_PIN_INIT(group, prop, idx) \
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{ \
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NXP_S32_PINMUX_INIT(group, DT_PROP_BY_IDX(group, prop, idx)) \
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},
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/**
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* @brief Utility macro to initialize state pins contained in a given property.
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*
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* @param node_id Node identifier.
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* @param prop Property name describing state pins.
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*/
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
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DT_FOREACH_PROP_ELEM, pinmux, \
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Z_PINCTRL_STATE_PIN_INIT)}
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/** @endcond */
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#endif /* ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_H_ */
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@ -1,100 +0,0 @@
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/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_COMMON_H_
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#define ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_COMMON_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h>
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#include <zephyr/sys/util_macro.h>
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#include <zephyr/types.h>
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#include <Siul2_Port_Ip.h>
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/** @cond INTERNAL_HIDDEN */
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/**
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* @brief NXP S32 common macros for Pinctrl.
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*
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* Each SoC implementing Pinctrl must create a "pinctrl_soc.h" which includes
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* this file and defines the following macros:
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*
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* - NXP_S32_PIN_OPTIONS_INIT(group, mux)
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* Populates SoC members of Siul2_Port_Ip_PinSettingsConfig struct based on
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* SoC-specific group properties and the pinmux configuration.
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*
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* - NXP_S32_SIUL2_IDX(n)
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* Expands to the SIUL2 struct pointer for the instance "n". The number of
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* instances is SoC specific and may be not contiguous.
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* Note: "n" may be a preprocessor expression so cannot be concatenated.
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*/
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/** @brief Type for NXP S32 pin configuration. */
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typedef Siul2_Port_Ip_PinSettingsConfig pinctrl_soc_pin_t;
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#define NXP_S32_INPUT_BUFFER(group) \
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COND_CODE_1(DT_PROP(group, input_enable), (PORT_INPUT_BUFFER_ENABLED), \
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(PORT_INPUT_BUFFER_DISABLED))
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#define NXP_S32_OUTPUT_BUFFER(group) \
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COND_CODE_1(DT_PROP(group, output_enable), (PORT_OUTPUT_BUFFER_ENABLED),\
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(PORT_OUTPUT_BUFFER_DISABLED))
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#define NXP_S32_INPUT_MUX_REG(group, val) \
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COND_CODE_1(DT_PROP(group, input_enable), (NXP_S32_PINMUX_GET_IMCR_IDX(val)), \
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(0U))
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#define NXP_S32_INPUT_MUX(group, val) \
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COND_CODE_1(DT_PROP(group, input_enable), \
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((Siul2_Port_Ip_PortInputMux)NXP_S32_PINMUX_GET_IMCR_SSS(val)), \
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(PORT_INPUT_MUX_NO_INIT))
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/* Only a single input mux is configured, the rest is not used */
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#define NXP_S32_INPUT_MUX_NO_INIT \
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[1 ... (FEATURE_SIUL2_MAX_NUMBER_OF_INPUT-1)] = PORT_INPUT_MUX_NO_INIT
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#define NXP_S32_PINMUX_INIT(group, val) \
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.base = NXP_S32_SIUL2_IDX(NXP_S32_PINMUX_GET_SIUL2_IDX(val)), \
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.pinPortIdx = NXP_S32_PINMUX_GET_MSCR_IDX(val), \
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.mux = (Siul2_Port_Ip_PortMux)NXP_S32_PINMUX_GET_MSCR_SSS(val), \
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.inputMux = { \
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NXP_S32_INPUT_MUX(group, val), \
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NXP_S32_INPUT_MUX_NO_INIT \
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}, \
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.inputMuxReg = { \
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NXP_S32_INPUT_MUX_REG(group, val) \
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}, \
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.inputBuffer = NXP_S32_INPUT_BUFFER(group), \
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.outputBuffer = NXP_S32_OUTPUT_BUFFER(group),
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/**
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* @brief Utility macro to initialize each pin.
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*
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*
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* @param group Group node identifier.
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* @param prop Property name.
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* @param idx Property entry index.
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*/
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#define Z_PINCTRL_STATE_PIN_INIT(group, prop, idx) \
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{ \
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NXP_S32_PINMUX_INIT(group, DT_PROP_BY_IDX(group, prop, idx)) \
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NXP_S32_PIN_OPTIONS_INIT(group, DT_PROP_BY_IDX(group, prop, idx)) \
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},
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/**
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* @brief Utility macro to initialize state pins contained in a given property.
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*
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* @param node_id Node identifier.
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* @param prop Property name describing state pins.
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*/
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
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DT_FOREACH_PROP_ELEM, pinmux, \
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Z_PINCTRL_STATE_PIN_INIT)}
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/** @endcond */
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#endif /* ZEPHYR_SOC_ARM_NXP_NXP_S32_COMMON_PINCTRL_SOC_COMMON_H_ */
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@ -1,52 +0,0 @@
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/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_ARM_NXP_S32_S32ZE_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_ARM_NXP_S32_S32ZE_PINCTRL_SOC_H_
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#include "pinctrl_soc_common.h"
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#if defined(CONFIG_SOC_S32Z27_R52)
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#include "S32Z2_SIUL2.h"
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#else
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#error "SoC not supported"
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#endif
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#define NXP_S32_SIUL2_IDX(n) \
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n == 0 ? IP_SIUL2_0 : (n == 1 ? IP_SIUL2_1 : ( \
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n == 3 ? IP_SIUL2_3 : (n == 4 ? IP_SIUL2_4 : ( \
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n == 5 ? IP_SIUL2_5 : (NULL)))))
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#define NXP_S32_PULL_SEL(group) \
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COND_CODE_1(DT_PROP(group, bias_pull_up), (PORT_INTERNAL_PULL_UP_ENABLED), \
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(COND_CODE_1(DT_PROP(group, bias_pull_down), \
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(PORT_INTERNAL_PULL_DOWN_ENABLED), (PORT_INTERNAL_PULL_NOT_ENABLED))))
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/* To enable open drain both OBE and ODE bits need to be set */
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#define NXP_S32_OPEN_DRAIN(group) \
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DT_PROP(group, drive_open_drain) && DT_PROP(group, output_enable) ? \
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(PORT_OPEN_DRAIN_ENABLED) : (PORT_OPEN_DRAIN_DISABLED)
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#define NXP_S32_SLEW_RATE(group) \
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COND_CODE_1(DT_NODE_HAS_PROP(group, slew_rate), \
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(UTIL_CAT(PORT_SLEW_RATE_CONTROL, DT_PROP(group, slew_rate))), \
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(PORT_SLEW_RATE_CONTROL0))
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/*
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* The default values are reset values and don't apply to the type of pads
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* currently supported.
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*/
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#define NXP_S32_PIN_OPTIONS_INIT(group, mux) \
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.pullConfig = NXP_S32_PULL_SEL(group), \
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.openDrain = NXP_S32_OPEN_DRAIN(group), \
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.slewRateCtrlSel = NXP_S32_SLEW_RATE(group), \
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.terminationResistor = PORT_TERMINATION_RESISTOR_DISABLED, \
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.receiverSel = PORT_RECEIVER_ENABLE_SINGLE_ENDED, \
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.currentReferenceControl = PORT_CURRENT_REFERENCE_CONTROL_DISABLED, \
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.rxCurrentBoost = PORT_RX_CURRENT_BOOST_DISABLED, \
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.safeMode = PORT_SAFE_MODE_DISABLED,
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#endif /* ZEPHYR_SOC_ARM_NXP_S32_S32ZE_PINCTRL_SOC_H_ */
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