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soc: arm: nxp_s32: s32k1: unselect CPU_HAS_xCACHE

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Following changes in #64978, align CPU_HAS_xCACHE symbols with
the CMSIS feature definitions in the device headers so that
both have the same value.

Fixes #66147

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles 2023-12-05 18:07:27 +07:00 • committed by Henrik Brix Andersen
commit 673f38f3d1
1 changed files with 0 additions and 12 deletions
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12
soc/arm/nxp_s32/s32k1/Kconfig.soc
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@ -20,48 +20,36 @@ config SOC_S32K142
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
config SOC_S32K142W
bool "S32K142W"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
config SOC_S32K144
bool "S32K144"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
config SOC_S32K144W
bool "S32K144W"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
config SOC_S32K146
bool "S32K146"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
config SOC_S32K148
bool "S32K148"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
endchoice