soc: arm: Add support for Ambiq Apollo4 Blue Plus.
Added devicetree and Kconfig for Apollo4 Blue Plus SoC. They are needed for the apollo4p_blue_kxr_evb board. Signed-off-by: Aaron Ye <aye@ambiq.com>
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122
dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
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122
dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
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/* SPDX-License-Identifier: Apache-2.0 */
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#include <arm/armv7-m.dtsi>
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#include <mem.h>
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/ {
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clocks {
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uartclk: apb-pclk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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/* MRAM region */
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flash0: flash@18000 {
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compatible = "soc-nv-flash";
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reg = <0x00018000 0x1e8000>;
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};
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/* TCM */
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tcm: tcm@10000000 {
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compatible = "zephyr,memory-region";
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reg = <0x10000000 0x10000>;
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zephyr,memory-region = "ITCM";
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};
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/* SRAM */
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sram0: memory@10010000 {
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compatible = "mmio-sram";
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reg = <0x10010000 0x2B0000>;
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};
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soc {
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pwrcfg: pwrcfg@40021000 {
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compatible = "ambiq,pwrctrl";
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reg = <0x40021000 0x400>;
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#pwrcfg-cells = <2>;
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};
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stimer0: stimer@40008800 {
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compatible = "ambiq,stimer";
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reg = <0x40008800 0x80>;
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interrupts = <32 0>;
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status = "okay";
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};
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counter0: counter@40008000 {
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compatible = "ambiq,counter";
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reg = <0x40008000 0x80>;
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interrupts = <67 0>;
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status = "disabled";
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};
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uart0: uart@4001c000 {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <0x4001c000 0x1000>;
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interrupts = <15 0>;
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interrupt-names = "UART0";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
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};
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uart1: uart@4001d000 {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <0x4001d000 0x1000>;
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interrupts = <16 0>;
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interrupt-names = "UART1";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
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};
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uart2: uart@4001e000 {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <0x4001e000 0x1000>;
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interrupts = <17 0>;
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interrupt-names = "UART2";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
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};
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uart3: uart@4001f000 {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <0x4001f000 0x1000>;
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interrupts = <18 0>;
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interrupt-names = "UART3";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
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};
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pinctrl: pin-controller@40010000 {
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compatible = "ambiq,apollo4-pinctrl";
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reg = <0x40010000 0x800>;
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};
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wdt0: watchdog@40024000 {
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compatible = "ambiq,watchdog";
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reg = <0x40024000 0x400>;
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interrupts = <1 0>;
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clock-frequency = <16>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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18
soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue
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soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue
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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
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if SOC_APOLLO4P_BLUE
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config NUM_IRQS
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default 83
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DT_NODE_SRAM := /memory@0
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config SRAM_NC_SIZE
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default $(dt_node_reg_size_int,$(DT_NODE_SRAM),1,K)
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config SRAM_NC_BASE_ADDRESS
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default $(dt_node_reg_addr_hex,$(DT_NODE_SRAM),1)
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endif # SOC_APOLLO4P_BLUE
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
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choice
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prompt "Ambiq Apollo4X Selection"
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@ -9,4 +10,7 @@ choice
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config SOC_APOLLO4P
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bool "Apollo4P"
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config SOC_APOLLO4P_BLUE
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bool "Apollo4 Blue Plus"
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endchoice
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