soc: nxp_s32: enable RTU.PIT timers for S32ZE
Each RTU includes one PIT instance that can be used by any of the cores. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
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4 changed files with 21 additions and 1 deletions
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@ -83,5 +83,14 @@
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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pit0: pit@76150000 {
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compatible = "nxp,kinetis-pit";
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reg = <0x76150000 0x10000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_P0_REG_INTF_CLK>;
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max-load-value = <0x00ffffff>;
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status = "disabled";
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};
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};
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};
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@ -83,5 +83,14 @@
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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pit0: pit@76950000 {
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compatible = "nxp,kinetis-pit";
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reg = <0x76950000 0x10000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_P1_REG_INTF_CLK>;
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max-load-value = <0x00ffffff>;
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status = "disabled";
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};
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};
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};
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@ -15,5 +15,7 @@ config SOC_SERIES_S32ZE_R52
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select PLATFORM_SPECIFIC_INIT
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select SOC_FAMILY_NXP_S32
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select CLOCK_CONTROL
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select HAS_MCUX
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select HAS_MCUX_PIT
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help
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Enable support for NXP S32Z/E MCUs family on Cortex-R52 cores.
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2
west.yml
2
west.yml
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@ -199,7 +199,7 @@ manifest:
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groups:
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- hal
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- name: hal_nxp
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revision: 6d91c1727dadb170facc48f5370358a12ae36677
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revision: b4a37865355a6d55cdcdc087b934017212fb0f54
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path: modules/hal/nxp
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groups:
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- hal
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