soc: lpc55xxx: Fix system hw clock cycle rate
Commit c6e3bac4f
changed the core clock frequency of LPC55XXX series.
That clock is used by the cortex-m systick timer, which is the
default timer used for system time in zephyr on this series.
The bug is that the config SYS_CLOCK_HW_CYCLES_PER_SEC default was not
updated on the affected platforms to account for this change, so system
time is currently recorded as 150% of reality. Fix this by changing the
kconfig to be set automatically at SOC level and remove board defaults.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
parent
3fde2d3073
commit
4d654250a5
8 changed files with 4 additions and 7 deletions
|
@ -13,7 +13,6 @@ CONFIG_SERIAL=y
|
|||
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||
CONFIG_GPIO=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
CONFIG_RUNTIME_NMI=y
|
||||
|
|
|
@ -13,7 +13,6 @@ CONFIG_SERIAL=y
|
|||
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||
CONFIG_GPIO=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
CONFIG_RUNTIME_NMI=y
|
||||
|
|
|
@ -13,7 +13,6 @@ CONFIG_SERIAL=y
|
|||
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||
CONFIG_GPIO=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
|
||||
CONFIG_ARM_MPU=y
|
||||
CONFIG_HW_STACK_PROTECTION=y
|
||||
|
||||
|
|
|
@ -13,7 +13,6 @@ CONFIG_SERIAL=y
|
|||
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||
CONFIG_GPIO=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
CONFIG_RUNTIME_NMI=y
|
||||
|
|
|
@ -12,7 +12,6 @@ CONFIG_UART_CONSOLE=y
|
|||
CONFIG_SERIAL=y
|
||||
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||
CONFIG_GPIO=y
|
||||
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
|
||||
CONFIG_ARM_MPU=y
|
||||
CONFIG_HW_STACK_PROTECTION=y
|
||||
CONFIG_PINCTRL=y
|
||||
|
|
|
@ -8,7 +8,6 @@ CONFIG_SOC_SERIES_LPC55XXX=y
|
|||
CONFIG_SOC_LPC55S69_CPU1=y
|
||||
CONFIG_BOARD_LPCXPRESSO55S69_CPU1=y
|
||||
CONFIG_GPIO=y
|
||||
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
|
||||
CONFIG_PINCTRL=y
|
||||
|
||||
CONFIG_RUNTIME_NMI=y
|
||||
|
|
|
@ -12,7 +12,6 @@ CONFIG_UART_CONSOLE=y
|
|||
CONFIG_SERIAL=y
|
||||
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||
CONFIG_GPIO=y
|
||||
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
|
||||
CONFIG_PINCTRL=y
|
||||
|
||||
# TFM sets up MPU_NS, can't correctly change this configuration yet
|
||||
|
|
|
@ -130,6 +130,10 @@ config INIT_PLL1
|
|||
Note that flash programming operations are limited to 100MHz, and
|
||||
this PLL should not be used as the core clock in those cases.
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 144000000 if INIT_PLL1
|
||||
default 96000000
|
||||
|
||||
config SECOND_CORE_MCUX
|
||||
bool "LPC55xxx's second core"
|
||||
depends on HAS_MCUX
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue