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ITE: drivers/i2c/target: Disable the timeout setting

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Disable the timeout setting when both the clock and data are
in a low state. This allows for I2C host clock stretching
without a timeout limit.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2023-08-02 16:58:01 +08:00 • committed by Carles Cufí
commit 3ae9a358fb
2 changed files with 6 additions and 5 deletions
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8
drivers/i2c/i2c_ite_enhance.c
View file

@ -1222,11 +1222,9 @@ static int i2c_enhance_target_register(const struct device *dev,
/* Software reset */
IT8XXX2_I2C_DHTR(base) |= IT8XXX2_I2C_SOFT_RST;
IT8XXX2_I2C_DHTR(base) &= ~IT8XXX2_I2C_SOFT_RST;
/*
* Set time out register.
* I2C D/E/F clock/data low timeout.
*/
IT8XXX2_I2C_TOR(base) = I2C_CLK_LOW_TIMEOUT;
/* Disable the timeout setting when clock/data are in a low state */
IT8XXX2_I2C_TO_ARB_ST(base) &= ~(IT8XXX2_I2C_SCL_TIMEOUT_EN |
IT8XXX2_I2C_SDA_TIMEOUT_EN);
/* Bit stretching */
IT8XXX2_I2C_TOS(base) |= IT8XXX2_I2C_CLK_STRETCH;
/* Peripheral address(8-bit) */

3
soc/riscv/riscv-ite/common/chip_chipregs.h
View file

@ -1347,6 +1347,9 @@ enum chip_pll_mode {
/* 0x13: Nack Status */
#define IT8XXX2_I2C_NST_CNS BIT(7)
#define IT8XXX2_I2C_NST_ID_NACK BIT(3)
/* 0x18: Timeout and Arbiter Status */
#define IT8XXX2_I2C_SCL_TIMEOUT_EN BIT(7)
#define IT8XXX2_I2C_SDA_TIMEOUT_EN BIT(6)
/* 0x19: Error Status */
#define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ BIT(0)
/* 0x1B: Finish Status */