* there is a subtle difference to the stm32h74x
* c.f. rm0468 (stm32h723/733 stm32h725/735 and stm32h730)
* verified on stm32h735
Signed-off-by: Roland Lezuo <roland.lezuo@embedded-solutions.at>
Align driver with changes introduced in the hal. `nrf_timer_frequency_set`
was changed to `nrf_timer_prescaler_set`, update driver accordingly.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
New Zephyr WDT driver for TI CC13xx/CC26xx family.
Supports interrupts & MCU soft reset on timeout.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
Each GPIO controller may contain GPIO hog definitions. GPIO hogging is a
mechanism for providing automatic GPIO configuration during system
initialization.
Each GPIO hog is represented as a child node of the GPIO controller.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
changes to support low power and wake support in microchip xec uart
driver. Add support for wakerx_gpio config in dts to select the wake gpio.
Configure for wake in PM_DEVICE_ACTION_SUSPEND state and clear
interrupt in wake isr. Also added support for
CONFIG_UART_CONSOLE_INPUT_EXPIRED
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
assign interrupt number 0 for jtag_uart.
Number can be found in soc/nios2/nios2-qemu/include/system.h
JTAG_UART_0_IRQ 0
Signed-off-by: Goh Shun Jing <shun.jing.goh@intel.com>
This board is confirmed to build and run simple applications in
RTL simulation as described in the included board documentation.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
According to the reference manual, all STM32G4 variants except
STM32G431/STM32G441 have the UART5 peripheral.
Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
Boolean properties for STM32 ADC internal channels are not used anymore
and can be removed. It is replaced by channel number properties.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In all STM32 dts, remove all reference to the following properties:
- has-temp-channel
- has-vref-channel
- has-vbat-channel
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that we have a binding to define the channel number for temperature
and Vref measurement, update all dtsi to include the information.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add some bindings to define STM32 ADC internal channels for:
- Temperature
- Vref
- Vbat
The goal is to transfer information to the dts instead of inside the
ADC driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Bugfix for the Cyclone V SoC DK ethernet driver need to add emac-index
in dts
- We remove the "local-mac-address" property from
dts/arm/intel_socfpga_std.dtsi to
boards/arm/cyclonev_socdk/cyclonev_socdk.dts, since this value is
dependant on the board / implementation and not universal to
the "intel_socfpga" package that it inherets from.
- The above is also true for the "status" property as the board
should enable the device.
Signed-off-by: Benjamin Kyd <benjamin.kyd@intel.com>
Add three xbar nodes and four qdec nodes in the rt10xx devicetree include.
Add xbara to rt1052 in Kconfig.soc
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add a driver for the NXP MCUX Quadrature Decoder. The driver
is simple and only implements the phase a and phase b inputs. The
module has additional features which can be added in future PRs.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Change the name of the custom macro defined for the stm32 devices
to fit the VND_PWM_xxx model
Keeping old deprecated macro, though.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce DT nodes for NETC complex and enable its usage for
s32z270dc2_r52 boards. Using PSI0 as default networking interface and
Switch Port0 as it's the only port available on this board.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce Ethernet low-level driver for NXP S32 Network Controller
(NETC). Current driver allows to manage from Zephyr a Physical Station
Interface (SI) and/or a Virtual SI. The NETC has an integrated Ethernet
Switch. Currently the Switch is initialized from this driver with a
default configuration, and all ports are enabled and transparent for
the user. A separate Switch driver should be addressed in future patches.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce NXP S32 NETC External MDIO controller driver. Driver supports
a single instance, as current support is based on NXP S32Z/E SoCs.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce NXP S32 Message Receive Unit (MRU) driver based
of Mbox API. The MRU couples with a processor and allows to
receive messages from senders, which are other modules or
processors.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
On STM32L4 that probvide HSI48 clock, use it as 48MHz domain clock.
This impacts following devices:
-SDMMC
-RNG
-USB
Otherwise, when HSI48 is not available MSI is used.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STMF412 and STM32F413 did not support CAN bus in Zephyr yet.
This adds the device tree entries to be able to use all 2, resp.
3 CAN controllers.
Signed-off-by: Tom Stirnkorb <tom@stirnkorb.me>
Remove the vref-mv = <3300>; property for all the ADC node of
the stm32 devices as it is set by default to 3300mV by the
dts/adc/st,stm32-adc.yaml
(Except for the stm32f303 vref is 3000mV)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Configure RNG domain clock and align it on USB (as this is the same clk).
This is not stricly required, as this configuration matches default
reset but its more consistent this way.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove SDMMC from f410 soc variant since it's not actually available.
Do this in package variant as F410 is included by f412 who has a SDMMC.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provide SDMMC domain clock, when required (because it is common)use
the same as the one selected by USB and RNG.
Otherwise, when available use HSI48, otherwise use the most handy (MSI,
sysclk ...).
PLLSAI is not used as not implemented for now.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add 2 properties in STM32 external interrupt controller:
- num-lines
- line-ranges
Additionally, make interrupt-names a required property.
The properties will help to simplify exti init code in building the
exti_irq_table and simplify the isr related bits.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Intel DSP Communication Widget is a device for generic sideband
message transmit/receive between IPs in a SOC.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Align RNG domain clock confguration on USB clock configuration.
For now we're not able to fully use CLK48 as a mux clock, so
this has to be done on both nodes rather than on a centralized
fashion.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The interrupt is used to wake up EC from low power mode.
So EC does not defer eSPI bus while transaction is accepted.
Fixes EC host commands slow issue.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit makes the peripheral-id property optional and removes it's
usage from the Gecko SPI driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
ALH dts definitions need to have 16 nodes, thus add them to supported
platforms (cavs25 and ace15).
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This sets the RNG node that will be used by the Nordic
devices which support TF-M (nRF5340/nRF9160) to use the
defined scheme with psa_generate_random.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
The documentation for the fixed-partitions binding is missing critical
information and is vague in other important respects. This is an
important binding that deserves to be crystal clear. Fix it.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Describe USB default domain clock on all USB devices.
When available select HSI48.
On some series, a default clock my be set by default at start up.
On those series, in order to be able to compute USB clock at runtime,
clock_control driver needs to be aware of configuration and then this
default config has to be described explicitly too.
Default clocks are not enabled though. It is up to board configuration
to provide correct clock configuration (and we should not enabled by
default clocks that would not be required by board configuration).
Note: This change doesn't consider STM32F1/F3 devices, which
have a specific USB clock configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add kscan pins gpio driver for KSI[7:0], KSO[15:0] pins that
they can be configured to gpio mode. These pins registers address,
bit fields and function are different from GPIO group, so I create
a new compatible driver for these pins.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
- Adds the declaration of the MMC API
- Adds MMC spec related declarations
- Adds some properties to sdhc dts binding for mmc
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The names of these peripherals in the device tree
did not match the Reference Manual for the RT500.
Also fixed a typo in a comment referring to USDHC which should have been
about USB.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Adds the pin controls and ushdc settings in device tree
- Attaches clock to USDHC in soc.c
- Adds binding for mmc
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
While nPM1100 is to be operated in fixed configuration for some
applications, it has some degree of configuration via GPIOs. For
example, mode (auto/PWM) can be configured via MODE pin. VBUS current
can also be adjusted using ISET pin, even though there is no API yet to
limit the PMIC input current.
This patch adds a new regulator class driver for nPM1100 PMIC, so that
it can be used with the standard regulator API when needed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In file stm32l412.dtsi, spi2 was missing fifo compatibility,
this way failing to initialise fifo threshold correctly
when spi data width is configured.
Signed-off-by: Mirko Bottarelli <mirko.bottarelli@gmail.com>
Add rng definition to f410.
Though, don't inherit directly in f412 as it's integrated
in a different way.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to ease description of DCKCFG regsiters,
make f412 a variant of f410 as it supposed to be.
Only exception is missing DAC1.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The interrupt and watchdog registers of the it82xx2 will be
remapped, so these device nodes should be separated to
it81xx2 from it8xxx2. it8xxx2 dtsi are common settings
for it81xx2 and it82xx2.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit adds the support for host commands being transported
by the Serial Host Interface on the IT8xxx2 SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
This commit adds the support for host commands being transported
by the Serial Host Interface on the NPCX SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Adds a driver for TDK InvenSense 42688 six axis IMU. Verified using
the sensor shell sample app via:
- sensor info
- sensor get icm42688p@0
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Signed-off-by: Yuval Peress <peress@google.com>
Add the st,static-prescaler DTS property to the
stm32u5 family on the LPTIM1.
Also present on lptim3, 4 but not defined yet.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a st,static-prescaler optional property to DTS
of the stm32 where the LPTIM has a x2 factor on
its clock input.
This property is present or not depending on the stm32.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Drop compatible from fuel-gauge.yaml, it's not needed since this binding
is not meant to be used directly, and is also incorrect as it includes
the "yaml" suffix.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The GCR, PINCTRL, I2C and WUC registers of the it82xx2 will be remapped,
so these device nodes will not be in the it8xxx2.dtsi, these should be
separated to create a it81xx2.dtsi.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Purpose of this node is only to provide a way to configure RF
clock using device tree and clock_control driver.
Default configuration is reproducing existing hard-coded configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add missing interrupts property for second FlexSPI device on RT5xx.
This interrupt is shared between both FlexSPI devices, but the memc
driver does not use interrupts so no conflict should arise.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce driver for APS6408L PSRAM, built on top of the MCUX memc
driver for flexSPI. This driver supports operating the PSRAM in high
speed mode (200MHz or more). Note that in order to support this
PSRAM's alignment requirements, either ahb-read-addr-opt or
ahb-prefetch must be set for the FlexSPI instance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rename flexspi-hyperram driver to flexspi-s27ks0641, and update
function names. This driver is only capable of supporting the
s27ks0641 HyperRAM chip, as the lookup table given in this driver
is specific to the s27ks0641.
Rename the flexspi-hyperram binding to reflect this, to
prevent confusion from users.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix all line-length errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(line-length)'
Using a limit is set to 100 columns, not touching the commandlines in
GitHub workflows (at least for now).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix all comments-indentation errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(comments-indentation)'
This checks that the comment is aligned with the content.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix all hyphens errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(comments)'
Default config would be to require two spaces after the start of the
comment, proposing to keep it on 1, inline with the Linux binding
config, that is:
```
- comments:
- min-spaces-from-content: 1
```
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix all hyphens errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(hyphens)'
Default config is only one space after the hyphen.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix all brackets errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(brackets)'
Default config is to have no spaces inside brackets, changed few
documentation strings as well that refered to lists even though the
linter does not care about those.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The addresses of the flash and flash controller of the RP2040
SoC were mixed up. There was no clear distinction between the
flash and the flash controller, which was unclear but also
caused a DTC warning.
This commit makes the distinction clearer: The SSI peripheral at
0x18000000 is the flash controller, and the flash itself starts
at 0x10000000. The flash driver and rpi_pico.dts were fixed
accordingly.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
The pinctrl node of the RP2040 had the same unit address as the GPIO
bank, causing a DTC warning. To fix this, the pinctrl's address was
removed, as it does not require any.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Remove the test clock out Kconfig from SoC level. Instead use
device tree PINCTRL entry with updated clock control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x. MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add initial support for gd32l23x series. gd32l23x used Cortex-M23, based
on ARMv8-M baseline, implement the System Timer.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
Enable RTU.SWT (Real-Time Unit.Software Watchdog Timer) instances on
s32z270dc2_r52 boards. Module clock frequency is fixed to 48 Mhz.
Signed-off-by: Quang Bui Trong <quang.buitrong@nxp.com>
Add missing I2C clock sources for STM32F303 & F373.
Add a comment for all STM32F3 I2Cx and for STM32F0 I2C1 that the clock
source should always be defined.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add config cell property to gd,gd32-dma.
For supporting hardware variation, Splitting base definition
to gd,gd32-dma-base.yaml.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Define SYSCLK as the default I2C source clock for I2C1 on STM32F0x
and all I2Cx on STM32F3x.
On most series, the default I2C clock source (when it exists) is PCLK.
This clock does not exist as I2C clock source on FO & F3 and the default
one is HSI. Since HSI is not necessarily enabled we explicitly set it
to SYSCLK instead.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Include the new clock file dedicated for STM32F7 instead of the F4 one
previously used.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
peripheral-id property should be eventually removed.
For now set it as optional and allow skipping the usage
in UART driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
peripheral-id property should be eventually removed entirely.
For now set it as optional and allow skipping the usage
in GPIO driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
HAL update affects also EFR32MG21 SoC. Because of that we need to
update the reg addresses in DTS.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
This commit adds support for Silicon Labs EFR32BG22 SoC.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds initial support for Silabs Real-Time counter
Co-authored-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
This commit adds a series of driver-related changes to
Gecko pinctrl.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds initial support for gecko pinctrl driver
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The ADC module has four conversion groups, each one is set up as a zephyr
device. The start-up calibration is initiated globally for all groups
and it is run in each device init function. The ADC module supports post
calibration per group. Post calibration is run automatically after each
group acquires the samples.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add virtual memory entry in dt to use as virtual space
regions for aplication.
Add virtual memory definition in adsp_memory.h
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
Add FFF-based fake regulator driver. This driver can be used as a stub
or mock in testing.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
These inherited properties from Linux bindings are not supported yet.
The reason for the removal is because regulator-couple-with requires
definition of #cells spec, unless bindings explicitely ban the property
or use allowlist.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add i.MX93 Cortex-A Core support on Zephyr.
i.MX 93 applications processors deliver efficient machine learning
(ML) acceleration and advanced security with integrated EdgeLock
secure enclave to support energy-efficient edge computing.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Adds two additional alh2 and alh3 "devices" to already defined
alh0 and alh1. This (seems) is a temporarily solution as
the hardware actually supports 16 streams and future update
to device tree is required.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Add support for virtual USB host controller intended for use
together with virtual bus and virtual device controllers.
This driver is not an emulation of any real host controller.
The driver has initial support for handling control and bulk
transfers.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add support for virtual USB device controller intended for use
by virtual bus and virtual UHC controllers. This driver is not
an emulation of any real host controller.
The driver has initial support for handling control and bulk
transfers.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add common layer of UHC API and MAX3421E host controller driver.
This implements the bare minimum necessary to communicate with
one peripheral device.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Assigning power domain to the GP DMA.
NOTE: Only controllers 1 and 2 are under IO_0 domain, controller 0 is
under HUB-ULP domain.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Support for the measuring the CPU die temperature
for the ESP32 targets S2,C3. The ESP32 support
was ommited due to lack of offset calibration.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Serial speeds listed in device tree did not reflect
what driver supports.
2M and 500K were missing while
1200, 2400 and 460800 were present while not supported.
This change synchronized dts with driver code:
drivers/serial/uart_smartbond.c
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
PCA9420 PMIC offers of multiple operation states, or DVS (Dynamic
Voltage Scaling). Such states may be automatically changed by hardware
using MODESEL0/1 pins. Certain MCUs allow to automatically configure
certain output pins when entering low power modes so that PMIC state is
changed without software intervention. This means that application just
needs to configure the voltages for each state using
`nxp,modeN-microvolt`, set `nxp,enable-modesel-pins` in devicetree and
forget about configuring regulators.
This patch introduces a new _parent_ API to expose such functionality in
a vendor agnostic way. Consider this API as experimental for now, until
we have other usecases.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Most of devicetree properties for regulator, such as:
- regulator-min/max-microvolt
- regulator-min/max-microamp
- regulator-allowed-modes
- etc.
Are meant to specify limits on what consumers may set. They are **NOT**
meant to describe the hardware capabilities. For example, I could have a
BUCK converter that supports 0-5V output voltage, but my circuit may
only allow working on the 2.7-3.3V range.
This patch reworks the API so that the API class layer manages this
information. This is done by drivers collecting all such fields in a
common configuration structure that is later accessed by the class
layer. This simplifies drivers implementation. For example, if A
consumer calls regulator_set_voltage() with a voltage that is supported
but not allowed, driver code won't be called. Similarly, if a regulator
is configured to be `always-on`, enable/disable driver code will never
be called.
Drivers have been adjusted. PCA9420 mode settings have been removed from
devicetree in this commit as they are not actual modes but PMIC states.
This will be refactored in a follow-up commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The stm32G0 device has a one APB peripheral clock bus
but splitted on two RCC registers: RCC_ABPENR1 and RCC_ABPENR2
Peripherals are on one or the other.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The XY Memory is a feature commonly found in DSP processors to increase
the DSP performance. The XY component allows a ARC processor to
implicitly load source operands and store results into a closely coupled
memory using a single instruction.
Add XY memory for ARC EM9D/EM11D processors including em_starterkit,
em_starterkit_em11d. emsdp_em9d, nsim_em, iotdk.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.
This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.
The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The interrupt-map property specifies both 32-bits values and a phandle;
update the type accordingly.
Update the definition of pcie-host-ecam-generic on qemu arm64 to match
the new type.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Add DTS information for qemu-virt-a53 and qemu-kvm-arm64 for PCIe
controller support. Three new bindings are required for the PCIe
controller in ECAM mode.
The DTS information was extracted from QEMU (dumpdtb) with a PCIe device
attached to the virtual machine (ivshmem)
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
We are about to add UART reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
We are about to add timer reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
To deassert reset in STM32MP1 RCC the driver needs to set the bit in
reset clear register.
This patch extends existing implementation to support this type of
register.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This driver exposes STM32 RCC reset functionality through reset API.
Information about RCC register offset and bit is encoded just like GD32.
The first 5 least significant bits contains register bit number.
Next 12 bits are used to keep RCC register offset. Remaining bits are
unused.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
STM32L4 devices, except STM32L412 STM32L422 STM32L4P5 STM32L4Q5, have
32 4-byte battery-backed RTC backup registers. Other STM32L4 devices
have backup registers in tamper module, not used in Zephyr.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All STM32L1 devices have 4-byte battery-backed RTC registers, but
they have different number of registers:
STM32L151Xb-a has 5 registers.
STM32L151Xb has 20 registers.
STM32L151Xc, STM32L152Xc, STM32L152Xe have 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add BBRAM entry for all STM32H7 microcontrollers except STM32H7A3 and
STM32H7B3 which have backup registers in tamper module.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All supported STM32F3 devices have 4-byte battery-backed RTC registers,
but they have different number of registers:
STM32F303x8 and STM32F334 have 5 registers.
STM32F303xc and STM32F303xe have 16 registers.
STM32F302x8 has 20 registers.
STM32F373 has 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Among supported devices only STM32F031, STM32F051, STM32F072 and
STM32f09x have 5 4-byte battery-backed RTC registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
STM32 battery-backed RAM is organized in 4 byte registers. Number of
registers can vary between models from 5 to 32 registers.
Usually, the registers are part of RTC. On some variants they are part
of tamper module. On STM32F1 the registers are in separate module. For
now, only backup registers from RTC are supported.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add definitions for DMAs, Digital Audio Interfaces (DAIs) and
the necessary clocks to enable full use of audio peripherals
in the intel_adsp_cavs25_tgph boards.
Link: https://github.com/thesofproject/sof/issues/6710
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
NXP LPUART IP supports rs485 mode when transceiver driver enable
using RTS. Allow setting rs485 mode up via the "nxp,rs485-mode"
dts property. "nxp,rs485-de-active-low" dts property can be used
for set RTS polarity.
Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
Add the HSI48 clock to the stm32 devices that have this
clock signal.
Within a stm32 family, only few might have the
RCC_HSI48_SUPPORT.
STM32WB has a CLK48 mux.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add zephyr,memory-region compatible and attribute to SOC memory regions,
so that sections will be generated and MPU attributes can be applied.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT1170 and RT1160 CM7 and CM4 cores have the same set of differences.
Merge the DTS files for both CM4 and CM7 cores, to create generic
rt11xx_cm4 and rt11xx_cm7 files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
- Similar to what was done for other parts of the driver, remove any
register specification from Devicetree (modesel-reg/mask)
- Keep all the information in the driver, and define modes as "numbers",
e.g. PCA9420_MODE0: 0, PCA9420_MODE1: 1, etc.
- Bindings provide IC defaults now (all modes allowed 0/1/2/3 and
initial mode set to 0).
- When mode is controlled via the MODESEL0/1 pins (ie directly by an iMX
MCU using the dedicated PMIC_MODE0/1 pins), the driver will not allow
to select a mode (it is not possible). This mode is now enabled by
setting `nxp,enable-modesel-pins` in Devicetree. When enabled, all the
allowed modes are configured to be selectable via pins. When disabled,
mode can be set via I2C (using TOP_CNTL3 MODE0/1_I2C fields)
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add system reset control device (sysrst), so that the drivers can
assert/deassert its reset line through the public reset controller
driver API.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Add bindings for Aspeed AST10x0 reset driver. The reset line can be
de-asserted or asserted through the syscon registers.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Add RX and TX fifo size properties to CDC ACM UART bindings.
This allows per instance settings in contrast to Kconfig
USB_CDC_ACM_RINGBUF_SIZE option. New properties takes the default
size value of USB_CDC_ACM_RINGBUF_SIZE which can be removed
subsequently.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add rgb-is-inverted option to indicate module's pixel-format is
inverting from MADCTL settings of ST7735R controller.
This option intends to implement a workaround for LCD modules
that is the actual screen color was different (inverted)
from the RGB setting in MADCTL property.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Implement a LED driver for Microchip XEC using the breathing,
blinking LED controller. The driver supports LED on, off, and
blink API's. The BBLED block uses the 32768 Hz clock domain
allowing the module to operate in light and deep sleep states.
Blink frequency is 32768 divided by 256 * (prescale + 1) where
prescale is a 12-bit value. Duty cycle is specified by an 8-bit
value where 0 = full off, 127 is 50%, and 255 is full on.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add new variant configuration of it81202cx and it81302cx.
This cx variant of it81xx2 changes are as follows:
1. SRAM size will increase from 60k to 128k.
2. Configurable ILM size is still 60k.
3. Support M extension of RISC-V.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Re-enable the CAAM for entropy
now that the HAL driver has been fixed
Job descriptors must be accessed coherently
between CAAM DMA and core.
The M4 Cores still do not work
because of mpu/cache/kconfig arch complications,
disable caam for M4 cores in DTS
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Remove regulator-fixed-sync specialization, create a single driver that
is always synchronous. The asynchronous part is rarely/never used, so
let's keep things simple for now.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable RTU System Timer Module (STM) instances on
s32z270dc2_r52 boards. Module clock frequency is fixed to
133.333333 MHz.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
NXP S32 System Timer module includes a 32-bit count-up timer and four
32-bit compare channels with a separate interrupt source for each
channel. The timer is driven by the module clock divided by an 8-bit
prescale value.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Microchip XEC GPIO pins support inverting the output of
alternate pin functions. This feature may be useful for
those peripherals that do not implement output inversion
in the peripheral. GPIO control register pad input and
parallel input register values are not affected by the
function output invert feature. GPIO interrupt detection
of an output is inverted if the invert polarity is enabled.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
add Intel HDA DAI driver
Long device list in dtsi needs to be refactored in the future
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
The driver had a conceptual issue regarding current limitation. PCA9420
is able to limit the current flowing through VIN, ie input current. This
is a global setting, not individual to each regulator. This patch
creates a new DT property: nxp,vin-ilim-microamp to specify such limit.
It is applied when the device is initialized.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Voltage ranges were hardcoded in Devicetree, however, things can be
significantly simplified by using the recently introduce linear ranges
API. All values are now computed using information stored in the driver,
so there is no need to store any lookup table in ROM. Code should now
both be faster in average and consume less ROM.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Maximum current was not specified. Even though not used, yet, it is a
valuable information. Values taken from PCA9420 datasheet, Figure 1
"Simplified block diagram".
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Regulator registers were set for each BUCK/LDO in DT, likely because of
the way the devices were instantiated. When using a generic iterator,
ie, DT_INST_FOREACH_CHILD, there's no way to differentiate the child
being _parsed_. Since instantiation happens now based on child node
names, we are able to know which registers each devices gets assigned at
the driver level. This greatly simplifies Devicetree, and it actually
removes information that is not strictly hardware description from it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Right now the PCA9420 driver instantiates by iterating over all
children. This is somewhat problematic, for a few reasons:
- Since instantiation is generic code, we're forced to put internal
details on Devicetree, e.g. reg-masks. After this change, this will no
longer be necessary.
- We take all children, regardless of what is defined in DT.
While we have no means to validate Devicetree node names as in Linux
dtschema, this approach allows us to have per-child specific
initialization code. This is somewhat similar to the Linux approach.
Note: nodelabels have been removed, since they were not used.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
regulator-allowed-modes/regulator-initial-mode are standard properties
defined in regulator.yaml, so use them.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Import all Linux properties, so that we can maximize compatiblity with
upstream bindings.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Following Linux regulator.yaml, regulator-name is a common property for
all regulators.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Define the octospi node for the stm32l4plus MCUs from
STMicroelectronics.
It is controlled by a OSPIMgr in front of each peripheral.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The sdhc-spi-slot requies an spi bus, but sd nodes (like sdmmc-disk)
cannot be added to it without a warning because it does not declare an
sd bus.
Signed-off-by: JP Sugarbroad <jpsugar@amazon.com>
RT1718S is an i2c-based TCPC chip that supports 3 additional GPIOs.
The pins can be used for USB-C operations e.g. handling FRS, but they
can also work as usual GPIOs.
Add a driver for the RT1718S GPIO and a handler for an alert signal from
the chip. The handler reads the alert register once asserted and calls
the GPIO interrupt handler if needed(Vendor-defined alert).
gpio_rt1718s.c file and "richtek,rt1718s" node collect common properties
and data for all RS1718S functionalities. The file can be extended for
TCPC driver. rt1718s.h file also defines inline functions with i2c
operations common for all drivers. The common header and source files
can be moved to tcpc directories once the tcpc driver is added since it
is the main functionality.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Add drdy_pulsed property in Device Tree in order to select how
data ready irq should behave (either pulsed or latched mode).
Moreover change/fix the API called to set drdy irq mode.
(fix#51944)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Since we can include other binding files at any level (child,
grand-child, etc.) it makes no sense to maintain two copies of pinctrl
props definitions (pincfg-node/pincfg-node-group). Instead,
pincfg-node.yaml defines props at root level, and it is included where
needed, either child-binding or grandchild-binding.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Added i-cache-line-size and d-cache-line-size values
to device tree for cavs and ace platforms. These values
are used by sys_cache_instr_line_size_get and
sys_cache_data_line_size_get functions.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added to the device tree values of the dma-copy-alignment
and dma-buf-size-alignment attributes.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added to the device tree values of the dma-copy-alignment
and dma-buf-size-alignment attributes.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
dma-buf-size-alignment: Buffer size alignment required by the DMA
controller.
dma-copy-alignment: Minimal chunk of data possible to be copied
by the controller.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Renamed the dma-buf-alignment field to a more explicit
and descriptive name dma-buf-addr-alignment.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
No sfdp-table property given by the DTS but received from
the octoflash Node rely on the issued by the read sfdp command.
Note that the size of the mx25lm51245 flash controller
is expressed in bits (ie 512Mbits or 64 Mbytes).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Changing pcie0 to pcie0: pcie0 allows it to be referenced as &pcie0. I
am not sure why this is required. Otherwise I get error:
...
parse error: undefined node label 'pcie0'
...
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
FlexSPI memory map indicates that the FlexSPI register space is 128MB, not
64MB. Update this value to be correct.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
DTS property attributes are (by default) not required.
Explicitly specifying `required: false` is redundant.
Perhaps a warning to that effect would be useful.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
Add a sample sbs gauge driver with feature parity and basic tests
comparison to its sensor counter-part. Includes a simple stub test that is
extended upon.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Added support for fxas21002 sensor over SPI bus on
RDDRONE board and proper selection through dts.
Tested with fxas21002 sensor on RDDRONE.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Co-authored-by: Sumit Batra <sumit.batra@nxp.com>
Added support for fxos8700 sensor over SPI bus on
RDDRONE board and proper selection through dts.
Tested with fxos8700 sensor on RDDRONE.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Co-authored-by: Sumit Batra <sumit.batra@nxp.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The BDF values can differ on the same platform, based on e.g. BIOS
configuration, and in the case of qemu the command line parameters. It's
therefore more reliable to always look up the BDF value based on the
known Vendor and Device IDs.
This patch introduces such a framework, and allows the incremental
update of PCIe drivers to start taking advantage of it.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add property mxicy,mx25r-power-mode to jedec,spi-nor binding for
controlling low power/high performance mode on Macronix MX25R* Ultra Low
Power flash devices.
- "low-power" configures the flash in ultra low power mode.
- "high-performance" configures the flash in high performance mode.
Signed-off-by: Gregers Gram Rygg <gregers.gram.rygg@nordicsemi.no>
Updating mps3_an547 board files with DTB entries for Ethos-U.
Adding DTS bindings for the Ethos-U DTB entry.
Signed-off-by: Kristofer Jonsson <kristofer.jonsson@arm.com>
Signed-off-by: Fredrik Knutsson <fredrik.knutsson@arm.com>
This commit adds an ieee802154 node to the list of nRF5340 application
core's peripherals. While it does not translate directly into a physical
RADIO peripheral, it represents the capability to use the ieee802154
radio (indirectly, through the network core).
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
The sensor uses the ALERT terminology (pin can be configured to trigger
on certain events such as conversion ready or overvoltage alerts). The
"IRQ" name is not clear.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Specify the units of the current LSB in microamperes, so that we can
measure low maximum currents. Right now it was specified in
milliamperes, but ignored and always hardcoded to 1mA in the driver.
This makes the driver pretty much useless when the maximum current to be
measured is in a range of e.g. 20-50mA.
This patch also removes some unnecessary ifdeffery: since we write the
calibration register, we can always provice measurements with the right
units. It is also wrong to provide sensor readings that do not match
with the units specified by the channel. After this change voltage is
always reported in V, current in A and power in W.
Note that power measurement had the current LSB hardcoded in the
calculation (assuming 1mA/LSB), this has been fixed as well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Following dtschema practices, add phyisical units to the shunt resistor
value: milliohms.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The "pmic" driver was in reality a driver for NXP PCA9420 PMIC. There's
no "universal PMIC". While the driver may work for other NXP PMICs, it
is clearly not generic for other vendors PMIC.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Force cache-size to 0 and treat flashdisk as read-only when backing
partition has read-only flag set. This allows users to save RAM when the
application does not write to the flashdisk, e.g. when a predefined FAT
filesystem is used.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Ensure that PECI block is enabled in the EC Subsystem by clearing
the PECI_DIS (peci disable) register
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Sort SoC nodes by address to make it easier to find them. As part
of this also move the intel-sha node under SoC where it belongs.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Following the modification of the STM32 OSPI driver, the clock-names
binding is now required
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 featuring octospi, clock-names are added to use them
instead of indexing for configuring the clock.
For U5 series, a third clock is added for the OSPI manager.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
"alh0: alh1:" will create only one instance and this needs to be
reverted to original form with two instances
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
As the power domain nodes don't represent something accessible via
a MMIO register move those under the lps node to address warnings
generated when building the DTS.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
The icmsg backend for ipc_service has a limitation of supporting only
on endpoint. This limitation is acceptable for many IPC instances.
However, some require to use multiple endpoints sharing a single
instance. To preserve the simple and the most efficient single-instance
backend, a separated backend is introduced implementing a wrapper
around icmsg core which adds multiple endpoints support.
There are two multi-endpoint ipc_service icmsg backends: one in the
initiator role, and the other one in the follower role. In a IPC
configuration one end of communication must be in the follower role
while the other one is in the initiator. The initiator initiates
an endpoint discovery handshake to establish enpoint identifiers for
requested endpoint names. The follower responds to requests sent by
the initiator.
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
For larger transfers DMA can be used enabling other tasks
to continue running. A threshold of 32 byte transfers
is about right and is defined threshold value for using DMA.
This does not currently support multiple SPI transactions changing
chip select with DMA (though the hardware supports this) currently.
Instead opting for the simpler first change of enabling one shot
DMA SPI transfers for those where the size warrants it.
Adds the loopback binding option to enable the spi_loopback test.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Set the status of the DMA controller, xdmac, to disabled. In effect
changing the default status from okay to disabled for all sam e70
based board.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add support input interrupts for GPIO pins on NXP S32Z27
SoC. The driver will convert GPIO pin to respective
interrupt line that will be processed by External
Interrupt Controller.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add initial support for the NXP S32Z27 SIUL2 External
Interrupt Controller. Each SIUL2 node has a child node
will act as an interrupt-controller that processes external
interrupt signals.
This driver is required to manage GPIO interrupts.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
New ADC driver for the TI CC13xx/CC26xx family.
ADC channel configurations are translated from Zephyr constants to
simplelink driverlib ones (e.g., sample times use a lookup table).
Async mode was also implemented & tested.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.
The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.
The code is inspirated from atmel_sam0/samd21.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
This commit adds an optional property to the nRF21540 Front-End Module
devicetree description that specifies supply voltage in mV. This
property can be used by the nRF21540 driver to compensate the value of
achieved gain for different supply voltage.
Signed-off-by: Artur Hadasz <artur.hadasz@nordicsemi.no>
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Define the DMA and DMAMUX peripheral for the stm32MP1
DMA1 and 2 are of type V1 of 8 streams (channels) each
with a DMAMUX peripheral. See the RefManual for details.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add SparkFun Pro Micro header connector that is implemented by many
other controllers. This allows hardware with compatible headers to
define the related GPIOs and peripherals.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Cavs25 alh definition is currently the same as in ace platform, which is
wrong, thus fix it.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Those dividers were configured in Kconfig so far. Add 'arm-podf',
'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes
under 'ccm' (Clock Control Module) and use configured 'clock-div' values
instead of Kconfig equivalents.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
The ESP32 series MCUs allow to set a timeout which triggers an error
if the SCL line is unchanged for the specified amount of time.
By default, the ESP-IDF HAL sets the timeout to an arbitrary value of
10 times the bus cycle.
This is not sufficient for chips like the TI bq76952, which pulls the
SCL line low (clock stretching) for several 100 µs.
The timeout should also not be dependent on the chosen bitrate, as it
is defined by the time a chip needs for internal calculation before it
can provide requested data or continue communication.
This commit adds a property to devicetree to allow configuration of
the scl timeout. This value is set via direct register access, as the
ESP-IDF HAL does not provide access to the enable bit and does not
give any information about the maximum size of the timeout (defined
in I2C clock cycles in the register).
Fixes#51351
Signed-off-by: Martin Jäger <martin@libre.solar>
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Set default interrupt priority to 3 for all Microchip MEC172x eSPI
host child devices except the UART's which are set to 1.
The espi peripherals don't require the maximum priority hence they
are being made uniform and a lower priority 3.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add bindings to describe a block storage device based on flash map
partition.
Co-authored-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add devicetree binding for the PSA Crypto Random source.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
This commit adds missing binding file for the ite,it8xxx2-usbpd.
Without this file, the DT_HAS_*_ENABLED macro wasn't defined and
couldn't be used in the Kconfigs.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
A USB TypeC connector has many peripherals associated with
it and the DTS binding in this commit provides a way to group
peripherals and properties in a device tree.
This binding is used with the USB-C Subsytem.
This is based on Linux, documentation:
https://www.kernel.org/doc/Documentation/devicetree/bindings/connector/usb-connector.yaml
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
Add pin control properties to the STM32 UCPD bindings file so that
the pins can be configured in the device tree.
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
USB interface that may be used to send messages from a USB host to
the M4 processor in the S3B, and vice-versa.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
Add support for regulator-boot-on to PMIC driver. Many PMIC devices will
be enabled at boot, so this property allows the regulator framework
to correctly track their state.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
As part of a previous refactor, this property was removed from the STM32
USART binding. The driver code to support this feature was not changed.
This commit simply adds the property back to the new base .yaml for
device trees which used it.
Tested on a proprietary board using the STM32U5 on USART1.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
Migrates all Winsen sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all WE sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Vishay sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all TI sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all ST sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Silabs sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Sensirion sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Semtech sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Seeed sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all SBS sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Plantower sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Panasonic sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all NXP sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Nuvoton sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Nordic sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Microchip sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Measurement Specialties sensors to inherit base sensor
device properties. This will allow us to define properties shared by
multiple sensors in one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Maxim sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all LM sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all ITE sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Intersil sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Invensense sensors to inherit base sensor device
properties. This will allow us to define properties shared by multiple
sensors in one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Infineon sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all HOPERF sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Honeywell sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Espressif sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Bosch sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Avago sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Atmel sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Asahi-Kasei sensors to inherit base sensor device
properties. This will allow us to define properties shared by multiple
sensors in one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Aosong sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all AMS sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all ADI sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Introduces an initial set of devicetree properties to be inherited by
all sensor devices, similar to how we define a base set of devicetree
properties for I2C and SPI devices. These properties will be used by the
future sensor subsystem to manage and expose sensors to a host operating
system, through HID or another protocol. Additional properties may be
added in the future.
An earlier version of this patch attempted to use the label property
instead of friendly-name, as it was noted during code review as a
possibly legitimate usage of the mostly-deprecated label property.
However, in practice it was difficult to implement because most sensor
bindings also inherit from i2c-device.yaml or spi-device.yaml, and
therefore inherit the deprecated label property from base.yaml. To work
around the deprecation, every sensor binding would have needed to
explicitly block the label property with a property-blocklist, which
would somewhat defeat the purpose of having a shared sensor-device.yaml.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Add MEC172x full duplex qmspi driver version to support full
duplex transfers as expected by the Zephyr spi driver model.
On every spi clock we transmit one bit and receive one bit.
This driver will work with Zephyr SPI NOR driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
updated dts variables naming (hyphen instead of underscore).
moved all properties in microchip ldma yaml to a separate include file,
these properties will be common with the (to be added)
full duplex spi driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Newer ESP32 series MCUs like the ESP32-C3 contain some register changes
incompatible to the original ESP32 and the SJA1000.
The additions in this commit consider these changes and fix the
incompatibilities in the TWAI front-end for the SJA1000 driver.
Signed-off-by: Martin Jäger <martin@libre.solar>
Enable GPIO driver on s32z270dc2_r52 boards. S32Z27 pads are grouped
into GPIO ports A to N.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Implement GPIO driver minimal API's for NXP S32 devices, based on SIUL2
peripheral. SIUL2 allows to control the pins electrical characteristics
such as internal pull resistors, pin direction and more.
GPIO driver API's for interrupts will be implemented in a future patch.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This patch introduces support for NXP S32 LINFlexD peripheral operating
in UART mode. Polling and interrupt-based serial API's are supported.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce support for Pinctrl driver on NXP S32Z/E SoC's.
The NXP S32 pin controller is a singleton node responsible for
controlling the pin function selection and pin properties, based on the
pin node group approach. The pinmux configuration is encoded in a
32-bit value.
Each S32 SoC implementing Pinctrl must create a `pinctrl_soc.h` header
which define SoC-specific macros to initialize the pinctrl structure.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce Pinctrl driver for SIUL2 module present on NXP S32 devices,
which provides control over all pins, such as function selection and
electrical characteristics that appear on external chip pins.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This patch introduces support for NXP S32 devices, specifically for
S32Z27 from S32Z/E family.
NXP S32Z27 processors are composed of two Real-Time Units (RTU)
containing each four ARM Cortex-R52 cores with flexible split/lock
configuration, and dedicated internal SRAM.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Ethernet MAC dts definition for STM32F107, similar to STM32F207 but with
different clocks, especially no PTP clock.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
Add mode selection properties for regulator-pmic compatible. These
mode selection properties will be used with regulators that support
multiple modes, with each mode enabling specific voltage and current
limits.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Refactor binding to use root PMIC IC, so that properties can be shared
between regulator devices. Each individual regulator output is still
created as an individual device, since the regulator API aligns with
these devices better than the PMIC IC itself.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is not guaranteed to match the physical layout of the memory, so
get them individually based on node label.
For initialization, use bbzero.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some windows might need to be set as writtable, so add a flag read-only
to DTS bindings which is set to true for all windows right now. This can
be set to false where needed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of just declaring the memory window register in DTS and have
everything else all over the place (headers, Kconfig, etc.) this change
defines the memory window instances in DTS and uses the device model to
initialize the windows. Code is still part of the SoC, given that we do
not have a driver subsystem suitable for this type of device yet.
Move FW status to own workflow and separate from window setup.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
If the flash is used in 4-byte addressing, reading SFDP will fail after
a system reset if the flash isn't power cycled or hardware reset, since
Zephyr will try to use 3-byte addressing while the flash (still) expects
4-byte addressing.
This commit adds the ability to send a reset command to the flash as part
of initialization, which complements the existing reset-gpio
functionality, and is useful on low-pincount flashes which do not have a
hardware reset.
Signed-off-by: Ole Morten Haaland <omh@icsys.no>
This is an AArch64 board. We also add RK3399 SoC support,
as well as a very simple Synopsys 8250dw UART driver.
Signed-off-by: Henri Xavier <datacomos@huawei.com>
Added support for the AMS AS621x series of temperature sensors as a
variant of the TI TMP108 temperature sensor.
Signed-off-by: Jared Baumann <jared.baumann8@t-mobile.com>
Signed-off-by: James Johnson <james.johnson672@t-mobile.com>
Adding ethernet in the DTS file and corresponding binding
for Cyclone V SoC FPGA board..
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
rt1170 has two group fast gpio and shared the same
interrupt source. Now add the dts definition for the
fast gpio
Signed-off-by: Crist Xu <crist.xu@nxp.com>
Add Intel dmic dai dts definitions for ace15, cavs15 and cavs25
platforms.
Add also pre dts cmake files as the dmic nodes use same address and emit
warnings otherwise.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Add a fifo address as int value into dmic yaml to separate different
outputs (corresponds to different dais) from the same hw block. Also
change shim address from array to int value.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Add successive inclusion for STM32F072 dts by including
STM32F070 dts instead of STM32F0 dts.
This allows to reuse the definition of
- Flash
- SPI
- USB
from the new parent.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Replace the hardcoded kPWM_Prescale_Divide_128
driver prescaler with the ones defined in the dtsi file
that allow overriding them by the user.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
This commit adds a driver to simulate GPIO state and interrupts
using the keyboard when using SDL.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Add 2 properties to configure the "any movement" event.
* Ability to disable the interrupt latch
* Select movement mode
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Update RT11xx SOC DTSI files to use DT nodelabels on RT11xx SOCs,
instead of reencoding the base address of each peripheral in the M7
and M4 DTSI files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Include files should not have compatible properties set. These do not
represent real hardware and should therefore not appear to do so, e.g.
by appearing in the bindings index as if they were a real hardware
peripheral.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Fix ordering of IOMUXC pinctrl selections for gpio pinmux setting.
This will allow the gpio_configure call to correctly set
mux settings for this SOC.
Fixes#50502
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The vref has to be set to 3000mV.
It is the voltage to find on the stm32F3.
is fixed by the platform to be lower or equal to VDDA.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add gpio-reserved-ranges property to gpio controllers on RT10xx devices
that have gaps in their GPIO numbering.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove pinmux calls and add pinctrl support for mec15xx
and mec1501 qmspi. Update board dts, pinmux and driver files.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Remove pinmux calls and add pinctrl support for mec15xx
and mec1501 adc. Update board dts, pinmux and driver files.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Remove pinmux calls and add pinctrl support for mec15xx
and mec1501 pwm. Update board dts, pinmux and driver files.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Remove pinmux calls and add pinctrl support for mec15xx
and mec1501 espi. Update board dts, pinmux and espi driver
files.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Apparently, downstream drivers are allocating devices using
DT_NODELABEL(alh0) and DT_NODELABEL(alh1) on a node with compatible
intel,alh-dai. These represent something like "channels" within the
device.
This is a strange choice. It would be better to do something like have
a property with the count of "channels", or one child node per
channel.
It is also a dtc error to have duplicate node names like this, and
will be an error in Zephyr's dtlib soon.
For now, work around this representation issue by replacing it with
something equivalent that doesn't have duplicate nodes. The
representation should be addressed at some point, but not by me.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Two issues:
- The nsmi_gpio107 node is being defined twice with the same pinmux
property value. This is an error when compiling the file with dtc.
Zephyr's dtlib doesn't currently error out on this, but it will soon.
Fix this by removing one of the redundant definitions.
- The eeprom_clk_gpio117 node label is referring to a node named
gpspi_clk_gpio117, which is already defined in the same file, but
with a different pinmux property value. This looks like a clear
copy/paste error causing invalid pinmux settings for the
gpspi_clk_gpio117 node.
Fix it by aligning the node name with the node label to create
a separate node with its own pinmux value.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Fix the incorrect temperature sensor (Die temp), the default value of
the vref-mv is 3.3V.
Actually, the vref is a board value rather than a soc one
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The FULLDRIVE description on the rt-iocon yaml file was
describing the slew rate and not the FULLDRIVE property.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
The LPC55s3x SOC comes with 2 FlexPWM peripherals each with 4 Sub-Modules.
Each Sub-Modules has 2 channels A && B.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
When the EXTI Line nb is not set as interrupt by default
(at reset value), the uart instance cannot waekup the
system from its low power stop mode.
The EXTI line must be specified, like with stm32WL55
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds a base binding for I3C controllers.
Note that this follows the Linux kernel 5.17 bindings under
Documentation/devicetree/bindings/i3c/i3c.yaml.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a few bits to the devicetree API tests for multi-bus
nodes where a bus can support multiple protocols. This uses
I3C as basis as I3C controller can support both I2C and I3C on
the same bus, while I2C controller cannot support both. So
this needs to make sure the correct bus macros are generated
if appropriate (and not generated if not needed).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add support to at86rf212[b] sub-giga devices. This work enables use of
pages 0, 2 and 5 in accordance with IEEE-802.15.4/2003/2006/2011. The
proprietary speeds can be object of future work.
Note: It is recommended that user define a power table for better
performance, low emissions and to save power. A reference power table
can be found in the datasheet and should be used for tests only and
not on a final product.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current version of power table is hardcoded in the driver which is a
problem when use devices in production. This change remove all hardcode
from driver and reimplement the feature to allow people create a table
which is defined in devicetree. The big advantage is that each board can
define their own table based on lab tests and allows use of FEM devices
inclusive.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some reg size in fvp-aemv8r.dtsi isn't correct. This commit is used to
fix it.
- gic, the correct reg size is 0x10000 and 0x200000.
- uart0-3, the correct reg size is 0x10000.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
The property is similar to the usb_controller_index_t
enum that is available in the NXP SDK.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit introduces the 1-wire master driver for maxim ds2485.
The ds2485 master has nearly the same (1-wire) feature set and
i2c-interface as the ds2477.
Therefore the common parts are extracted, but to avoid
any nda troubles only the ds2485 specific part is included.
Compared to older 1-wire masters, the ds2485 supports higher level
commands, supporting multi byte operations, search next, automatic crc
calculation.
In this driver only basic read and write operations are supported,
further hardware features are not yet utilized by the driver.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
According to errata sheet, LSE driving-capability should not be set
to 0 or 1.
Set it to 2 as default value.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This driver provides an interface to SocketCAN interfaces of the Linux
system running a Zephyr application with the native_posix board. These
interfaces may be virtual or actual CAN buses.
Signed-off-by: Martin Jäger <martin@libre.solar>
Migrate information to DTS and get it from there on the code. Note that
for CAVS 15, the information is not migrated as there's no DTS entry for
it. It can be brought back (in the DTS) if TLB support is enabled for
it.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Reduce the default RAM usage for the NXP LPC MCAN CAN controller driver by
reducing the number of RX buffers, TX buffers, and filter elements.
The LPC MCAN uses regular SRAM as backend and the default configuration
causes SRAM overflows for many CAN tests.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add emulator functionality to the serial_test driver, so that it can be
used to simulate a device on the other end of the uart.
If you don't set the buffer-size property in the dts node, there should
be effectively no change from the previous behavior.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Add the DMA in the DTS binding for OCTOSPI interface
for the stm32 devices from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
There are three types GD32 FMC.
GD32 FMC v1: its flash memory has 1 bank, page size is equal in the
bank, flash size is smaller than 512KB.
GD32 FMC v2: its flash memory has 2 banks. Page size equal within the
same bank but different between banks. Flash size can be up to 3072KB.
FMC v2 has two registers to control bank0 and bank1 separately.
GD32 FMC v3: its flash memory has 2 banks, use sector size as the
minimum operating unit, the sector size is not equal.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
The enet1g peripheral was missing in device tree for nxp rt11xx.
With this commit, the peripheral can be operated like the enet peripheral
with the eth_mcux (kinetis-ethernet) driver at 10/100 Mbit (no gigabit).
Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
R-Car Gen3 platforms have up to 7 channels. Add the node to
the rcar_gen3_cr7 SoC series. In contrary to Linux, declare
only one PWM controller with 7 channels. So only one node is
written into dtsi file.
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
Define RaspberryPi Pico ADC.
The ADC has internally connected temperature sensor,
Add property to enable this.
The ADC has a single VREF. VCC usually connects to it,
but it may not be in a case.
Add property to make configurable it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Use the clock control API to enable peripheral clocks. Note that both
GPIO and pinctrl drivers are updated at once since they share some IP
blocks.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use the clock control API to turn on ADC clocks. Note that clock
selection is not yet implemented, so we still rely on custom rcu
properties for that.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove the CAN_STM32FD_CLOCK_DIVISOR configuration option,
and add configuration via dts property clk-divider instead.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
There is only a single DMA in GD32F3X0. It is referenced as DMA in
datasheet, not DMA0 as in series that have > 1.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano
applications processor, composed of a quad Cortex®-A53 cluster
and a single Cortex®-M47 core.
Zephyr OS is ported to run on the Cortex®-A53 core.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
1. Enable all cpu cores in soc dts and disable unused core in board dts.
2. Use default irq priority for uart interrupt.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Use node label to overwrite the flash and ram properties.
This removes some boilerplate as it is less verbose.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Changes to code:
1. Renamed CAVS_IPC API from common/include/cavs_ipc.h to
common/include/intel_adsp_ipc.h. Renamed all API functions and structs -
added "intel_adsp_" prefix.
2. Moved definitions from intel-ipc-regs.h and ace-ipc-regs.g to SOC
specific headers include/<soc_name>/adsp_ipc_regs.h.
3. Added new common intel_adsp_ipc_devtree.h header with new
macros to retrieve IPC and IDC nodes and register addresses.
Put those new macros in code replacing hardcoded values outside of
devicetree.
4. Changed documentation of IDC and renamed IDC register struct
to have common name between all intel adsp socs.
5. Removed excessive docs description on cAVS IPC protocol.
Changes to Devicetree:
1. Renamed in all CAVS boards .dtsi files content in IPC nodes:
- "cavs_host_ipc" node labels to "adsp_ipc" labels.
- compatible "intel,cavs-host-ipc" renamed to
"intel,adsp-host-ipc".
2. Added (previously missing) yaml file for "intel,adsp-host-ipc"
compatible.
3. Renamed in all CAVS boards .dtsi files content in IDC nodes:
- "idc" node labels to "adsp_idc" labels.
- compatible "intel,cavs-idc" renamed to "intel-adsp-idc"
4. Renamed intel,cavs_idc.yaml file to intel,adsp_idc.yaml
so it is suitable for both CAVS and ACE SoC family.
Moved it from ipm bindings to ipc bindings where it belongs.
Changes to Kconfig:
1. Renamed existing Kconfig option CONFIG_CAVS_IPC to
INTEL_ADSP_IPC.
2. For renamed INTEL_ADSP_IPC addded default value based on
status of the "adsp-ipc" and "adsp-ipc" node.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Convert the device to be Devicetree based. Adjusted tests and other
areas that were using old Kconfig properties.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This patch adds D0i3 definition to available core power states in device
tree.
Additionally, changing the name of the OFF state to better reflect what
is in the documentation.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Added code to enable platform specific Virtual Wire GPIOs. With this
change, able to send the USB-C overcurrent Virtual Wire event to
Meterolake SOC.
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
The clock bus of the specific SPI module (FIU) is under FIUCLK. The
previous commit misconfigured it to APB3_CLK. Although it won't
cause any issue as the driver doesn't use it. It should be fixed to
prevent confusion when reading the datasheet.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Some custom refresh profiles need to set the PLL and VDCS
registers. Add them as optional DT properties.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add support for overriding display LUTs in the UC81xx driver. This
makes it possible to use different LUTs for the full and partial
refresh profiles.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add a separate profile for partial refreshes. This makes it possible
to specify a separate refresh configuration for partial and full
refreshes.
The driver now transitions to full refresh mode when blanking is
turned on. It transitions back to partial refresh mode when there is a
write while blanking is off.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Introduce the concept of refresh profiles which are specified as a
child node in the device tree. This makes it possible to use different
overrides for different types of refreshes (full/partial).
The only profile that is currently supported is the "full" profile.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
This reverts commit fdd47f39be.
After v4.4.1, write-block-size is no longer needed to be 32-bytes
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This patch is to add Cadence QSPI NOR flash device tree element
for the Cadence QSPI NOR flash driver bringup
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
This patch is to increase kernel VM size to 1.5MB and
memory size to 2MB to ready for future driver bring up.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
There are two external clocks driving i.MX RT 10xx SoCs: XTAL and
RTC_XTAL. Add "fixed-clock" DT nodes for each. Update also "nxp,imx-ccm"
binding, so that CCM (Clock Control Module) peripheral consumes those
clocks by "xtal" and "rtc-xtal" names.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
zephyr.dts:482.21-491.5: Warning (simple_bus_reg): /soc/dietemp: missing
or empty reg/ranges property.
To fix this bug, just move dietemp node outside of soc{}.
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
This adds flash driver for Renesas SmartBond(tm) family.
This technically uses QSPI controller but since default and most
commonly used configuration is to boot from external QSPI flash (DA1469x
do not have built-in flash) and that flash is mapped into memory space,
it can be represented as internal flash.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds serial driver for Renesas SmartBond(tm) family. Both polling
and interrupt APIs are supported.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds GPIO driver for Renesas SmartBond(tm) family.
Driver supports pin configuration (input/output) and interrupts on edge.
Interrupts on level are not supported by hardware.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds initial support for Renesas SmartBond(tm) DA1469x series SoC.
Initailly only DA14699 is explicitly supported, however this code should
also run on other SoCs in this series since all of them support the same
core features available initially.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This device-tree file is only used by rt10xx dtsi files, as rt11xx (and
other families as well) have their own root SoC specific dtsi file.
Rename nxp_rt.dtsi to nxp_rt10xx.dtsi for consistency across families.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
All 'k' parts share the same amount of RAM/FLASH, so rename file to
include 'x' instead of 'i'.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new reset driver for GD32 platforms. This driver controls the
reset registers from the RCU peripheral. It can be used to restore
peripherals to their initial state when initializing a device.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add prescaler property to prevent counter driver imprecise when CPU clock
is close to the PIT clock.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
It was not possible to disconnect a pin using the nRF pinctrl driver.
That is, it was not possible to set PSEL to 0xFFFFFFFF (indicating pin
is not connected). This can be useful in certain scenarios, e.g. a
bootloader configures all signals of a certain peripheral but
application then needs to disconnect certain signals.
A new DT macro has been introduced to accomplish this:
NRF_PSEL_DISCONNECT. It can be used like this to explicitely disconnect
a peripheral signal:
```
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 1)>,
<NRF_PSEL_DISCONNECTED(UART_RX)>;
};
};
};
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit enables the SoC's flash memory controller.
- added lpc55s36 specific code in the NXP MCUX driver
to take advantage of the SoC's check-before-read
capability
- enabled the FMC node in the SoC's dtsi (iap)
- added the flash controller chosen node to the board's dts
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Disable flexspi flash controller by default, allow boards to enable it.
This SOC uses external flash, so boards should only enable the flash
controller when their specific flash module has been verified to work
with the flash driver API in Zephyr.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
enable IAP flash controller for secure core, as this is the core where
flash support has been verified.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Disable IAP by default for lpc55s06, enable it for the non secure core
as this is the mode that the flash controller has been tested in.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for LPC54xxx IAP flash driver to soc_flash_lpc.c
Driver is tested on M4 core only, and is therefore disabled on the M0 core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update flexspi partition layout to add a 128KB storage partition. Also,
fix flash device name and size to match the SIP flash present on
the RT1024 SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Document support for flexspi as flash controller on mimxrt1064_evk, and
move status=okay for internal flash to soc level dtsi
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
disable flash controller for nonsecure core, as only the secure core is
tested with flash support.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
set nxp,imx-flexspi to disabled by default to disable flash driver for
this SOC unless enabled by the target board. This SOC uses external flash,
so boards should enable the flash controller only when flash support
has been verified with their specific external flash module
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
According to DT spec, device_type property is deprecated (ref. 0.3 spec,
2.3.11):
> The device_type property was used in IEEE 1275 to describe the device’s
FCode programming model. Because DTSpec does not have FCode, new use
of the property is deprecated, and it should be included only on cpu and
memory nodes for compatibility with IEEE 1275–derived devicetrees.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Set the default value for SYS_CLOCK_HW_CYCLES_PER_SEC based on DT cpu0
clock-frequency property.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Set the default value for SYS_CLOCK_HW_CYCLES_PER_SEC based on DT cpu0
clock-frequency property.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Make use of nodelabels to extend flash/sram nodes instead of re-defining
the whole tree. This pattern is already used in some other files.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Despite being used in GD32 dts files, the compatible did not exist. Note
that there is no GD32 flash driver yet.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
There's no need to specify the interrupt parent on each node, it can be
defined at soc level node instead (same as in ARM parts with NVIC).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The can2 only works if gating clock of the master can (can1)
is enabled, therefore also set that bit for can2.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add the support of the temperature sensor in the ADC device-tree node of
each stm32 where it is available.
- Check all the ADC of the stm32 mcus where the temp and VrefInt monitoring
is available (based on the Ref Man).
- Check that has-temp-channel; and has-vref-channel; in the corresponding
ADC node of the DTS of each stm32 mcu is correctly set.
- Verify the VTEMP/ VREFINT activation in the in adc_stm32.c for example).
-Add the die-temp node (based on the ref man/ datasheet).
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
The TS_CAL values for the temperature sensor are measured on 12, 14 and
16 bit resolution depends on the STM32 series. Because the drivers
operates at 12 bit resolution the TS_CAL1 and TS_CAL2 must be divided.
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
USB SRAM region was accidentally deleted by an earlier
commit. Rename the memory region used by USB to USB_SRAM instead
of SRAM4. SRAM4 was the wrong name for this region.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit defines the GPDMA peripheral for the stm32U5.
This dma is of a new type with 16 channels and 114 requests.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit defines a new dma version for devices like stm32U5.
The peripheral is a GPDMA in this soc serie.
It has several specific definitions used by its stm32 LL driver
compared to the V2, including up to 16 channels.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove 'ranges' property from gpio node as it shouldn't be there
since we aren't converting 1:1 between address spaces. This fixes
the following DTC warning:
Warning (ranges_format): /soc/gpio@e000a000:ranges: empty "ranges"
property but its #size-cells (0) differs from /soc (1)
Signed-off-by: Kumar Gala <galak@kernel.org>
We currently get a number of warnings like:
Warning (simple_bus_reg): /soc/otgfs_phy: missing or empty
reg/ranges property
This is due to the usb phy nodes not have a reg property since they
don't have an mmio address associated with them.
Move the phy nodes out of the SoC node so their lack of a reg property
will not cause a warning. This is similar to how Linux dts files
handle the phy nodes.
Signed-off-by: Kumar Gala <galak@kernel.org>
There are 3 bindings for STM32 serial driver:
st,stm32-uart.yaml
st,stm32-usart.yaml
st,stm32-lpuart.yaml
Add a common st,stm32-uart-base.yaml that would be included by these
3 bindings an would group common properties.
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
Adding I2C FIFO mode can reduce the time between each byte to
improve the I2C bus clock stretching during I2C transaction.
The I2C master supports two 32-bytes FIFOs, channel A and C
are supported now.
I2C FIFO mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.
Test:
1. tests\drivers\i2c\i2c_api --> pass
2. Reading 16 bytes of data through i2c_burst_read() can reduce
0.52ms(2.4ms->1.88ms) compared to the original pio mode when the
frequency is 100KHz.
3. It is normal to read sensor data through I2C on Nereid's platform.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit adds string token versions of the values also
in items inside string-array.
Signed-off-by: Radosław Koppel <r.koppel@k-el.com>
Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Co-authored-by: Kumar Gala <galak@kernel.org>
Add missing support for the triggered mode using GPIO
interrupt alert pin. It uses mode detection at runtime
which allows working multiple sensors with different
modes simultaneously.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
The nist-config and health-test-magic properties are added
to the dtsi file, in the RNG node for the stm32 devices
that supports the RNG entropy source validation.
The health-test-magic nb exists on stm32l552 stm32h723/7a3.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The new property nist-config is introduced to the stm32 mcus
to configure the RNG for NIST SP800-90B certification.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The gpio-leds binding is meant for LED drivers, not GPIO. As in Linux,
move the binding to the led folder.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
gpio-keys binding has been used in Zephyr to describe random push
buttons in boards. On Linux, it is used by a keyboard input driver,
while in Zephyr is, in most cases, used directly in applications out of
the device driver model. This should likely be _fixed_ if one day we
have a proper input device class. Still, we can align a few things:
- Inherit from base.yaml (we need status, compatible, etc defined there)
- Remove the requirement of a label in child nodes
- Fix child nodes label description
- Move to dts/bindings/input
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Don't import the label prop from base.yaml as it is marked deprecated.
This lets the various tests that still use DT_LABEL() to work properly.
Signed-off-by: Kumar Gala <galak@kernel.org>
Mark 'label' property as deprecated in base.yaml. 'label' is still
defined and valid for specific bindings to specify like gpio-keys.yaml
or fixed-partitions.yaml.
Signed-off-by: Kumar Gala <galak@kernel.org>
Previous versions were using, incorrectly, the host in/out regblock size
of 40 bytes for all peripherals when in fact the link in/out regblock size
is 20 bytes in size.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add spi0 and spi1 configuration to rp2040.
spi0 and spi1 are declared as compatible with
"raspberrypi,pico-spi" and "arm,pl022".
"raspberrypi,pico-spi" is just inherited from
"arm,pl022" and "reset-device"
spi0 and spi1 declare as compatible with "raspberrypi,pico-spi"
and "arm,pl022".
"raspberrypi,pico-spi" is just inheriting "arm,pl022" and
"reset-device" for declaring the 'reset' property,
with no additional property and implementation.
Add also pinctrl macros to dt-bindings header.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add fundamental feature support for PL022 SPI peripheral.
This commit implements synchronous transfer with 8bit-MSB format.
Optional functions are not currently implemented yet.
- interrupt based transfer is not implemented yet.
- DMA transfer is not implemented yet.
- Slave mode is not implemented yet.
- Currently support only 8-bit data transfer.
Hardware limitation:
- LSB-first format is not supported by hardware.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
The fast-gpio has a dedicated interrupt idx 99, not
the same with the normal gpio. So if we want to use
the fast-gpio, need use the interrupt idx 99.
Signed-off-by: Crist Xu <crist.xu@nxp.com>
The binding 'nxp,lpc-iap' is no longer used, which is confirmed
by running:
$ find ${ZEPHYR_BASE}/dts/arm/nxp -type f | egrep -e '\.dts(i)*$' | \
xargs grep -nH nxp,lpc-iap
Changes in this commit:
- remove DT_HAS_NXP_LPC... in drivers/flash/Kconfig.mcux
- remove schema file for nxp,lpc-iap
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
The lpc and mcux drivers' DRV_COMPAT is updated for the new bindings
introduced in the previous commit. The drivers' Kconfig files also
reflect this change (DT_HAS_ENABLED_NXP_...).
The SoC device trees are updated with the new bindings
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
The binding 'nxp,iap-lpc' is used for different flash controllers,
preventing clarity. This commit introduces bindings for each version of
the flash controller, as they appear with NXP lpc device families:
nxp,iap-fmc11: for the flash controler used on the lpc11u6x family
nxp,iap-fmc54: for the flash controler used on the lpc54xx family
nxp,iap-fmc55: for the flash controler used on the lpc55xx family,
except lpc553x
nxp,iap-fmc553: for the flash controler used on the lpc553x family
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
The names of these peripherals in the device tree
did not match the Reference Manual for the RT600.
Added alias for usdhc0 to be able to use SDHC test.
Also fixed a typo in a comment referring to USDHC which should have been
about USB.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add pinctrl definitions for the SMC peripheral (8) and add the
module to the sam4e soc.
IDs and addresses are taken from the datasheet.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The SSD16xx driver currently hard-codes a couple of register overrides
that aren't relevant or even correct for many devices. Make them
optional device tree properties instead.
Note that this changes the behavior for panels that expect
SSD16XX_CMD_DUMMY_LINE and SSD16XX_CMD_GATE_LINE_WIDTH to be set by
the driver. This fixes a bug where the incorrect value
was written to all SSD16xx panels except for GDEH0213B1 and GDEH029A1.
The overlay files for devices that need dummy line and gate line width
to be specified have been updated as a part of this commit.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The OTP in most SSD16xx-based displays normally contain default
VCOM/GDV/SDV values. Make all of these optional in the device tree.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Avoid build errors for platforms that do not support devicetree and
hence do not generate a Kconfig.dts.
Signed-off-by: Wolfgang Puffitsch <wopu@demant.com>
Add the option to specify the minimum duration that the `reset-gpios`
pin is held low on boot. This lets devices with additional capacitance
on the reset line still reboot the Bluetooth controller.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This fixes underrun issues when hardware flow control can't be used.
Only tested on STM32F4.
Signed-off-by: John Kjellberg <kjellberg.john@gmail.com>
...
All the of the ITE it8xxx2 devicetree compatiables are of the form
ite,it8xxx2-<DEV>. However the PECI device was ite,peci-it8xxx2,
rename the compatiable to match the pattern used everywhere else.
Signed-off-by: Kumar Gala <galak@kernel.org>
Add dts bindings for the NIOS2 QSPI controller and flash device and
add nodes to the dts files for these devices as well.
Signed-off-by: Kumar Gala <galak@kernel.org>
Fat finger mis-typed when I renamed the file last time.
So correctly name the file this time. Hopefully this is
correct and won't need anymore renaming... :(
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The current atmel sam flash driver was develop based on the cortex-m7
version of smart arm microcontroller. The driver support write
protection and cache functions which is not supported by other cortex-m
variants. This fixes current driver implementation and devicetree
entries for all sam variants.
Notes:
* The cortex-m3 doesn't have support erase pages flash command and
because of that the driver still not not compatible. Keep it disabled
until a patch be send. The hwinfo driver is not affected by this
restriction.
* The sam4l variation requires a specific driver because uses another
flash controller (flashcalw). Added another compatible to
differentiate and keeped node disabled until a driver be available.
Fixes#48516
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
() Fix the compatible string from "intel,dai,dmic" to
"intel,dai-dmic".
() Also rename the yaml file to have vendor name first.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Enable Zephyr device runtime power management mechanisms in Intel SSP
driver. This allows Zephyr to track usage reference for power
domain gating.
Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
Labels are no longer needed because devices are obtaines using
zephyr,ieee802154 DT choice.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use a test compatible so that test can create a DT-based device and
provide a valid choice when building the test.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable the IEEE 802.15.4 radio node on all boards that listed
'ieee802154' in the supported field.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to work on a clock speed higher than 20 MHz, IO MUX is required.
Co-authored-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Signed-off-by: XiNGRZ Chan <hi@xingrz.me>
various microchip bindings set 'girq-cells' and 'pcr-cells'
sections in the bindings. However the bindings where for the
client nodes and thus do not need to set these.
Signed-off-by: Kumar Gala <galak@kernel.org>
Change the wording about "alternate/optional" clock to "domain" clocks,
to better describe the feature and minimize confusion.
Additionally, provide more description about domain clocks and dual
domain functionality implemented in peripherals.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds optional device tree property to specify a default character
to clock out when the TX buffer pointer is NULL. If the property is
not set the existing behavior (default char of 0x00) is used.
I verified the expected behavior using an i.MX RT685 board and
logic analyzer that the def-char character is transmitted when
TX buffer pointer is NULL.
Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
This is temporary until support has been enabled. lpc55s36's IAP controller
is different and does not match previous implementations.
The Zephyr driver uses a data structure matching the IAP controller to
implement a feature that should normally come out of the ROM.
Since IAP support is not in yet, disabling the option in the SoC's Kconfig
and disabling the node in the device tree is the proper way to go forward.
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
LPC55s3x family has an additional analog mode bit available. Update
IOCON binding and IOCON driver to support setting this bit via a pin
control property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use Devicetree to describe the UART UPIPE IEEE 802.15.4 driver. This
allows to remove usage of IEEE802154_UPIPE_DRV_NAME in preparation for
the removal of NET_CONFIG_IEEE802154_DEV_NAME.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_NRF5_DRV_NAME in preparation for the
removal of NET_CONFIG_IEEE802154_DEV_NAME.
All SoC files have been updated with the addition of an ieee802154 node
(disabled and only on those SoCs that define ieee802154-supported. The
peripheral has been enabled in the nRF52840DK board (used for testing
ieee802154).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_KW41Z_DRV_NAME in preparation for the removal
of NET_CONFIG_IEEE802154_DEV_NAME.
KW41Z files have been updated with the addition of radio and an
ieee802154 nodes The peripheral has been enabled in the frdm_k41z board
(used for testing ieee802154).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_CC13XX_CC26XX_SUBG_DRV_NAME in preparation
for the removal of NET_CONFIG_IEEE802154_DEV_NAME.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_CC13XX_CC26XX_DRV_NAME in preparation for the
removal of NET_CONFIG_IEEE802154_DEV_NAME. All boards used in testing
have been updated to enable the peripheral in DT as well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
ICI (Inter-Core Interrupt Unit) interrupts and priorities were hardcoded
in C files. This patch moves this information to Devicetree and updates
code to make use of it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
sysconf base address was hardcoded in <soc.h>. Create a new compatible
and define it in Devicetree, where hardware needs to be described.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe secure timer0 instead of hardcoding values in
<soc.h>.
DT files have been structured to match the following requirements: In
case of sectimer0 - it's should be only enabled for:
- emsdp_em7d_esp.dts
- em_starterkit_em7d.dts
- nsim_sem_mpu_stack_guard.dts
- nsim_sem.dts
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files were missed during the migration. This patch adds the prefix
where missing.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Introduce a simple binding for atmel,24mac402 EEPROM that the SAM
GMAC ethernet driver can utilize to get MAC address out of. We
introduce a 'mac-eeprom' phandle into GMAC ethernet devicetree
node that will provide a pointer to the MAC eeprom to utilize.
Signed-off-by: Kumar Gala <galak@kernel.org>
Use the sifive,clint0 compatible instead of "riscv,clint0" and remove
interrupt controller fields (clint compatible is used for its timer
registers). Refer to the Linux or previous commits for more context.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use the sifive,clint0 compatible instead of "riscv,clint0" and remove
interrupt controller fields (clint compatible is used for its timer
registers). Refer to the Linux or previous commits for more context.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The CLINT (Core Local Interruptor) description was not aligned with
Linux. For example, there's no "riscv,clint0", but "sifive,clint0". The
peripheral is not described as an interrupt-controller either.
Ref. https://elixir.bootlin.com/linux/v5.18.14/source/arch/riscv/boot/
dts/starfive/jh7100.dtsi#L106
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
After some analysis I found out that there's no machine timer provided
by the "riscv" vendor. There are some specs for the mtime/mtimecmp
registers (this is why we can have a single driver), but the actual
register layout or implementations differ amongst vendors. GD32 uses the
Nuclei implementation, named "system timer" in their documentation. This
patch aligns with vendor specs.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This adds a driver for Maxims DS2484 Single-Channel 1-Wire master
driver. The DS2484 features an extra pin to enable sleep modes which
is available if the pin is configured in the device tree.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Unlike stated in 57df225b396e43358aac4cc998ed2e99fdb57780, RM0456.pdf
reference manual mentions about PLL1R that "Only division by 1 and even
division factors are allowed."
Though, in reference manual, there is one issue on PLL1R values
description, which should actually be:
0000000: pll1_r_ck = vco1_ck
0000001: pll1_r_ck = vco1_ck / 2 (default after reset)
0000010: Not allowed
0000011: pll1_r_ck = vco1_ck / 4
...
This description will be fixed.
Reflect this in binding and driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This configuration does not work on some variants (simulator), reduce
the number to something that work on all variants.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of enabling WOVCRO clock based on the SOC, use a configuration
to indicate support, so that each platform can specify if WOVCRO is
supported or not.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Add system clock control device (sysclk), so that the drivers can turn
on/off its clock through the clock control API.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Add binding for Aspeed AST10x0 clock driver. The clocks can be turned
on or off through the syscon registers.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
The stm32f303x8 SoC is not equipped with spi2 and spi3 peripherals.
Exclude them from the SoC-level devicetree.
Signed-off-by: Jan Kuliga <jtkuliga@gmail.com>
Add the octospi nodes to the stm32h7A3 and
and h7B0/h7B3 devices.
Note that RM0455 gives a size of 1kB.
The definition of the octospi clock source for both intances
is given by the DTS node. The selected value for
the alternate clock control is the PLL1_Q.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the octospi nodes to the stm32h723/h725
and h730/h733/h735 devices.
Note that RM0468 gives a size of 1kB.
The definition of the octospi clock source for both intances
is given by the DTS node. The selected value for
the alternate clock control is the PLL1_Q.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The UC8176 and UC8179 chips that exist in tree have subtly different
register layouts. Use separate compatible strings for these chips and
a quirks structure that describe device-specific behavior.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The GD7965 driver is really just a vendor name for the UltraChip
UC8179. Rename the driver to UC81xx since there are other chips in the
family (e.g., the UC8176) with an almost identical register interface.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
For the !SOC_I2C_SUPPORT_HW_CLR_BUS in which we implement bus
reset via GPIOs, change the devicetree properties to be actual
gpio properties and update the code to reflect this.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commit adds the pll2 and pll3 clock control nodes
with st,stm32u5-pll-clock compatible.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit changes the range for stm32u5 pll divider values
to allow divider value of 1.
- DIVQ is allowed to beconfigured 1 for all PLL instances
- DIVR can be 1 for PLL2 and PLL3, but is not valid for PLl1.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
We have drivers for "nxp,lpc-rtc" and "zephyr,native-posix-counter"
devicetree compatibles, however we had no bindings for them. Add
simple bindings
Signed-off-by: Kumar Gala <galak@kernel.org>
Two files ending with yml while the rest is ending with yaml, just
rename those two to avoid special handling.
Fixes documentation build.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This CL adds a DT node, 'power_leakage_io', which property,
'leak-gpios', contains GPIOs that have leakage current. In oerder to get
better power consumption, npcx power driver will disable the connections
between these io pads and input buffers before entering deep sleep.
Then, restore the connections after ec wakes up.
The users can overwrite this property at board DT file. Here is an
example:
&power_leakage_io {
leak-gpios = <&gpio0 0 0
&gpiob 1 0>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL configures low-voltage (1.8V) detection via GPIO driver with
GPIO_VOLTAGE_1P8 flag. It also adds support for this flag in
pin_get_config() function.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Cleanup npcx low-voltage (1.8V) detection configuration. It removes
unused soc utilities, macros, and DT node. We will configure this
feature by GPIO driver with GPIO_VOLTAGE_1P8 flag later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
ITE EC chip it81202 and it81302 both have embedded integrated
pd module (support two usbpd ports), this is different from
standalone TCPC. To prevent cc pins leakage, we disable not
active ITE USBPD port cc modules, then cc pins can be used
as gpio if needed.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Move the RX (MISO) delaying capability information to Devicetree. It is
done using 2 properties:
- rx-delay-supported: enabled on SPI nodes that support delaying RX.
This property can be used by the driver to determine if this
capability is supported or not on a given instance.
- rx-delay: the actual RX delay value
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Specify the overrun character in Devicetree. Since 0xFF is the most
common value, DT property contains such default.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Devicetree is the natural place to describe hardware, so move the
maximum frequency the SPI can work with to Devicetree instead of relying
on values from HAL.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some panels using this driver don't provide tcon/cdi/pwr/softstart
values in their reference code. It is normally expected that the right
values will be loaded from OTP in such cases. Make these values
optional to support such panels.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Introduce a generated Kconfig.dts that sets a Kconfig symbol for
every compatible.
* We set DT_HAS_<compat>_ENABLED if the devicetree has a node with
<compat> enabled. (status is okay...)
We can then use the Kconfig symbol in driver Kconfig to determine
if the driver should be available, and thus enabled by default.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
Add configuration for SPI connected ADXL345 accelarator sensor
as adi,adxl345-spi.yaml.
Rename original adi,adxl345.yaml that configured for I2C
rename to adi,adxl345-i2c.yaml.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Implement support for SAMR34 and SAMR35 parts, tested on a SAMR34
Xplained Pro dev board. Confirmed operational peripherals: UART, GPIO,
PWM, ADC.
NOTE: The SAMR34 datasheet lists NVIC line 20 for the ADC's interrupt,
but the SAML21 datasheet gives line 22. It appears that the SAMR34 sheet
is incorrect (the ADC doesn't function with line 20), and as such, I have
also omitted the adjustments for TC4 and AC...
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Implement support for SAML21 parts, tested on a SAML21 Xplained Pro dev
board. Confirmed operational peripherals: UART, GPIO, PWM, ADC.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
The built-in USB serial peripheral is a virtual serial and does not
allow to be configured like a normal UART.
Removing the unused UART config parameters.
Also reducing initialization to single-instance only.
Signed-off-by: Martin Jäger <martin@libre.solar>
Remove 'label' property from SDHC nodes. We can use variants of
DEVICE_DT_GET to get access to a device pointer for use in an
application.
Signed-off-by: Kumar Gala <galak@kernel.org>
The 'nxp,imx-flexspi-device' compatible that was specified in
the YAML file is not an actual compatible that is intented to be
used. Instead the YAML file is included in other YAML files
that set specific compatible.
If the 'nxp,imx-flexspi-device' was used we'd actually get an error
from edtlib because of having the same compatible specified by
two different YAML files.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
Clean up unused psl functions in scfg.c, unused DT macros, unused psl DT
nodes and related yaml files. Currently, PSL pad configurations are made
by pinctrl mechanism. Please refer
https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add adsp-imr binding. This memory type is being used in intel adsp dts
but this binding was missing.
Co-authored-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
All in tree device drivers on a bus use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
Add simple clock control node in devicetree for beetle to handle
relationship between drivers (uart, timers, gpio) and clock controller
device.
Signed-off-by: Kumar Gala <galak@kernel.org>
Use DT_INST_FOREACH_STATUS_OKAY to reduce duplicated code for each
instance.
We make interrupts optional since they aren't always available.
Signed-off-by: Kumar Gala <galak@kernel.org>
Replace sensor_label property in devicetree with just a sensor phandle
property. This is more generic and allows driver to use DEVICE_DT_GET
instead of device_get_binding.
Signed-off-by: Kumar Gala <galak@kernel.org>
Add counter nodes to timer nodes in dts of stm32l4 series.
This should enable the support of the basic counter API
on all stm32l4 mcus for general-purpose and basic TIMx timers.
Signed-off-by: Jan Kablitz <kabeljant@gmail.com>
Fixes configured DMA direction for HDA link in/out drivers.
Adjusts the number of channels for link in/link out to safe value
that seems to work on all tested parts.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
- adds properties 'group', 'index' and 'prescaler'.
- updates board's dts to include those properties.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Clean up unused pinmux function 'npcx_pinctrl_mux_configure()' and
related 'NPCX_DT_IO_ALT*' macro functions.
Please refer https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Switch from using a driver-specific, compile-time devicetree one-shot
property to supporting the newly added CAN_MODE_ONE_SHOT flag for
enabling/disabling one-shot mode at run-time.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove the support for enabling passthrough mode support for MPU9150
on the AK8975. We don't have a proper MPU9150 driver and the MPU9150
has been EOL. So its highly unlikely this code is being used.
Additonally we remove the device tree binding for the MPU9150 since
we don't have a proper driver for it.
Signed-off-by: Kumar Gala <galak@kernel.org>
CONFIG_SIFIVE_SPI_0_ROM (default y) was an option to disable spi0 if
used to access SPI Flash ROM. However, its design had a problem: it
relied on instance numbers. You had to set status okay for spi0 to make
it work (incongruent with the purpose of the option itself). This patch
makes things simpler: if such SPI0 is not available, simply keep it
disabled in DT. Bindings have been updated to mention this case.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This seems to cause a crash when running tests/boards/intel_adsp/hda and
also causing issues downstream on SOF.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.
Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.
By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add NPCX Power Switch Logic (PSL) DT node which controls the power rails
of SoC to get better power consumption.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces how to configure PSL (Power Switch Logic) pads
properties such as input detection mode/polarity, pin-muxing and so
on via pinctrl mechanism. It includes:
1. Add two pinctrl properties and their enums for PSL input
detection configuration.
psl-in-mode:
- "level"
- "mode"
psl-in-pole:
- "low-falling"
- "high-rising"
2. Add macro functions to get PSL input detection and pin-muxing
configurations from 'pinmux', 'psl-offset' abd 'psl-polarity'
properties.
Here is an example to configure PSL_IN2 as the PSL detection input and
its mode and polarity.
/* A falling edge detection type for PSL_IN2 */
&psl_in2_gp00 {
psl-in-mode = "edge";
psl-in-pol = "low-falling";
};
A device will be introduced later which uses this pinctrl node to
configure PSL input detection settings and how to turn off VCC1 power
rail by PSL_OUT.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This peripheral combines a hardware-based USB CDC ACM serial interface
and a JTAG interface.
It is present in the ESP32-C3.
Signed-off-by: Martin Jäger <martin@libre.solar>
Both idle and suspend states were just being used to set the cpu
idle. That is not necessary, if the pm policy does not find a suitable
power state the kernel automatically calls k_cpu_idle().
This remove unnecessary code and the weirdness of having
min-residency-us set to 0 and other arbitrary values.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Meteorlake support as part of the Intel ADSP family.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
This will add ace compatible DMA driver.
Co-authored-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This adds basic support for the watchdog timer on the RP2040 MCU and
Raspberry Pi Pico development board
Signed-off-by: Jamie McCrae <spam@helper3000.net>
This commit adds support for the ds18b20 1-wire temperature sensor.
The sampling resolution of the sensor can be set in DT.
In case only a single device is on the bus, the driver issues
skip_rom commands. However, in case DT defines several devices,
the driver will use match_rom commands and therefore it is necessary
to set the rom_id of the device via the sensor attribute interface before
being able to sample sensor values.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The zephyr-serial w1 driver introduced in this commit implements
all routines for the w1 api on top of the zephyr serial driver.
W1 bit read, write, and reset operations are executed by issuing
polling zephyr serial byte read and write operations.
The driver should be usable on most platforms in zephyr that have
implemented support for the polling procedures of the serial driver.
As not all serial drivers are implemented exactly the same minor
additional quirks may be needed on some platforms.
The most notable difference of polling serial driver implementations
seems to be that some return immediately from poll_out after the
transmission was started(e.g. STM32) and others wait until
the transmission was completed before returning from poll_out
(e.g. NRF). While this has influence on the timeout, both types
are supported by this driver because the driver waits for a
configurable time period until it terminates the read.
The driver needs an appropriate open drain interface to be able
to communicate with slaves.
In the simpliest case this might be achived by configuring the mcu pins
in open-drain configuration with a (sufficiently small) pull-up to 3V3/5V.
Otherwise an external circuit needs to provide this interface.
Overdrive and Standard Speed modes are supported by this driver.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit introduces a new api for the Dallas 1-wire protocol.
The api includes link functions for read and write operations on
bit, byte, and block level, as well as functions to reset and
lock the bus.
The bus configuration is derived from the device tree and can be
queried using w1_slave_count routine.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This patch is to enhance the uart ns16550 driver to get clock frequency
from clock manager or devicetree if clock_frequency is defined.
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
The default S0S1 drive setting is not suitable for TWI/TWIM pins.
Override it with S0D1 as for some SoCs (e.g. nRF52833) without
this the peripheral will not work properly.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This mirrors #36499 and other PRs that added them for other
architectures.
This silences a large number of dtc warnings due to the missing
property. It seems reasonable to require an address-cells property since
any interrupt controller could be the parent of an interrupt-map.
The only device actually using interrupt-maps is neorv32, and it needs
an address-cells of 2 (since this is the default if none is specified it
worked like that before this change).
While I touched this, I reordered the properties for consistency across
boards, but there's a lot of variance here already.
Signed-off-by: Olof Johansson <olof@lixom.net>
There is no driver or other references to the zephyr,ipm-console
devicetree compatiable. So remove the binding.
Signed-off-by: Kumar Gala <galak@kernel.org>
Add binding for zephyr sdmmc disk device, which uses the SD
subsystem to manage an SD memory card.
Fixes#46410Fixes#46266
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When required, add "st,stm32h7-spi" compatible on stm32 compatible
series (today: stm32h7, stm32mp1 and stm32mp1).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a stm32h7 spi compatible.
This compatible intends to match all SPI hardware blocks that
can be compatible with the one available in stm32h7 devices,
for instance, but not limited to stm32u5 and stm32mp1.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use consistent name for SPI HW block property so applications
using a device tree overlay work transparently.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Use consistent name for SPI HW block properties across Microchip
HW, so applications using a device tree overlay work
transparently.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add MKR header connector that is implemented by Arduino MKR series.
This allows hardware with compatible headers to define the related GPIOs.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Some EFR32 SoCs use a secure element subsystem to manage
security features (i.e., TRNG, secure bootloader or cryptographic
functions).
This driver relies on the SE Manager high-level API provided by Silicon
Labs. The API interacts with the SE subsystem, provides helper functions
to achieve cryptographic operations and ensures that only one operation
is running at a time by using mutexes and semaphores.
Instead of relying on the SE Manager from Silicon Labs, one could
recreate the behaviour of the Manager and put the code in the crypto
driver folder and create a dependency for other drivers using the crypto
manager (e.g., keys, entropy).
I went for the SE Manager API as it is already there and supported by
Silicon Labs.
Tested using the random subsystem.
Signed-off-by: Steven Lemaire <steven.lemaire@zii.aero>
Add the stm32g0 bindings for the HSISYS to be used with the hsi divisor
with a factor programmable from 1 to 128.
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
The definition of the octospi clock source is given
by the DTS node. The default value selects the sysclk
(not pclk) for the alternate clock control.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The definition of the clock source for the 2 octospi
instances is given by the DTS node.
The default value selects the sysclk (not pclk)
for the alternate clock control.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
According to the formulas found in the reference manuals of the SoC
families using the "st,stm32-temp-cal" version of the temperature sensor
(i.e. G0, G4, H7, L0, L1, L4, L5, U5, WB, WL), the temperature is
computed with the following formula:
T = ((TS_CAL2_TEMP - TS_CAL1_TEMP) / (TS_CAL2 - TS_CAL1))
* (TS_DATA - TS_CAL1) + TS_CAL1_TEMP
What is called ts-cal-offset in the stm32_temp driver is therefore the
same value as TS_CAL1_TEMP1. Use it directly instead of defining another
property.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The stm32_temp driver defines the ts-voltage-mv property to determine
the reference voltage of the ADC in the temperature computation. However
this information is already available in the device tree at the ADC
level (even with the same default value). Use it through the ADC API
instead of duplicating the information.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This new DTS Node is defining a ratio for Vbat internal
bridge of monitoring sensor connected
to a ADC internal channel. The voltage reference value
is given by the ADC of the stm32.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Like other temperature or vrefint sensor, the stm32 mcu
also have a Vbat monitoring internal channels on ADC.
Add this entry to the device tree.
The vref is usually 3300mV present on the target board.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
-pin properties, e.g. tx-pin have been replaced by pinctrl. Mark them as
deprecated since old pin configuration schemes will be deprecated in
Zephyr 3.2.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit moves the hardware configuration for ledc
peripheral to the device-tree instead of Kconfig.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
enable swo output for iMX RT 10xx series. SWO pinmux settings are
currently only present for the RT1060 and RT1064
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pin control support for SWO log backend, by creating a new
ITM node for the ARM instrumentation trace macrocell. Add pin control
properties under this node, and refactor the swo-req-freq property to be
defined within this node.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add devicetree node for the pinctrl of the Xilinx Zynq-7000 series. Pinctrl
is set through a subset of the System Level Control Registers (SLCR), which
is accessed through the syscon driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit rewrite renesas R-Car clock driver in order
to be able to support any new SoC easier.
This work is so creating a clock driver per soc alongside a
common driver for all reneasas r-car boars.
- drivers: create a driver per soc
- create a common driver
- create a common header used by soc & common driver
- create a soc specific driver calling for common driver
- dts: use new compatible
- use old yaml as common yaml
- create a new "child" yaml to define the new compatible field
- change compatible in device tree
As in Linux, the driver can support both r8a77951 and r8a77950
SoC's so we decided to name the new driver as in Linux with Zephyr
prefix : "clock_control_r8a7795_cpg_mssr.c".
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
This commit is reworking clock definition in
order to match linux filetree and definition
as much as possible.
- dt-bindings: rework renesas clocks dt-bindings
- regroup renesas related dt-bindings in a folder
- rename renesas rcar common dt-binding to match linux name
- add soc specific dt-binding matching linux name
- soc dt-bindings are defining clocks matching linux names
- dts: use new clocks names
- move clocks definitions in SoC layer for each core clock entry
- driver: use new clocks names
As seen in this commit, we are declaring clocks for "R8A7795" SoC
to match linux names.
Linux is not declaring "R8A77951" SoC specific files because
its also supporting the first H3 SoC version numbered "R8A77950".
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Panasonic's reduced Arduino header is based on the Arduino UNO layout.
The main difference is that some pins are not available due to the
lack of pins on the Panasonic module.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
The STM32H7A3 SoC has 64 kB of ITCM RAM mapped at address 0x00000000.
Tested using zephyr_code_relocate().
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This patch is to enable arm timer driver for Intel Agilex SoC FPGA.
The PPI's interrupt ID will be mapped into the interrupt ID
defined by SBSA in GIC-400 controller.
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
Bindings for Intel HDA now require the buffer alignment property to be
set.
Sets the property to 128 bytes for the common Intel cAVS device tree as
was implied by the tests cases.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Enable statically allocated buffers to determine their buffer alignment
with a device tree property rather than having to find out through docs.
Should save people lots of time.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
In #46480 the st,stm32-fdcan driver was updated to use clock_control to
configure peripheral bus clocks. However, the default clocks property
added to the can1 node of stm32u5.dtsi was not correct.
This correction has been tested on known good hardware which uses the
STM32U5 and FDCAN peripheral.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
Current write block size does not guarantee proper
write operation, what might cause corrupted data.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit unifies the driver initialization for can1 and can2
instances so that a single macro can be used.
Enabling the master clock for can2 as introduced in 8ab81b02 had to
be moved to devicetree in order to have the same CAN_STM32_CONFIG_INST
macro for all instances.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add I2C bus recovery support to the NXP MCUX LPI2C driver. Since the LPI2C
peripheral block does not natively support I2C bus recovery, recovery is
performed using GPIO bitbanging.
Fixes: #42574
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The erase time for a sector differs by a few order of magnitude for the
various SoCs of the STM32H7 family. Declare it in the device tree using
the existing max-erase-time property. For that it is necessary to add
"st,stm32-nv-flash" to the compatible node.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Some flash properties are currently in the individual SoC definitions,
while they are common to the whole STM32H743/753 SoC line. Move them one
level higher.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
h753
Some flash properties are currently in the individual SoC definitions,
while they are common to the whole STM32H7A3/STM32H7B3 line. Move them
one level higher.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Platforms that enable UART_NS16550_ACCESS_IOPORT (the case for ia32)
require reg-shift to be zero. Fix this issue introduced in
4c8a8149de.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The armv8 timer, arm gic, and arm gic-v3-its don't use or need the
devicetree label property. Update the dts bindings to not require it and
remove setting of the label property in dts files.
Signed-off-by: Kumar Gala <galak@kernel.org>
In 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings for
sifive CPUs'), new compat strings for SiFive CPUs were added, but with
riscv prefixes. Vendor-specific compats should just be prefixed with the
vendor, so move that over here.
Fixes: 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings
for sifive CPUs')
Signed-off-by: Olof Johansson <olof@lixom.net>
G4 and U5 series missed clock information in DT. Driver likely worked
because it was using HAL helpers, bypassing the purpose of DT and clock
control drivers. The clocks property is now required in the binding
file.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Adds `four-byte-opcodes` property. When set, then used write and read
opcodes will be converted to 4-Byte opcode.
Doesn't convert erase opcodes yet.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds write opcode (`writeoc`) property. That allows to provide
custom write opcode in the DTS.
Doesn't support OPI mode.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
The driver supported getting register shift from Devicetree, from a
custom definition in SoC headers (fragile) or, it took a default value.
This change simplifies things by making reg-shift property required in
all instances.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The ns16550 flags reg-shift property as optional. In case it is not
supplied, the ns16550 driver relies on a value defined in <soc.h>, or,
by default it takes 4 (shift by 2).
This patch adds the property to all ns16550 nodes, with the following
values:
- 2 if SoC did not have any custom value defined by
UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4)
- If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such
value (4=2, 2=1, 1=0).
These changes will allow simplifying the ns16550 driver.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
- The MX25UM51345G flash is connected to FLEXSPI PortA for
mimxrt595_evk.
- Updated flexspi_mx25um51345g driver to support DTR OPI mode.
- Tested with tests/drivers/flash.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Enable access to the HS_SPI pins(JP26) on the mimxrt595_evk board.
Using DMA mode, tested with spi_loopback testcase.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
WWDG1 doesn't work on STM32H7 because its peripheral clock
is never enabled due to wrong enable bit in RCC_APB3ENR
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
All the gpio drivers are based on devicetree and thus we always set
HAS_DTS_GPIO, thus we don't need this Kconfig option anymore. Remove
uses as its safe to assume DTS is supported for GPIO.
Signed-off-by: Kumar Gala <galak@kernel.org>
All the watchdog drivers are based on devicetree and we dont utilize
HAS_DTS_WDT anywhere so we can remove it.
Signed-off-by: Kumar Gala <galak@kernel.org>
The STM32F723 SoC has 16 kB of ITCM RAM mapped at address 0x00000000.
Tested using zephyr_code_relocate().
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The reserved memory mechanism (sections and regions definition) has been
entirely replaced, greatly extended and made it better by the work done
on the zephyr,memory-region compatible.
Since there is are no actual users, we can remove it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This reverts commit 7f51907fda.
The problem with setting the priority at the highest priority possible
is that when the IPC is under high traffic, the WQ could starve the
scheduler.
Move back to a more sane preemptive priority as default value.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This includes DTS bindings for the Texas Instruments CC13xx/CC26xx flash
controller driver and adds support for it in CC1352R and CC2652R SoCs
DTS files.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Recently OpenAMP introduced the possibility to set the sizes for TX and
RX buffers per created instance. Expose this also to Zephyr users by
using a DT property "zephyr,buffer-size".
For the sake of simplicity use the same DT property to set the buffer
size for both TX and RX buffers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Extends #43119 with PPB and IO values of
`memory-region-mpu`.
That allows MPU region definition with
PPB or IO attributes in the DTS.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
This patch adds DTS properties for using wake-up mode
and the autosleep function to the ADXL362 driver.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Add a pseudo device diver with device tree bindings for coredump.
The device tree bindings exposes memory address/size values to be
included in any dump. And the driver exposes an API to add/remove
dump memory regions at runtime.
Signed-off-by: Mark Holden <mholden@fb.com>
This commit aligns SPIM shim to utilize memory-region property from
nordic,nrf-uarte compatible. The memory-region is not required
property that enables user to specify placement of dma buffers
in memory region. It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
This commit aligns UARTE shim to utilize memory-region property from
nordic,nrf-uarte compatible. The memory-region is not required
property that enables user to specify placement of dma buffers
in memory region. It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Since the introduction of the `zephyr,memory-region` compatible
to create new memory region, drivers can now use the newly defined
region in the DT by using the macro LINKER_DT_NODE_REGION_NAME()
on the node_id to retrieve the region name and possibly allocated data
or variables in that region (or for whatever other use).
This is assuming though that the driver knows in advance the node_id to
reference.
A better approach is to add a new generic 'memory-region' property
that can be used by any driver to reference a region by using a phandle,
so that the driver can use that to retrieve the memory-region of interest.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The ALH is an intermediary device, which acts as a hub and provides an
abstracted support for numerous sound interfaces (e.g. SoundWire).
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
To support both 8-bit and 32-bit Control/Status register variants, register
offsets need to be calculated from device tree.
Updated register data in device tree to the 32-bit CSR variant.
Renamed defines to be similar to other LiteX drivers.
Changed frequencies in clock-outputs nodes, so i2s/litex sample works.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Correct width when accessing LITEETH_RX_LENGTH register.
Also update register data in device tree to the 32-bit CSR variant.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Make driver take register info from device tree so it can work with both
8-bit and 32-bit CSRs.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This sensor is virtually identical to the lsm6dso. The only difference
is the accelerometer ranges are double those of the lsm6dso.
Use the same driver. The difference is detected by using "st,lsm6dso32"
as the first compatible entry, followed by "st,lsm6dso".
An bit flag in the existing accel_range config field is used to check if
the chip is the doubled range or not.
Signed-off-by: Trent Piepho <trent.piepho@igorinstitute.com>
Fix various board fixed-partition definitions where the devicetree cell
has been defined oddly, such as 9 nibbles (which makes no sense since
the cells are 32 bit) or 7 nibbles where all the others are 8.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix PM minimum residency time and exit latency for rt11xx to reflect
actual delays when entering and exiting low power modes.
Fixes#45750
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Set the priority of the wwdg instance to 6
else a build error happens :
static assertion failed: "Invalid interrupt priority.
Values must not exceed IRQ_PRIO_LOWEST"
Signed-off-by: Francois Ramu <francois.ramu@st.com>
LPC55sx6 SOC has NXP Manufacturing Programmed Area(NMPA) stored at
offsets 0x3EC00-0x3FDFF. Correct uuid offset to be within this region.
Fixes#43870
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
All the SPI1,2,3 clock of the stm32h7x mcus
are sourced by the PLL1_Q by default. This must be set
in the DTS to have a valid clock rate calculation.
The pll1_q is divided by the <div-q> property of the pll node.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Config pwm open-drain mode without enabling STORE_REG. This CL
collects all active PWM's base address and related index in an
array. Then, pinctrl driver configs its open-drain mode by
finding the corresponding 'channel' index.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This PR Fixes the Audio PLL Rate Calculation (there was an additional
divide / 8 which is not necessary and does not appear in similar
calculations in example code from the SDK).
Additionally, it adjusts the SAI .dtsi to more correctly configure the
mclk rate, and adds comments specifying what the regististers mean.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
Pinmux is depricated (see #39740) and shouldn't be used anymore
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Pinmux is deprecated (see #39740) so let's get rid of
it's usage for HSDK board.
As we call pinmux only once at init phase we simply do
register setup in platform code instead of pinmux.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
The binding was erroneously changed in commit 988fe8d, which led to
build failures. This commit reverts the change.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add inclusions of header files with devicetree related ADC definitions
to the nRF SoC dtsi files so that those definitions can be used also
for nRF SoC based boards.
Provide definitions of nRF ADC and SAADC analog inputs suitable
for use in devicetree.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Extend the common ADC controller binding with a child binding that
allows specifying configuration of ADC channels.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
On Espressif SoCs, the pin controller is a virtual device.
Pin settings are actually controlled in a distributed way.
Therefore, that node does not belong to the SoC bus.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Add 'inversion-on' property to st7735r.
Issue INVON(21h) command on initializing if inversion-on was enabled.
As a result of this command, the display color is inverted.
Otherwise, INVOFF(20h) will be issued.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add partial pin control support for the imx8mp. Since the UART driver is
not currently enabled, pin control cannot be tested on this platform.
Therefore, only the DTS definitions required to set the pinmux options
are present for this platform, and are not being applied (since
CONFIG_PINCTRL=n).
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add initial pin control support for the A53 core of the imx8mm. Since
the UART console driver is not currently enabled for this platform,
there is no way to test the full pin control enablement. Therefore,
CONFIG_PINCTRL is still not selected for this platform, although the
required DTS definitions and pin control headers are present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8ml8_m7 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for IOMUXC peripheral present
on mimx8mq6_m4 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx7_m4 SOC. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a new header and
compatible binding to handle the different register layout on this SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add pin control support for mcimx6x. The IOMUXC peripheral present on
this SOC is identical to the one used on the iMX RT10xx series, so the
dts bindings are reused.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add the DTS binding for OCTOSPI interface for the stm32 devices
from STMicroelectronics.
This corresponds to a NOR octo SPI flash.
In this config, there is only on NOR-flash device.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx eSPI and host_subs driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx adc driver. Please notice users need to
configure the corresponding pinctrl nodes in 'pinctrl-0' property in the
adc0 DT node. For example, if ADC0 and ADC2 channels are selected for
the application, please add the follwoings in your board DT layout file.
&adc0 {
status = "okay";
/* Use adc0 channel 0 and 2 for 'adc_api' driver tests */
pinctrl-0 = <&adc0_chan0_gp45
&adc0_chan2_gp43>;
pinctrl-names = "default";
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx tachometer driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in ps2 driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in pwm driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in i2c driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in uart driver.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL is the initial version for npcx pinctrl driver and introduces
pinctrl nodes for both IO-pads and peripheral devices for each npcx
series. Users can set pin configuration via these nodes in the board
layout DT file. It also wraps all configurations related to pin-muxing
in pinctrl_soc.h. Regarding the other pin properties, we will implement
them later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The drive-mode property is nRF specific, so prefix it with `nordic,`,
same as the `nordic,invert` property.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Removes label and compatible properties
from the flash section. The properties are
provided by included stm32h723.dtsi.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Removes label and compatible properties
from the flash section. The properties are
provided by included stm32h723.dtsi.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
* Corrects SRAM0 size. The `TCM_AXI_SHARED`
is `000` after reset. That means ITCM
is shared with SRAM0.
* Adds missing SRAM1,2,4, and ITCM
regions.
* Adds label and compatible properties
to the flash section.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Enable pin control for lpc11u6x i2c driver, and remove pinmux usage from
board level DTS files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
convert lpc11u6x syscon clock driver to pin control, and remove all
pinmux usage from driver and syscon dts node.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update pin control driver for lpc11u6x. This SOC does not have a HAL,
so fsl_clock is not available. It also lacks a slew-rate field in the
IOCON register, so this property must be optional.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
switch gpio driver to use pio nodes to configure pin control settings,
and stop using pinmux driver within gpio driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
soc: arm: privilege: add Cyclone V SoC FPGA suppport
Add support for the Intel Cyclone V SoC FPGA (arm Cortex-A9).
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
Since implementation of clock source selection in consumer device drivers
could be achieved without usage of a clock-names property and no
example of usage is provided up to now, remove this property from existing
examples.
Additionally, make it clear in stm32 clock control binding that it is
driver's responsibility to correctly access clock source information
and use it as required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clock sources bindings on F0/F3/G0/G4/L0/L1/L4/WB/WL series.
Due to inconsistencies, some common bindings are now split:
F1 -> F0/F1/F3
L4 -> L4/G4/WB
Update .dtsi files when required
In a first step, allowed sources are limited to already supported
clocks: LSI/LSE/HSI/HSE/MSI/PCLK/PLLCLK/SYSCLK
Support for other clocks such as HSI48, SAIXCLK, ... is left for a
next step.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This new binding allows to work on providing stm32u5 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add STM32 clock mux binding.
Only property of a node using such compatible is to
select a clock input.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
e8e88dea incorrectly changed registers
used in `sys_clock_cycle_get(32|64)` functions.
This commit fixes that.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
This is a follow-up to commit 586e26e8fc.
Add missing `qdec0` node labels in definitions of SoCs that have only
one QDEC instance so that the `HAS_HW_NRF_QDEC0` option is properly set
for them. Use the same pattern as in the WDT case and keep the existing
`qdec` labels for backward compatibility.
Also update validation of base addresses so that both QDEC0/QDEC and
QDEC1 are checked.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the UPLLCK clock for the CAN controller as recommended by the Atmel SAM
E70 data sheet.
Move the configuration of the clock prescaler from Kconfig to devicetree
and limit it to the values recommended by the SAM E70 datasheet.
Fixes: #45012
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
In #45014 the m_can compatible identifier was changed from "m-can-base"
to "m_can-base" while #45216 was being developed. This commit updates
the dts for u5 to the latest format.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Cleaned up the IPC configuration for nRF5340 SoC in Device Tree. This
change fixes the (simple_bus_reg) warning about the missing or empty
reg/ranges property.
This is a follow-up to commit cf6a58d.
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Adds addresses and names for individual CSR registers to device tree.
This way liteuart driver no longer depends on CSR data width being 8
bits.
Also when register names or their number changes, then overlay generated
by LiteX will be incompatible with one defined here.
This should make finding breaking changes easier.
I also appended `_ADDR` suffix to defines, to distinguish them from
normal values like `LITEETH_EV_RX`.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds addresses and names for individual CSR registers to device tree.
This way liteuart driver no longer depends on CSR data width being 8
bits.
Also when register names or their number changes, then overlay generated
by LiteX will be incompatible with one defined here.
This should make finding breaking changes easier.
I also appended `_ADDR` suffix to defines, to distinguish them from
normal values like `UART_EX_TX`.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds addresses and names for individual CSR registers to device tree.
This way timer driver no longer depends on CSR data width being 8 bits.
Also when register names their number changes, then overlay generated by
LiteX will be incompatible with one defined here.
This should make finding breaking changes easier.
I also updated register names to those used in current LiteX and
appended `_ADDR` suffix to defines which lacked them.
Because register `total` was renamed to `value` and `update_total` to
`update_value` I updated variables accordingly as well.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Add support for the fdcan peripheral to the stm32u5 series device tree
include. This can be applied here since (at present) all of the stm32u5
series MCUs have an FDCAN peripheral.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
All DT nodes end up being part of the generated 'devicetree_unfixed.h'
header, wether they are referenced or not. The number of entries in that
file can grow quickly when using pre-generated pinctrl nodes.
Considering <devicetree.h> (file uncluding devicetree_unfixed.h) is used
in lots of places nowaday, not using /omit-if-no-ref/ can lead to
increased build times.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The OpenISA RV32M1 pinctrl groups need a dummy pinctrl node to populate
with pinctrl options at the board level.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This adds the CMOS RTC node to the common devicetree files
for x86. Note that this is not added to Lakemont, as it is
usually used for embedded applications which would not have
CMOS RTC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add DTS binding for Motorola MC146818 compatible Real Time Clock.
This is being used for the RTC/CMOS timer on x86 PC-compatible
platforms.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
cavs15 uses different base addresses for IP blocks than the rest
and thus needs its own configuration in device tree.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add optional PINCTRL support to the Microchip XEC PS2 driver
shared between MEC15xx and MEC172x families.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Comparator will monitor signal though ADC channel, based on
user configuration, callback will be triggered.
This will enable comparator functionality for nuvoton MCU utilizing its
ADC threshold detection feature. Implementation is exported through
sensor trigger API. Use of CONFIG_ADC_CMP_NPCX is required.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
add pin control nodes for LPC SOCs, to be filled with pin control
settings at the board level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In the EC application, the system may jump between two built Zephyr
images when necessary. When jumping from the current image to the other,
the firmware switches the eSPI-related pins to GPIO function at
initialization if define alt1_no_lpc_espi in def-io-conf-list.
It causes the eSPI to reset and breaks the eSPI communication after the
image jump. This patch prevents it by removing alt1_no_lpc_espi from
def-io-conf-list.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The LPC platforms define memory in SRAM blocks that can be
combined to represent larger memory blocks to the CPU. Change
the cpu0 allocation to use SRAM0-SRAM2 for 192K and change
cpu1 to use SRAM3-SRAM4 for 80K.
Signed-off-by: David Leach <david.leach@nxp.com>
The LPC platforms define memory in SRAM blocks that can be
combined to represent larger memory blocks to the CPU. Change
the M4 allocation to use SRAM0+SRAM1 for 128K.
Signed-off-by: David Leach <david.leach@nxp.com>
LPC platforms define multiple SRAM memory blocks that are contiguous
in memory but the zephyr build system doesn't have a method to
specify all the nodes to be used for a CPU's chosen "zephyr,sram"
node. To be able to get full use of memory, sram0 is redefined to
80KB in size.
Fixes#43872
Signed-off-by: David Leach <david.leach@nxp.com>
remove existing SDMMC SPI driver, since it is replaced by the SPI mode
SD host controller driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
with the legacy USDHC driver fully removed from the tree, the
nxp,imx-usdhc binding can now be used for the new SD host controller
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
all in tree SOCs with the USDHC peripheral have now been converted to
use the new SD host controller USDHC driver, so remove legacy NXP disk
USDHC driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
added support for NXP iMX RT600/RT500 to use to SDHC driver, with SD
subsystem. Tested with RT685 EVK
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add SDHC driver implementing spi mode support for SD cards. This driver
implements the standard SD host controller APIs, and sets the host
property "is_spi" to indicate to the SD subsystem the card will be
running in SPI mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add generic SDHC dts binding, as well as DTS binding for NXP USDHC.
Update iMX.RT DTS binding to use USDHC compatible
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Fix the descriptions for the ST STM32 FDCAN devicetree bindings. These
are derivates of the Bosch M_CAN, but they target specific SoC
implementations.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the base Bosch M_CAN CAN-FD controller devicetree binding to
match the product name and the upstream Linux devicetree binding.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Fold the simple bosch,m-can devicetree binding into the front-end
devicetree bindings. The bosch,m-can compatible is not used in Zephyr.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
MCP4728 is a 12-bit, Quad Digital-to-Analog Converter with EEPROM Memory.
Controlled via I2C interface.
Signed-off-by: Marek Janus <marek.janus@grinn-global.com>
In 92d8329d5b a new DT property was introduced to set the WQ priority
of the instance. The fallback value when the property was not present
was arbitrarily set to <0 PRIO_PREEMPT>.
The problem is that this value is actually changing the behaviour for
the code that is not explicitly setting the DT property, breaking in
some cases the existing code.
Move the default value to <0 PRIO_COOP> to give the old code a
consistent behaviour before and after the 92d8329d5b commit.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add a GPIO pass-thru map for accessing the full range (0 to 39) of ESP32
GPIO pins by their datasheet number.
GPIOs 0 to 31 are mapped to gpio0 while GPIOs 32 to 39 are mapped to
gpio1.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This is a follow-up to commit 1a01ca2adf.
Since support for pinctrl has been added to the qdec_nrfx driver,
the related binding can no longer require the `a-pin` and `b-pin`
properties to be defined.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add DT option to configure the data ready interrupt mode.
Latched is the default; pulsed can be enabled through
the drdy-pulsed DT, if desired.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Add FDS (Filtered Data Type Selection) + High-Pass reference mode support
(FDS in CTRL6, HP_REF_MODE in CTRL7)
Values are configurable through DT per instance.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
fvp-baser-aemv8r has four pl011_uart devices and all of then have
been added in this patch.
only uart0 and uart1 are enabled as default in fvp_baser_aemv8r.dts
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
STM32WB55xG MCUs include 256 KiB of SRAM split into three banks.
The size of the main bank is 192 KiB, and not 96 KiB as it was
specified in the device tree. This commit fixes the issue and
also updates the definition of the NUCLEO-WB55 board, based on
a STM32WB55RG MCU.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
The PWM period cell will soon be required by the pwm_dt_spec facilities,
this patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The binding has no corresponding driver and it is not referenced
anywhere, so drop it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The binding did not define the PWM cells. Only channel and period have
been added as they are the minimum required ones (flags are not supported).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The PWM period cell will soon be required by the pwm_dt_spec facilities.
This patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to be consistent with other platforms, include the PWM
dt-bindings by default.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The PWM period cell will soon be required by the pwm_dt_spec facilities.
This patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The period cell will soon be required by the pwm_dt_spec facilities,
this patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to be consistent with other platforms, include the PWM
dt-bindings by default.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The PWM period cell will soon be required by the pwm_dt_spec facilities,
this patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The period cell will soon be required by the pwm_dt_spec facilities,
this patch adds it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Include the PWM dt-bindings by default, so that boards can use utilities
like PWM_MSEC() without extra includes. This is a common pattern done
for e.g. i2c or gpio.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The period cell will soon be required by the pwm_dt_spec facilities,
this patch adds it. Note that flags have not been added as they are
optional and not supported anyway.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Introduce has-interrupt-mask-reg DTS property for nxp,pca95xx driver.
This additionnal property allow to specify that the gpio expander has an
interrupt mask register that must be configured by the driver.
This allow to use this driver with PCAL95xx.
This fixes issue #44834.
Signed-off-by: Xavier Chapron <xavier.chapron@stimio.fr>
In order to be consistent with other platforms, include the PWM
dt-bindings by default.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
NXP LPUART IP supports loopback mode, where TX is internally connected
to RX input. Allow setting loopback mode up via the "nxp,loopback" dts
property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Align the board dts with the recent changes in the "nordic,nrf-sw-pwm"
binding (remove the no longer existing `channel-count` property) and
add a node representing the edge connector for convenient referring
to SoC pins connected to it.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... and "nordic,nrf-pwm" binding:
- use channel indexes instead of pin numbers in `pwms` properties that
define PWM LEDs
- add the period and flags cells to `pwms` properties in all PWM LED
definitions; use the commonly used period of 20 ms (giving 50 Hz)
as a default setting
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... to align with what is used in most other PWM bindings.
Update PWM nodes in SoC .dtsi files accordingly.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Align with other PWM drivers and treat the `pwm` parameter (described
ambiguously as "PWM pin") of the `pwm_pin_set_cycles` function as a PWM
channel, not an SoC pin. This will also make the driver consistent with
the `pwm-cells` property definition in the "nordic,nrf-sw-pwm" binding
and with related `DT_PWMS_*` macros.
The change described above requires also providing a way to specify
SoC pins that are to be assigned to the PWM channels. Hence, the commit
introduces in the "nordic,nrf-sw-pwm" binding the `channel-gpios`
property that replaces the `channel-count` one.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Rework bindings documentation to clearly illustrate the role of ahb
(and cpu1) prescaler which defines the actual core clock frequency,
and not only a bus frequency.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use enum to describe the range of allowed MSI values.
This will help to detect configuration issues earlier.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On some parts, it could be required to use steps before applying
highest frequencies.
This was previously done as part of LL_PLL_ConfigSystemClock_FOO
utility functions which are no more used.
Use device tree to mention when this is required and implement it
in stm32_clock_control_init().
Additionally, fix the calls tp LL_RCC_SetAHBPrescaler, which require
use of ahb_prescaler helper.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Introduce a new scheme to define clock bingings on u5.
In a next steps, this new scheme will allow to provide u5 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This new binding allows to work on providing stm32h7 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The pinctrl support made usage of the 'peripheral'
property no longer required.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
those bindings are no more needed since pinmux was
deprecated in favor of pinctrl.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
to support implementation and peripheral usage of the pinctrl
driver API.
Removes deprecated "use-iomux" property from the SPI node.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
After pinctrl's subsystem support, I2C pin properties are
no longer required for pin muxing, however, this information
is still valuable in an eventual FSM failure if the target
SoC has no harwared mechanisms to support bus recovery.
In this case, bus recovery uses pin information to restore
the I2C bus state.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Adds hda link in and out drivers. The link in and link
out channels of HDA have small differences
with the host channels. Updates the existing
cavs_hda drivers and code to account for these
differences.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
all the consumers of the obsolete pinmux driver is
updated to use pinctrl API, this commit removes
the pinmux driver and assosciated sections.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
This commit has the necessary changes to update the consumers
of pinmux driver(SPI, I2C, UART) and update the board specific
files to use the pinctrl interface.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Add pinctrl driver for CC13XX/CC26XX family of SoCs
to facilitate transition from pinmux to pinctrl.
`IOCPortConfigureSet()` from TI hal driverlib used to
implement the generic pinctrl driver.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
LPTIMER has a different `countermode` meaning.
We shall exclude introduced property from lptim bindings.
Alternative property (e.g. `external-mode`) can be added
later on to support external counter mode.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
This PR fixes up the Scatter-Gather EDMA mode for the MCUX EDMA Driver,
as well as enabling the dma reload feature for the same EDMA Driver.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
This commit adds a flash_controller node for the stm32u5 soc family
blocks of 8K and erase time given by the Datasheet (with margin).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduces H7 FMC bindings with support for
memory remap or swap configuration.
The following values are supported:
* disabled - default mapping (reset state).
* sdram-sram - swaps the NOR/PSRAM and SDRAM banks.
* sdramb2 - remaps SDRAM bank 2.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
the icm42670 from Invensense/TDK is a 6-axis accelerometer with
gyroscope and temperature sensing capabilities.
this initial driver does not support the devices 2K FIFO or many of the
other advanced features. Instead, only basic features are implemented.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@escolifesciences.com>
Extend Altera Jtag Uart driver support without Altera HAL driver
by default. uart_altera_jtag_hal.c renamed to uart_altera_jtag.c and
new config, CONFIG_UART_ALTERA_JTAG_HAL is introduced to allow driver
to use Altera HAL driver when needed.
Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
Add the period cell to GD32 PWM compatible and update all boards
accordingly. A period of 20 ms (50 Hz) has been set for all PWM LEDs.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
STM32 supports now custom PWM flags, include them by default as done for
the standard flags.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
add soc level pinctrl node to LPC55s6x DTSI file, to be populated with
pin groups at the board level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rather than specify input clock for each peripheral individually, instead
specify the relevant clocks in DTS.
This will enable easier support for non-default coreclk on fe310 in a
follow-up CL.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
Currently the only way for a BOARD/SOC to configure at compile time the
MPU regions is to add, in a soc-specific file, the 'mpu_config' struct
adding static entries for the new regions with the needed attributes
(cacheable, non-cacheable, etc...). This exported struct is then read by
the MPU driver at boot time and used to properly setup the MPU regions.
At the same time it is now possible to introduce new memory regions in
the DT using the newly introduced 'zephyr,memory-region' attribute.
What is missing is the link between these two solutions: that is how to
declare the memory regions in the DT and automatically configure these
regions in the MPU with the correct attributes.
This patch is trying to address exactly this problem.
It is now possible to declare the memory regions in the DT and define
the MPU attributes for the regions using the 'zephyr,memory-region-mpu'
property. When this new property is present together with the
'zephyr,memory-region' property and a the 'zephyr,memory-region'
compatible, the 'mpu_config' struct is automatically extended at
compile-time to host the DT defined regions with the correct MPU
attributes.
So for example in the DT we can now have:
sram_cache: memory@20200000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20200000 0x100000>;
zephyr,memory-region = "SRAM_CACHE";
zephyr,memory-region-mpu = "RAM";
};
and a new region will be created called "SRAM_CACHE" and a new MPU
region will be configure at boot time with the attribute
"REGION_RAM_ATTR".
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add a new boolean devicetree property `tx-rx-swap` to the
st,stm32-usart binding, used to control TX/RX swap during
device initialization.
Signed-off-by: Alexander Mihajlovic <a@abxy.se>
Add boolean properties to the binding for the nRF RADIO peripheral
to indicate whether the following features are supported:
- IEEE 802.15.4 mode
- 2 Mbps BLE mode
- coded BLE PHY
- high TX power settings
Set these properties appropriately in devicetree radio nodes for all
nRF SoCs.
Add also such properties and set them in appropriate nodes for nRF
flash controllers to indicate whether they support partial erase.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
For consistency with the scheme used for other nRF peripherals,
use the peripheral name that nRF Product Specifications use.
In this case, it is WDT, not WATCHDOG.
Also remove the requirement for the label property in the binding.
It is no longer needed.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add missing devicetree nodes representing the following peripherals
in nRF SoCs:
- ACL
- BPROT
- CCM
- COMP/LPCOMP
- CTRLAP
- DCNF
- MPU (nRF MPU peripheral in nRF51 Series, not ARM MPU)
- MUTEX
- MWU
- NFCT
- OSCILLATORS
- POWER (in nRF51 and nRF52 Series)
- PPI
- RESET
- SWI
- USBREG
Add also corresponding bindings and validation of base addresses of
these nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit cf6a58d3f6.
Restore the "nordic,nrf-ipc" compatible property in mbox nodes for both
nRF5340 cores and use it together with the new "nordic,mbox-nrf-ipc"
one. This way either the MBOX or the IPM driver can be used for these
nodes without further modifications. This eliminates the need to use
overlays in quite a few cases, so remove all those no longer needed
ones (which are also a bit confusing now as they refer to no longer
existing ipc@2a000 and ipc@41012000 nodes).
Restore also the ipc node label removed in the commit mentioned above,
as the label is used in validation of base addresses of nRF DT nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Adds an initial driver for HDA streams on cAVS. A common code base is
provided for all HDA streams while the drivers are identified
differently as they have small behavior differences.
Uses dma_status to describe the positions for read/write. Uses dma_reload
to inform when to move the read/write positions. This closely follows
how HDA is being used in SoF
Simple test case is provided for both drivers.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Since the HCI entropy device is a software construct that is able to
provide entropy bytes by retrieving them from a Bluetooth Controller,
generalize it by moving it to the Nordic common DTS code. Additionally
move the chosen nodes from the nRF5340 DK board files to the SoC ones.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add build time optional PINCTRL support to the Microchip XEC TACH
driver shared by MEC15xx and MEC172x families.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Update Microchip XEC TACH driver to support MEC172x.
Standardize device tree properties between chips.
Standardize device structure usage.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Depending on the stm32 mcus and the timer instance, several channels
can enable the complementary output for the PWM signal.
Example of a DTS <&pwm1 2 4 (PWM_POLARITY_NORMAL | PWM_COMPLEMENTARY)>;
Note that the timer channel must support the complementary output
on that channel : usually channels 1-3 + channel 4 on stm32g4x.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Customize busy wait timer for micro-seconds accuracy.
Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_error_case
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_monotonic
west build -p auto -b it8xxx2_evb tests/kernel/timer/starve
west build -p auto -b it8xxx2_evb tests/kernel/context
west build -p auto -b it8xxx2_evb tests/drivers/adc/adc_api
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Add devicetree node for IPC driver so that the IPC interrupt properties
can be accessed with device tree interrupt property macros and
configured using devicetree overlays.
Signed-off-by: Eivind Jølsgard <eivind.jolsgard@nordicsemi.no>
Co-authored-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Follow up on commit 37bf7cb
("dts/bindings: stm32: Set pinctrl-[0/names] properties as required")
Report lack of those fields soon at build to avoid cryptic
DT api build error messages.
Signed-off-by: Maciej Zagrabski <maciej.zagrabski@grinn-global.com>
Instead of having one single WQ per backend, move to one WQ per
instance instead and add a new "zephyr,priority" property in the DT to
set the WQ priority of the instance. Fix the sample as well.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add Nano header connector defined by Arduino. This allows
hardware with compatible headers to define the related GPIOs.
Signed-off-by: Marco Peter <marco.peter@joylab.ch>
Add description for a plain GPIO configuration using
st,stm32-pinctrl and st,stm32f1-pinctrl bindings.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add backlight gpios property to mcux display driver, so that the driver
can correctly initialize the backlight gpio control.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In order for pinctrl support to be complete, RT series GPIO driver must
support pinmuxing within the driver level. RT series pinmux settings do
not correspond directly to gpio port/pin numbers, so use DTS mappings to
pinctrl nodes to select and apply pinmux settings in the gpio driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pinctrl driver for usdhc. USDHC driver uses custom pinctrl states
for fast, slow, and medium signal frequencies, as well as pin pull for
SD detection.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable pinctrl for flexspi driver. Note that when flexspi is being using
in XIP mode, pinctrl settings are not required and will not be applied.
Pinctrl settings are only required when the flexspi device being used is
not the one used for XIP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT11xx series has similar pin configuration peripheral to RT10xx, with
some differences in register layout. Create new pinctrl definition
header file, and reuse existing driver code for RT10xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
iMX.RT parts use a GPR register for some pinmux settings. Update pinctrl
driver to support this GPR register definition.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
OCRAM can be used for DMA, and in this case it should be marked as
noncacheable. Add KConfig symbol and appropriate linker scripts to
enable OCRAM region to be defined as noncacheable, and initialized with
data from flash at boot.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This update Atmel sam and sam0 ethernet gmac and mdio drivers to use
pinctrl driver and API. It updates all boards with new pinctrl groups
format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This add support to pinctrl at Atmel sam0 rtc driver. It allows to
define pins to be used for tamper detection.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This add support to pinctrl at Atmel sam0 dac driver. It updates all
boards with new pinctrl groups format and drop pinmux entries.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This add support to pinctrl at Atmel sam0 usb dc driver. It updates
all boards with new pinctrl groups format and drop pinmux entries.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This add support to pinctrl at Atmel sam0 tcc pwm driver. It updates
all boards with new pinctrl groups format and drop pinmux entries.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This add support to pinctrl at Atmel sam0 i2c driver. It updates all
boards with new pinctrl groups format and drop pinmux entries.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This add support to pinctrl at Atmel sam0 spi driver. It updates all
boards with new pinctrl groups format and drop pinmux entries.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam0 serial drivers to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update current Atmel sam0 pinctrl initiative to current Zephyr
pinctrl API. It update current devicetree bindings and add the sam0
pinctrl driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam qdec sensor driver to use pinctrl driver and API.
It update board and sample with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam pwm driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format. In addition this
remove all remaining manual pinmux at board level.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam canfd driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format. In addition this
add missing entries to run automated tests for can/canfd drivers.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam ssc driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format. In addition this
remove DEV_NAME macro at sam xdma driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam afec driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format. In addition, it
add overlay files to allow run samples/drivers/adc example.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam usb drivers to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam counter driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam i2c drivers to use pinctrl driver and API. It
updates all boards with new pinctrl groups format. This add missing
i2c-0 alias into sam4l_ek board.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam spi driver to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Atmel sam serial drivers to use pinctrl driver and API. It
updates all boards with new pinctrl groups format.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update current Atmel sam pinctrl initiative to current Zephyr
pinctrl API. It update current devicetree bindings and add the sam
pinctrl driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Enable the alt function with setting both bit5@0xf016f1 and
bit6@0xf02046 bits will cause internal leakage.
Only bit6@0xf02046 bit is required to enable the alt function,
so fix it.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit makes the transition from the pinmux driver to the pinctrl
driver. It also modifies UART, SPI and I2C drivers used in FE310-based
boards to use the new pinctrl API.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The PLL div-p for the stm32g4x has more possible value than stm32l4
possible ra nge is from 2 to 31
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Adds an entropy driver that uses Bluetooth HCI commands as its source
of randomness. As this method is blocking, the ISR API is not supported.
As this method will range from relatively slow (same core Bluetooth HCI
controller) to extremely slow (UART HCI Bluetooth controller), use the
xoshiro PRNG by default for RNG generation.
Implements #37186
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
added bindings for vnd,reset used for devicetree test reset
added adc temp sensor as supporting reset
Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
added bindings and compatible for reset controller nodes
added bindings for devices that use the reset controller
Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
Aspeed ast10x0 series SoCs contain a ARM Cortex-M4F processor. This
processor operates at 200MHz and executes on SRAM.
This patch adds support for ast1030 as the first SoC of this series
which is targeted but not limited at the bridge IC in a server system.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I668af1ff8a36a05da791c3329ae08f5ae712bdd4
the tlc5971 driver uses spi for controlling the global brightness
and individiual pixel brightness of a daisy chain of tlc5971
devices.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@escolifesciences.com>
If a user has a 1GB external flash it is currently not possible
to configure this through DTS. To allow for such a configuration
we add an option which specifies the size in bytes not bits.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
This commit adds ipc backend, that relies on simple
inter core messaging buffer also added by this commit.
This backend is configurable with DT overlay. Each
ipc instance could be defined with ipc-icmsg commpatible.
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
Enable pinctrl for ethernet mcux driver, and update kinetis DTS node to
include labelling for PTP node, to enable driver to access pinctrl
properties.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
kinetis pinctrl driver had swapped values for slew rate
(fast slew rate should set bit to zero). Fix slew rate values.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
- Move the SX oscillator control pins to a regulator node
- Create a board level compatible for the RF switch
- Use gpio_dt_spec to simplify board pins.c (now rf.c)
- Cleanup include list
For reference:
https://downloads.rakwireless.com/
LoRa/RAK811/Hardware_Specification/RAK811_HF_Schematics.pdf
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add build time optional PINCTRL support to common PWM driver
for Microchip XEC MEC15xx and MEC172x families.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add support for MEC172x series to Microchip XEC PWM driver.
Standardize device tree properties for both SoC families.
Standardize device structure usage.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add the Vref reference voltage in the DTS, so that the adc driver
can retrieve the value for conversion.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
As mentioned in #42882, the I2C of IT8XXX2 is designed for two different
IP blocks, so this PR divides this I2C driver into two compatibles.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The datasheet for both sam4s/same70 specifies that the NRST pin
is an input after reset, used as a user reset.
Add the user-nrst property to match the default.
Fixes#43306
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Adds 'swj-cfg' property to the F1 pinctrl. It is an optional
property that allows to control Serial Wire JTAG
configuration.
Different configurations allow to free certain IO
pins that can be used in remap or standalone.
That replaces previously used Kconfig approach.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
This contains accessor macros for getting the maximum bitrate supported
by a CAN controller/transceiver combination.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add generic devicetree bindings for simple CAN transceivers.
Always-on CAN transceivers are considered passive and just provide a
maximum supported bitrate.
Active CAN controllers can typically be controlled by the MCU via either
SPI, I2C, or GPIO. Common GPIO controlled CAN transceivers provide
either a stand-by or an enable pin (or both) for controlling the state
of the CAN transceiver.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for the new pinctrl API to the nRF PWM driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF QDEC driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF QSPI NOR flash driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for configuring pins to be used by the nRF PWM, QDEC, and
QSPI peripherals.
A new custom property "nordic,invert" is added to the pin configuration
group binding to allow configuring PWM channel outputs as inverted.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the DMIC driver that handles
the nRF PDM peripheral. Update code of the driver and the related
devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF I2S driver. Update code
of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Bindings for the Xilinx Processor System GPIO controller, both for the
parent controller device as well as the GPIO pin bank child devices.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add the parent controller device node plus the child nodes for all
GPIO pin banks managed by the GPIO controller to the device trees
of the Zynq-7000 and ZynqMP SoCs.
Device base addresses, IRQ lines, number of banks, number of pins
per bank and bank descriptions taken from the Zynq-7000 TRM (Xilinx
document ID ug585), the Zynq UltraScale+ TRM (Xilinx document ID
ug1085) and the Zynq UltraScale+ Devices Register Reference (Xilinx
document ID ug1087, web-based document).
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
add dtsi settings for rt series
dtsi use gpr to replace pinmux
nxp iomuxc has gpr which has more settings than mux and io settings
current solution is to export gpr separately and access then directly
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add dts binding for rt1xxx pinctrl driver settings. A binding file is
present for the pinctrl node itself, and for the pinctrl child node that
defines all pinmux options
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce ADC properties which indicated if the ADC instances have
dedicated channels for the internal temperature sensor or voltage
reference.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Don't set AFIOEN when enabling IO port clock.
The bit is set upon requirement within pinctrl
or pinmux
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
RT11xx USB PLLs source from 24MHz XTAL oscillator. Add this oscillator
as a clock source for the usb dts entries for the RT11xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This macro expands to DT_STRING_TOKEN if property exists, otherwise
falls back to default value.
Helpful when a non-required enum binding doesn't mention a default
value, but a default value makes sense to be set in the code.
Including DT_INST_STRING_TOKEN_OR and test code.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
rename IMX_CCM_UART_CLK to IMX_CCM_UART4_CLK and
IMX_CCM_UART2_CLK a53 dtsi.
This was missed in a previsous patch set.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for the new pinctrl API to the I2C drivers that handle
the nRF TWI and TWIM peripherals. Update code of the drivers and
related devicetree bindings.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the SPI drivers that handle
the nRF SPI, SPIM, and SPIS peripherals. Update code of the drivers
and related devicetree bindings.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add power management code for the RT10xx SOC. By default, the code will
simply gate the core clock and transition the SOC to WAIT mode when
sleeping, but if clocking hooks are register to reduce clock frequencies
these will be called as well, and the SOC core voltage will be lowered
for additional power savings.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
1. Check I2C Clock and Data is high through GPIO driver instead
of the I2C bitbang registers
2. i2c_xec_poll_write() and i2c_xec_poll_read() will poll to
check I2C clock and data lines are high before initiating the
transaction. The polling will be every 25us for a cumulative
max of 2.5ms
3. wait_completion() will not call recover_from_error() to reset
the controller. Instead will poll for 10ms for the PIN bit to
clear before returning error.
4. wait_completion() will send STOP if the 9th bit is NACK
5. If any errors with current transaction:
(a) Set error_seen flag.
(b) In the next transaction do the recovery process (reset the
i2c controller) if the clk and data lines are high.
Note: error_seen flag is set for Address NACK with Repeated
Start as well.
6. If timeout error occurs in wait_completion():
(a) Set timeout_seen flag;
(b) Wait till the slave will release the clock.
(c) Once slave releases clock send STOP on the bus. If the
timeout occurred while master read, read the I2C DATA register
for the hardware to proceed.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Since we are moving to pinctrl, removing pinmux.c
from mec172x board folder and removing pinmux from dts
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Allow movement detection to be used on hardware
that only has one interrupt line connected.
Change hardware configuration to a bitmask.
Signed-off-by: Andrew Hedin <andrew.hedin@lairdconnect.com>
The ADC driver of IT81302 chip can support channels 0-7 & 13-16.
This PR adds to implement ADC channels 13-16.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
SOC specific wrapper files were used to include pinctrl DTSI files.
Remove these in favor of including pinctrl header files directly from
board pinctrl definitions.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Kinetis pinctrl groups need dummy pinctrl node to populate with pinctrl
options at the board level. Add one in each
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The dma nodes in device tree were entirely copy pasted. Rather than
doing that lets create a common intel_cavs.dtsi each specialization
then includes. This dedups the lpgpdma entries.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The Bluetooth HCI driver based on the RPMsg transport now uses the IPC
service module. The compatible Bluetooth sample - HCI RPMsg - has also
been migrated to the new IPC solution.
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Add zephyr,memory-region compatible to SRAM1 nodes. These memory
regions are dedicated to the USB device controller for USB descriptors.
Fixes#43090
Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
Previous Kconfig designated designware dma but did not define
the ip block in device tree. This caused warning when building tests.
The warnings caused CI to fail.
Really though the devices do all depend on the gpdma derivative and not
the generic DesignWare driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This is a slightly higher level Zephyr device that manages the host
IPC device for applications. There's an interface to make synchronous
and asynchronous calls, to receive commands via (interrupt context)
callbacks and emit async "done" notifications after processing is
complete. It should work for pretty much any application
architecture.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
the stm32h725 family is mostly identical with the stm32h723 family with
the exception that the h725 family has an in-built SMPS.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@escolifesciences.com>
Add the 256 kB On-Chip memory area which is located at 0xfffc0000.
In conjunction with a corresponding 'chosen' entry at the board level,
equivalent to board device trees based on the Zynq-7000, explicit placement
of data in the OCM becomes possible, for example when setting up the GEM
Ethernet Controller's DMA area.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add a new hwinfo driver to get the reset cause on
SAM4S/SAME70/SAMV71 SoC series.
The user-nrst dts property has been added to enable external user
resets.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Add a new board to support Intel Tiger Lake H PCH variant of cAVS2.5.
Move common Kconfig options for cavs25 to soc level. No need to
replicate these for every board.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Unify the CAN controller configuration done in Zephyr devicetrees:
- Specify a resynchronization jump width (sjw) of 1 time quanta in SoC
devicetrees as this is the most common. Boards can override this if
needed.
- Specify a sample point of 87.5% as recommended by CAN in Automation
(CiA) in SoC devicetrees. Boards can override this if needed.
- Specify a bus speed of 125 kbits/second (arbitration phase) and 1
Mbits/second (CAN-FD data phase) in board devicetrees as this is what
is used by all Zephyr CAN samples.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit implements the temperature sensor interface for
the Maxim MAX31875Low-Power I2C Temperature Sensor.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
Properly set both pull up and down flags explicitly when
making changes.
Properly implement disabling interrupts on a given pin.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
In nRF53 family of SoCs, GPIO pins must be explicitly forwarded by the
application core to the network core if the latter should drive them.
Add a binding of a generic GPIO pin forwarder.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
The driver was never migrated to Devicetree, this patch converts the
driver to a proper Devicetree based device.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The current MCUX IGPIO driver assumes that the target SoC supports
the DR_SET, DR_CLEAR, and DR_TOGGLE functionality, but some do not
(namely, the M7 core of the i.MX8M Plus SoC). Current releases of
the MCUXpresso SDK IGPIO driver contain utility functions to set,
clear, and toggle pins which include provisions to support SoCs
with and without DR_SET, DR_CLEAR, and DR_TOGGLE, and this change
switches to using these utility functions.
Additionally, this change enables GPIO support on the mimx8ml8_m7
target.
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
This adds support for the ads101x (ads1013, ads1014, ads1015) and
ads111x (ads1113, ads1114, ads1115) family of i2c adc devices.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
Introduce a new "zephyr,memory-region" compatible to be used when a new
memory region must be created in the linker script from the devicetree
nodes using the compatible.
Remove also the LINKER_DT_REGION_FROM_NODE macro and add a new
LINKER_DT_REGIONS macro to cycle through all the compatible regions.
In the same PR modify the DTS files and the linker scripts.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This enables the below configuration so the AP and EC are able to
communicate over eSPI:
CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
The last 2k bytes of the data RAM is used by the booter in some npcx EC
chips. This commit adds a bootloader_ram DT node to describe this
additional layout of the RAM. As a result, we can determine the total
RAM size by adding the size of flash0, sram0, and bootloader_ram.
Also, this commit moves 64k bytes from the code RAM (flash0) to the data
RAM (sram0) for npcx7m7fc because its internal flash is 512K bytes.
(In the Chromebook application, we need the code RAM size <= half of the
flash size.)
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The application may not always use the PSL mode. Change the status of
node vsby-psl-in-list default disabled. The application can override it
when it wants to use PSL hibernate.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Intel's adsp needs to set, at a minimum, a clocking bit before the driver
can initialize the designware dma controller. In many ways it is the
designware dmac IP but with additional registers and functionality added
on top of it. So the code structure here follows how the hardware
appears to be designed, layered on top of the designware driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This patch adds GPIO and 96board LS (Low Speed)iexpansion connector
support for SiFive HiFive Unleashed and also enables GPIO basic test.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This is the compatible which is used in the blinky sample, so
it's worth trying to add a better example for what you can do with it
in general in the main description.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Added basic support for the RP2040 SoC. Support
includes booting and starting the kernel, on one
core only.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
As npcx9m3f/npcx9m6f needn't share the upper 2KB of data RAM to Booter,
let's fix the data RAM size from 62KB to 64KB for them.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
the pre-dic is not used in rt11xx series, but for driver compatible
with rt10xx we still need have it in dts
fixing: #42179
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Exposes the RC register so that the initial value can be set in
the device tree. This is useful in the case where the timer
generates an event but an interrupt is not required.
e.g generate event to sample adc on RC register match.
Tested on Atmel SMART SAM E70 Xplained Ultra board
Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
Current uart driver implementation is incompleted regarding the
usage of DT_INST_FOREACH_STATUS_OKAY. If uart0 and uart2 are selected,
build breaks due to peripheral number ordering, which would be
0 and 1 in this case. This fix PR fix this by re-working the macros
and setting proper uart peripheral instances in DTSI, required for signal
routing configuration.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Remove the "cpus" node from the SoC device tree. The Zynq-7000
comes with either 1 or 2 CPU cores. While all the different
models within this SoC family have different capabilities in
particular when it comes to the programmable logic part and
I/O pins, there is no difference between the XC7Zxxx (2 cores)
and XC7ZxxxS (1 core) models when it comes to the peripherals
integrated in the SoC. Therefore, it makes little sense to
add a zynq7000s.dtsi next to the existing zynq7000.dtsi whose
only difference is the CPU count. Instead, the "cpus" node,
containing the appropriate CPU core definitions for the SoC
the respective target is equipped with, shall be specified at
the board level instead.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
Build shows warning due to incompatible
CPU vendor name. This fixes it and applies
necessary changes in files.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Initial implementation of a simple GPIO controlled power domain.
It exposes no API of its own, all functionality is contained inside
the runtime power management callbacks.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add support for power domains on Zephyr. Power domains are implemented
as simple devices so they can use the existent Zephyr API, for resume
and suspend sync and async and also reference count.
The pm subsystem will ensure that domains are resumed before and
suspended after devices using them. For device runtime power
management, every time the device is got or released the same actions
is done to the domain it belongs.
As domains are implemented as simple devices, it is totally acceptable
a domain belongs to another domain.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Adds power state definitions for RT1170. Min residency times are loosely
derived from transition times into similar power states in the datasheet
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds power state definitions for RT1160. Min residency times are loosely
derived from transition times into similar power states in the datasheet
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enables basic power management for the RT11xx series SOCs. The following
power saving measures are currently implemented:
- system reduces core voltage during sleep
- core clock can be gated in deep sleep
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for disabling automatic retransmission of CAN frames
(similar to CAN "one-shot" mode in the Linux kernel).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Pin controller address is the same for all member of the
GEN3 SoC Series, but pinmux configuration is SoC specific.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Renesas R-Car series contains a PFC (Pin Function Controller).
This module consists of registers for selecting the function of
the multiplexed pins and controls the pull-up resistor on each pin.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Remove the unused base binding for CAN bus devices (as in devices
present on a CAN bus). This binding should have been removed in
2269408572
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
On some platforms, HPET is not wired to trigger IRQ 2.
This would make HPET non-functional if the legacy
interrupt routing bit is set in the global config
register. This adds a DTS flag so the driver won't
set the bit to enable legacy interrupt.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fix the interrupt setting in the fvp_baser_aemv8r dts:
- The correct interrupt number is 5, not 0.
- The interrupt priority and type are swapped.
This patch also enables interrupt driven mode for this platform as this
is the ideal setting for a Fast Models based platform.
Issue-ID: SCM-4037
Signed-off-by: Filipe Rinaldi <filipe.rinaldi@arm.com>
Change-Id: Ic4815f5afe4c9df9d8fe373d47d2773d64087c96
dts/bindings/timer/riscv,machine-timer must have compatible name
riscv,machine-timer. nuclei,machine-timer is wrong, correct it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This PR adds the different handling of temperature sensor for the
STM32L5 soc. In this soc, there are some calibration settings which
need to be applied for temperature conversion.
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
The dts binding general rules document states that the property
description should explain why the default value was selected
(e.g. "default is the value at power-on").
See comment in #41143
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add fragment:
io-channel-cells:
- input
to binding of the "ite,it8xxx2-adc" and "zephyr,adc-emul" compatible.
It is necessary to use io-channels property.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Certain stm32 soc's have a single shared irq for all adc channels
on those soc's only a single channel is supported.
Added a Kconfig that enables a shared irq for stm32f2x, stm32f4x,
stm32f7x soc's. The shared IRQ uses a flag to limit the number of
interrupts defined to only 1. A shared irq handler is added which
determines which ADC instance the interrupt is for, it then calls
into the existing interrupt.
Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
The default I2C channel 3 is used by alternate function of GPIO H1/H2
Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the
compatibility of the GPIO F2/F3.
TEST=test on it8xxx2_evb:
zmake configure -b zephyr/projects/it8xxx2_evb/
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
An additional devicetree poperty `single-wire` is added
to uart and usart bindings of stm32. The driver checks this value
during initialization and enables the single wire mode when set.
Signed-off-by: Jonathan Hahn <Jonathan.Hahn@t-online.de>
The leon3 SoCs were missing definitions of the CPU node. This node is
now required for PM, so that power states can be defined.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Better setting a default value there so DT_PROP() will return something
relevant whether the property is set or not.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add timer and pwm nodes. The structure follows a similar approach to the
one used by STM32. Timer nodes store all timer information (e.g.
pre-scaler), whereas the pwm nodes are children of the timer node
indicating a specialization of the multiple timer functionalities.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add timer and pwm nodes. The structure follows a similar approach to the
one used by STM32. Timer nodes store all timer information (e.g.
pre-scaler), whereas the pwm nodes are children of the timer node
indicating a specialization of the multiple timer functionalities.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
HSE clock frequency value depends on target.
It can't be defaulted.
Remove this property to ensure it is set properly for each target.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
NPCX7/9 has a different ADC register structure. NPCX7 has 3 threshold
detectors from offset 0x14 & has 10 input channels. NPCX9 has 6
threshold detectors from offset 0x60 & has 12 input channels.
This commit fixes the NPCX ADC register structure.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Kconfig options will anyway enable/disable the driver relevantly.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Assign unique memory-region attribute values for both OCM
memory areas so that the lower region starting at address 0
is identified as OCM_LOW, while the alternate location for
the OCM memory is identified as OCM_HIGH.
The updated linker command file will use those identifiers
for OCM section mapping based on which of the two OCM areas
is marked as 'chosen' at the board level.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
YAML description file for the On-Chip Memory of the Xilinx
Zynq-7000, DT identifier "xlnx,zynq-ocm".
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
- The gpio dt-bindings were not included
- gpio-controller property was not present in gpio nodes
- number of gpio cells was not present in gpio nodes
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
- The gpio dt-bindings were not included
- gpio-controller property was not present in gpio nodes
- number of gpio cells was not present in gpio nodes
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT node for EXTI (External Interrupt Controller). Only line
interrupts added for now (used for GPIO interrupts).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT node for EXTI (External Interrupt Controller). Only line
interrupts added for now (used for GPIO interrupts).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The spi-bus-width property provides information if the target system
has all SIO[0123] pins connected to NOR flash memory.
It must be equal to 4 to enable QSPI 4 IO operation.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Some flash memories connected to QUADSPI IP block on stm32[fh]7 devices
require proper reset pulse before configuration.
This patch adds two new properties - the 'reset-gpios' phandle,
which allows specifying GPIO pin for RESETn pulse and
'reset-gpios-duration', which provides the time (in ms) for reset
duration.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The 'flash-id' property defines the number of QSPI's dedicated GPIO
bank (and flash ID), which will be used to communicate with flash
memory.
For example, on stm32h7xx it is possible to use 'quadspi_bk1_*' and
'quadspi_bk2_*' set of pins, so one may need to select between them
when required.
By default - pins from 'quadspi_bk1_*' bank are used, so the
'flash-id = <2>;' property, when your use case (e.g. PCB design)
requires it, forces usage of 'quadspi_bk2_*' pins.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Now in Zephyr only stm32f7 processors have by default provided support
for QSPI IP block.
The same IP block is also available in stm32h7 (with different offsets),
so proper DTS description shall be provided as well for it.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In npcx_itim_evt_isr, it updates the cyc_sys_announced variable and
then calls sys_clock_announce() to update the kernel curr_tick variable.
If an ISR handler with higher priority preempts the timer ISR after the
sys_clock_announce is updated and before the sys_clock_announce() is
called, it will read the wrong time when calling k_uptime_get() because
the cyc_sys_announced and the curr_tick are not synchronized.
The commit fixes the problem by raising the timer's interrupt priority
to the highest one (i.e. 1 in npcx's configuration).
This commit also moves the computation of the delta cycle inside the
spinlock in sys_clock_elapsed() to prevent another potential racing
condition.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Convert the CAN loopback driver from being configured via Kconfig to
multi-instance configured via devicetree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The syscall_perf test cannot be built successfully due to region RAM
overflow on qemu_riscv32_xip and hifive1_revb. The dtim is only 16KB,
To reduce the main stack size to make it can be built successfully.
Base on the spec(fe310-g002-manual-v1p1.pdf), the size of itim should
be 8KB. Modify the definition in its DTS file.
And it also fix some of the gcc warning when testing it by twister.
This PR partially fixes#41399.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
The vnd,gpio-device compatible is now used by the test GPIO driver
(CONFIG_GPIO_TEST) introduced in #41387. This means that we can't define
new devices with this compatible when CONFIG_GPIO=y.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The pinsN group name can be a confusing in some circumstances, so change
it to groupN. Some platforms (e.g. nrf or gd32) are already using
groupN. Documentation and API tests have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
If there are no console messages input at an interval of 15
seconds, the system will be able to enter suspend mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
So far driver was using SENSE mechanism for all or none edge
interrupts. This was not convenient since in some modules may
require IN event to be used and other did not. Converting it to
use a mask specified in the device tree. Pins indicated in the
mask will use sensing.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add a new DT property named "pixel-group-size" that allows users to
configure the driver to refresh the matrix by illuminating multiple
LEDs in particular rows simultaneously. This way the maximum possible
brightness of the LEDs can be increased (as they can be lit longer)
and the timer interrupt handler is executed less frequently, what
results in decreased CPU load, but more GPIOTE/PPI channels needs to
be allocated if the PWM peripheral cannot be used. Thus, it is left
to users to select the configuration that suits them best.
Update definitions of both the bbc_microbit boards with this new
property, using the maximum available group size (to achieve maximum
possible brightness). For v2, no new resources are used (only all
channels in the already used PWM peripheral are now utilized).
For v1, two more GPIOTE and PPI channels are allocated.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Some STM32 series need to configure health test register
for proper RNG behavior.
In addition, some also require to write a Magic number
before writing the configuration.
Note: on stm32h7 not all product lines support this configuration.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Some STM32 series need to configure health test register
for proper RNG behavior.
In addition, some also require to write a Magic number
before writing the configuration.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
- Supporting multiple instances of ivShMem virtual devices.
- Introduces DT based configuration for ivShMem devices.
- Add DTS overlay file to test new multiple ivshmem instance capability.
- Enable BDF unspecified device initialization.
(limited to one instance. An improved version of pcie_bdf_lookup()
will come soon that fixes this limitation)
- Make PCIE DTS file macros available for a proper ivshmem device
properties parsing.
Sample for dts file:
pcie0 {
label = "PCIE_0";
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,pcie";
ranges;
ivshmem0: ivshmem@800 {
compatible = "qemu,ivshmem";
reg = <PCIE_BDF_NONE PCIE_ID(0x1af4,0x1110)>;
label = "IVSHMEM";
status = "okay";
};
};
Signed-off-by: Michael Schmidt <michael1.schmidt@intel.com>
Modifying configuration to enable with gd32vf103
- Add usart definition to devicetree.
- Define USART_STAT as alias of USART_STAT0 if not defined it.
- Enable USART if SOC_SERIES_RISCV_GIGADEVICE_GD32VF103.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Change the settings to support pinctrl on the GD32VF103.
- Split soc/arm/gigadevice/common/pinctrl_soc.h
and put it into include/dt-bindings.
- Leave some definitions that can't handle with device tree compiler
in pinctrl_soc.h.
- Remove dependency to SOC_FAMILY_GD32 because always enabled it
if GD32_HAS_AF(IO)_PINMAX was selected.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
GD32V SoC uses divided clock from core-clock for machine timer clock.
Add config of clock divide factor to support GD32V.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
As Nordic SPI, I2C and UART buses can act as both slave and master,
these nodes can have different compatible properties, and are annotated
with a comment, instead of a compatible property. This forces boards to
put compatible properties in their definitions, which is unnecessary
boilerplate for most boards, as most boards acts as masters on these
buses.
Set master mode by default for these buses, to reduce boilerplate and
potential errors in board definitions. Boards that need to act as slave
nodes will just continue to override the compatible properties.
Likewise, existing boards that override this compatible property with a
master binding will not be affected by this change.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
The stm32u5 device has a single iwdg node entry and label
without any need for interrupt. Even if it exists the irq entry
is not required.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Implemented driver for the simcom sim7080 modem.
This driver features Socket offloading, TCP, UDP, DNS,
SMS, GPS and FTP.
Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
Remove the requirement for specifying #address-cells and #size-cells
properties for CAN controller devicetree nodes.
CAN controllers do not have a common concept of devicetree child nodes
and thus have no need for these properties. This is in line with
upstream Linux kernel devicetree bindings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
NPCX series used npcx-lvol-ctrl-map to record the GPIO & low voltage
control register map. However, GPIOE3 was configured as GPIOE6, which
is a non-existed pin. This commit fixes the GPIOE3 low voltage control
map.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Move odr and range properties for both accelerometer and gyro
from Kconfigs to Device Tree.
Fixes#41117
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Fix the yaml dts multi-line property description in the following
(expected) way:
description: |
PUT_TEXT_HERE
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Adding support for the TI TMP108 temperature sensor. This includes
over/under temp interrupt support as well as one shot, continuous
conversion and power down modes.
Signed-off-by: Jimmy Johnson <catch22@fastmail.net>
By enabling SMP option plus the APPCPU, also
completes the SMP port by adding the esp32
specific arch_sched_ipi() function
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
RT11xx can peripheral had incorrect clocking configuration in SOC clock
init code and DTS. Fix peripheral configuration.
Fixes#41251
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add a display driver and the corresponding devicetree binding for a LED
matrix with rows and columns driven by nRF SoCs GPIOs. Such matrix can
be found, for example, in the BBC micro:bit boards.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add board support for NXP i.MX8M Plus EVK. This board has the following
features:
Processor : i.MX8M Plus Quad applications processor
Memory : 32-bit LPDDR4 w/6 GB
eMMC 5.0/5.1 w/32 GB
SD/MMC connector
QSPI w/32 MB
Connectivity : MIMO 2x2 Wi-Fi 802.11b/g/n/ac and BT 4.2
2x Ethernet (1x w/ TSN)
PCIe M.2
2x CAN FD DB9 Female connectors
USB : USB 3.0 Type C for Power
USB 3.0 Type A
USB 3.0 Type C
Debug : JTAG connector
MicroUSB for debug console
More information about this board can be found in NXP website: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
When building for an STM32K010xB MCU, there is a deprecated properties
warning, which should be fixed by this PR.
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
Everything I can find as a reference says that the LP-SRAM block on
these devices is 64kb, and direct experimentation with cAVS 1.5 and
2.5 agrees. Access to areas beyond 64k hangs the DSP (it should cause
a PIF fault I guess, but the exception never gets trapped, that's
probably a different problem).
Fix this in devicetree to reflect what actually works. It's not clear
where the 128k values came from; if they're not typos we can correct
that when we find better docs.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Create an explicit ina230 driver which is supposed to
work with 230 and 231 variants. While at it switch
to i2c_dt_spec helpers and change device-tree node
names to use - instead of _ in order to follow
convention.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Create a common properties file that will be included by all bindings
(as i2c and spi) handled by lps22hh driver.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
PSL_IN pin select register is Vsby power-up reset. When the other
core-domain-reset reset the chip, PSL_IN3/4 don't set to GPIO. This
commit adds PSL_IN3/4 to the pin select list in NPCX devicetree. So
these pins can be set to GPIO when the other core-domain-reset.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
GPT base address in the devicetree for the RT11xx SOC series was
incorrect, this commit fixes it
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added a driver to enable the GPT timer on RT1xxx parts to be used
instead of systick as a clock source. The timer is set to run in reset
mode, and uses the low frequency 32kHz oscillator for power savings
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for the 8 channels TCA9548A I2C mux.
Added a new binding ti,tca9548a binding inheriting
properties from ti,tca954x-base and defining its own compatibles fields.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Add an optional "reset-gpios" phandle-array
field to the driver common yaml.
The reset GPIO channel and pin can be defined
in device tree as a node property.
The driver then deassert the reset signal at mux
initialization if a "reset-gpios" has been specified.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Prepare the driver to upcoming support of more mux references.
Rename all TCA9546A related files to TCA954x.
Keep ti,tca9546a and ti,tca9546a-channel compatible
for backward compatibility reasons.
New tca954x-base binding embedding common properties,
tca9546a binding inherits from it and define its own compatibles fields.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Include the mem-region bindings for the stm32 ccm nodes and set the name
in the current dtsi files.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Add the compatible property to the board level sdram nodes in few stm32
dts files so that the zephyr,memory-region name is used correctly in the
linker script.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Add bindings for SDL based display controller.
Rework SDL based display controller driver to obtain
configuration from devicetree. Remove unnecessary casts,
add multi-instance support.
Add display controller node and chosen property
to native_posix devicetree.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Include common display controller bindings.
Add required height and width properties to "ilitek,ili9340"
and "ilitek,ili9488" users.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Not all boards use the same UART's defaults properties.
This commit updates device tree declarations by deferring
specific definitions to the board's DTS.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Not all boards use the same UART's defaults properties.
This commit updates device tree declarations by deferring
specific definitions to the board's DTS.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Enable flexspi for RT11xx SOCs. This requires selecting the correct
KConfig symbol for the cortex m4 and m7 SOCs, as well as correcting an
error in the flexspi DTS node and updating the clock init for RT11xx
SOCs.
Note that in addition, the NXP hal must be updated to properly support
including the cache management driver for the Cortex M4.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce optional `zephyr,linker-region` property which signifies that
the node should result in a linker memory region and what the name of
that region should be. Property added to compatibles likely to result
in a linker memory region; 'mmio-sram', 'arm,itcm`, `arm,dtcm`,
`nxp,imx-itcm`, `nxp,imx-dtcm` and `fixed-partitions`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Refactor the mcp230xx driver to generically also support
SPI IO expanders, renaming it to mcp23xxx in the process.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
DMA controller is enabled and tested for cortex M7 core. The M7 core was
tested on the loop and channel link transfer tests.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
DMA controller is enabled and tested for cortex M7 core. The M7 core was
tested on the loop and channel link transfer tests.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds a generic i2c regulator driver, and enables the NXP
PCA9420 PMIC IC using this driver. The regulator driver also exposes an
additional API in include/drivers/regulator/consumer.h, which allows
drivers to implement support for adjusting voltage levels and current
limits, if their device supports it.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
the RT685 contains an additional flexcomm peripheral, that supports
only I2C. This commit adds this peripheral to the device tree,
and enables pins and clocks for flexcomm15.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
There is currently no information available about the XIP
addresses for the nRF52840 and nRF5340.
Add this via a new 'reg' block in the relevant QSPI nodes, along with
names for the register blocks so they are easier to retrieve.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This board, whose hardware is just a cAVS 1.8 device without an x86
host CPU, started life (as all the cAVS devices did) as a
cut-and-pasted copy of the same basic code.
Because of hardware and schedule limitations, it didn't get the same
unification treatment that all the other platforms did. But it turns
out that in SMP configurations (which... it's not clear if we actually
test on hardware?) it wants to use the cavs_timer driver, which now
uses the new SOC API and not the old one. Which s1000 doesn't expose.
So... I guess we have to continue to cut and paste until we can find
time to unify this. Add a copy of the new shim/IDC headers to this
SOC and expose them via devivcetree.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Adds a driver using the SNVS high power and optionally low power
RTC instances. A device specific function `mcux_snvs_rtc_set` is
provided to update the current counter value.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
GPIO10 was missing from RT11xx DTS, and is required to manage SD card
power. Enable this GPIO.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The commit adds "disk-access" property to fstab bindings to allow
selecting FS_MOUNT_FLAG_USE_DISK_ACCESS while defining file
systems in DTS.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
This adds an spi master mode driver via bitbanged gpio. Only syncronous
transfers are implemented. Clock signal timing is accomplished via busy
waits, the gpios are manipulated via the standard gpio interface; these
two factors limit the frequency at which it can operate - but here
a simple and generic implementation was chosen over performance.
The driver supports the various clock polarity and phase
configurations, and can also work with word sizes which are non
multiples of 8bits, currently up to 16 bits.
A sample program is also added demonstrating basic use of the driver
with 9bit data words.
Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
MCUX PWM driver used hardcoded clock source. update driver to use clock
bindings to determine PWM peripheral clock frequency.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds optional device tree properties to insert delays between spi chip
select assert/deassert and the clock edges, and also between spi
frames and transfers to the mcux flexcomm spi driver. If the properties
are not set, no additional delay is inserted.
Verified expected behavior on mimxrt685_evk and check with a scope
that the pre- and post-delay could be changed from the device tree
properties.
Signed-off-by: Bryce Wilkins <bryce.wilkins@gmail.com>
This commit adds support for IMX6SX PWM.
The PWM module is the same module present on the IMX7D and so dts
bindings has been renamed following the one present on linux.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Most of the time SPI devices use TI's frame format. But some may use
Motorola's. This is already taken care of in the SPI API and now it will
be possible to select the right format from DTS. Like:
...
frame-format = <SPI_FRAME_FORMAT_MOTOROLA>;
...
This is only meant to be used for devices supporting both formats (so
the format is not hard-coded in the driver) and selected by hardware
configuration or else. Which, in such case, it will need to use
DT_INST_PROP(<instance number>, frame-format) macro call to retrieve
the property value. Others can fully ignore it.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Software reset is already implemented in the driver when the
`reset_gpio` is not defined. However it could not be activated
because the `reset_gpio` is a required field in the DTS
binding.
Signed-off-by: Casper Meijn <casper@meijn.net>
This patch adds support for the new pinctrl API to the UARTE driver. The
old pin property based solution is still kept so that users have time to
transition to the new model.
Notes:
- Some build assertions cannot be performed since the driver does not
have direct access to pin settings anymore. As a result user will not
be notified if HWFC is enabled but RTS/CTS pins are not configured.
- Hardware flow control can be enabled regardless of pin configuration,
it is now up to the user to configure RTS/CTS pins in DT.
- Some RX enable checks that were performed using pin information has
been replaced with a DT property that informs if RX is enabled or not.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.
Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.
Thanks to Marti Bolivar for bindings documentation.
Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Now that STM32 drivers are using pinctrl API, set pintrl-0 and
pintrl-names properties as required in order to report malformed
nodes description soon at build stage and avoid cryptic
DT api build error messages.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use the new pinctrl API to configure pins.
Since STM32F1 series require pinctrl option and required register
address is parent timer address in place of own node register address,
use PINCTRL_DT_INST_CUSTOM_REG_DEFINE in place of usual
PINCTRL_DT_INST_DEFINE for this specific series.
Additionally, remove the automatic selection of PINMUX API.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use the new pinctrl API to configure pins.
Additionally, rename usb_pinctrl to usb_pcfg to better fit
new pinctrl API.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the I2C peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use nrfx_gpiote and nrfx_ppi allocators to allocate channels
at runtime instead of fixed, device-tree based allocation which
is harder to maintain.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add bindings for a generic PCIe Controller in ECAM mode.
ECAM stands for PCI Express Enhanced Configuration Access Mechanism
where the PCIe config space is flat memory-mapped.
An optional msi-parent phandle is added to link to an optional
MSI/MSI-X Interrupt Message Translation HW component.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The qemu arm64 virt machine PCIe controller config space needs a
64bit adressing, so switch the entire qemu-virt-a53 and
qemu_cortex_a53 board dts to address-cells & size-cells to 2
to accommodate for 64bit addresses.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
These registers were hardwired in the platform layer. Move to
devicetree, via a struct interface that looks like the pre-existing
shim layer.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These registers are identical on all platforms, the only difference
being that cAVS 1.5 places them at a different address.
Create a devicetree node to track the register block, and replace the
platform header code with a global API defined once (it works like the
pre-existing shim struct).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Each platform was defining its own shim.h header, with slightly
variant field definitions, for a register block that is almost
completely compatible between versions. This is made worse by the
fact that these represent an API imported fairly early from SOF, the
upstream version of which has since diverged.
Move the existing shim struct into a header ("cavs-shim.h") of its
own, remove a bunch of unused symbols, fill in definitions for some
registers that were left out, correct naming to match the hardware
docs in a few places, make sure all hardware dependencies are source
from devicetree only, and modify existing usage to use the new API
exclusively.
Interestingly this leaves the older shim.h header in place, as it
turns out to contain definitions for a bunch of things that were never
part of the shim register block. Those will be unified in separate
patches.
Finally: note that the existing IPM_CAVS_IDC driver (soon to be
removed from all the intel_adsp soc's) is still using the old API, so
redeclare the minimal subset that it needs for the benefit of the
platforms in transition.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is dead code. It's based on the cAVS "IPC" mechanism to allow
communication to and from the host CPU. But there is no test rig in
the Zephyr tree for the protocol defined. And in fact the only
Zephyr-based user of the IPC mechanism (Sound Open Firmware) has its
own IPC driver and speaks its own protocol with the host kernel. That
driver needs to migrate into Zephyr soon and this legacy bit is just
confusing.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Introduce a new RPMsg with static VRINGs backend. This new backend makes
easy to generate and use IPC instances backed by OpenAMP using the DT.
Each instance is defined in the DT as (for example):
ipc: ipc {
compatible = "zephyr,ipc-openamp-static-vrings";
shm = <&sram_ipc0>;
mboxes = <&mbox 0>, <&mbox 1>;
mbox-names = "tx", "rx";
role = "primary";
status = "okay";
};
It is then possible to register an send data through endpoints using the
IPC service APIs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
* With existence of Adafruit Qt Py boards, and upcoming wireless
Xiao from Seeeduino, define nexus node and peripheral node
labels for use with shields that accept any Xiao format board.
* Adds `&xiao_d`, `&xiao_spi`, `&xiao_i2c` and `&xiao_serial` generic
node labels.
* Add new 'seeed-xioa-header.yaml` to document new nexus node.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Add a pin control driver for GD32 SoCs using the AFIO model.
Thanks to Gerson Fernando Budke for testing and implementation
suggestions.
Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
1.Putting the PWM_CHANNEL_X, PWM_PRESCALER_CX information
in the description.
2.Use the common definition EC_FREQ.
3.Use the common macro IT8XXX2_DT_ALT_ITEMS_LIST.
4.Stop using DRV_CONFIG, DRV_REG macro.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Users will have to include dt-bindings/spi/spi.h in order to use the
relevant flags fol this property. For instance:
...
duplex = <SPI_HALF_DUPLEX>;
....
By default all SPI device are configured to be full duplex so the
property is optional. This property makes sense only for devices that
can be configured on either modes. Which, in such case, it will need to
use DT_INST_PROP(<instance number>, duplex) macro call to retrieve the
property value. Others can fully ignore it.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add tests for the instance based enum macros DT_INST_ENUM_IDX and
DT_INST_ENUM_IDX_OR.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.
Changes include:
- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
IT8XXX2 uses shared ns16550.c driver which does not provide a power
management callback(pm_action_cb), so create driver to handle
IT8XXX2 specific UART features.
note: pm_action_cb(old name: pm_control_fn)
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
Also prescaler is common to all PWM channels of the same timer.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
For compatibility reason temporarily keep pwm binding to avoid
breaking boards out of tree.
Block st,prescaler property in lptim binding
as lptim doesn't use this property for now.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This will be used to take a phandle to a FEM device, either a generic
two pin device or an nRF21540. Keep the nRF21540 binding example up to
date.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The way the nRF21540 device is configured makes sense once you
understand it, but it's quite unusual: a single peripheral is
configured with two separate devicetree nodes linked by a phandle.
Since this risks entering "exploding head" territory for beginners, it
deserves a thorough example. Add one to the binding's description.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This is a helper binding for radio front-end modules that have a
two-pin control interface, where one pin is used to turn on an power
amplifier (PA) for TX, and another is used to turn on a low-noise
amplifier (LNA) for RX.
Such hardware is already supported by the Bluetooth subsystem, but via
PA/LNA Kconfig settings. Since this is hardware configuration, it is
better to move this to devicetree instead.
Add a binding that makes it possible to define nodes which contain the
same information, along with a bit of extra information related to the
gain in dB of each amplifier not currently available from Kconfig.
This is similar to the existing binding for the nordic,nrf21540-fem
compatible.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Andrzej Kuros <andrzej.kuros@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This is to support upcoming external radio coexistence implementations,
see binding documentation for more info.
Signed-off-by: Jonathan Rico <jonathan.rico@nordicsemi.no>
add ledc to board dtsi file,
change compatible and device define in pwm driver,
add yaml for board ledc support,
fix missing include for board in gpio include
Signed-off-by: Andrei-Edward Popa <andrei_edward.popa@upb.ro>
Use i2c_hal functions to enable support for
multiple SoCs.
Use DT compat to enable I2C from device
tree configuration
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the USB On-The-Go Supplement, Revision 2.0 in the DTS
of the stm32u575 and stm32u585 devices
(not for the stm32U5 serie).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In order to have Espressif SoCs working with
the same uart drivers, all low level functions
are now replaced to hal_espressif HAL calls.
This also changes pinmux, gpio and uart
init order to meet its dependencies.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
STM32WL could be either single core (stm32wlex) or
dual core (stm32wl5/4x).
Make CPU2 prescaler an optional property (while it will
be required if inherited from st,stm32wb-rcc.yaml.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that Kconfig option for STM32 clocks configuration has been
removed, set rcc properties as required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fix register addresses in rt11xx SOC dts. Flexcan1 was defined with an
incorrect register address, and watchdog 3 was incorrectly labelled as
watchdog 1. Watchdog 2 should not be enabled, as it is only accessible
from code running in the trustzone context.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add baseline support for mimxrt1160_evk Cortex M4 and M7 cores
UART shell, synchronization, and hello world have all been verified to
build and run correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Convert all in-tree NXP FlexCAN instances from hardcoding the CAN bus
timing in time quanta to specifying a desired sample point of 87.5% as
recommended by CAN in Automation (CiA).
This allows for the CAN driver to calculate the optimal time quanta
based on the CAN clock and the requested CAN bitrate.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added watchdog implementation which is using counter device
to implement watchdog driver API. Watchdog timeout is called from
counter interrupt context. Some counter implementations support
using ZLI interrupt level which can be use here as well. Watchdog
like this can be used along hardware watchdog to cover for its
limitations, i.e. Nordic watchdog resets unconditionally after
62uS after triggering watchdog interrupt. It is not enough time
to dump logging data.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The FIU/UMA module in the NPCX chip provides an dedicated SPI interface
to access the SPI flash. This commit adds the driver support for it.
With this commit, the application can call the flash APIs
(via spi_nor.c) to access the internal flash of NPCX EC chips.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I32bbf09f6e014b728ff8e4692e48151ae759e188
Add the power state of deep doze. When system enters deep doze, the
clock of CPU and EC can be stopped to reduce power consumption. And
enable the UART Rx WUI before entering deep doze to wake up EC and
CPU.
Tested on it8xxx2_evb board. It will reduce 5.25mA when system enters
deep doze mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add SoC-specific code, the basic device tree and Kconfig data as well
as the corresponding linker command file for the Xilinx Zynq-7000
family of SoCs. This SoC - either as a QEMU simulation or on actual
hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini-
tial target for the ARMv7 Cortex-A support.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Rewrite the NRFX IPC driver to properly support multi-channel addressing
leveraging the newly introduced MBOX APIs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
One limitation of the current IPM API is that it is assuming that the
hardware is only exporting one single channel through which the data can
be sent or signalling can happen.
If the hardware supports multiple channels, the IPM device must be
instantiated (possibly in the DT) several times, one for each channel to
be able to send data through multiple channels using the same hw
peripheral. Also in the current IPM API only one callback can be
registered, that means that only one driver is controlling all the
signalling happening on all the channels.
This patch is introducing a new MBOX API that is supporting
multi-channel signalling and data exachange leveraging and extending the
previous (and outdated) IPM API.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This is a driver for the Synopsys DesignWare MAC. It should work
with the "DesignWare Cores Ethernet Quality-of-Service" versions 4.x
and 5.x.
This driver uses a zero-copy strategy, meaning that the hardware
reads and writes data directly from/to packet fragment buffers
provided by the network subsystem without first copying the data into
a dedicated DMA bounce buffer.
Platform specific setup is necessary for the hardware to work.
Currently, only the STM32H7X series is implemented and tested.
While this part needs refinement, this driver performs better and uses
far less code space than the HAL-based alternative.
Not yet implemented:
- MDIO (it is WIP, currently relying on default PHY config)
- PTP support
- VLAN support
- various hardware offloads (when available)
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
MEC172x eSPI driver, eSPI pin programming, interrupt updates related
to eSPI and other updates for MEC172x eSPI driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Pick those common node in 'fvp-baser-aemv8r.dts' to 'fvp-aemv8r.dtsi'
which reside in 'dts/arm64/fvp-aemv8r' directory.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Add a set of tests to check the API behavior. The API tests can only run
on a platform that does not have an actual pinctrl driver, e.g.
native_posix. The test itself implements a pinctrl mock driver and
provides the required "pinctrl_soc.h" header with required types/macros.
The implementation is used in the tests to verify the behavior of the
API or Devicetree macros.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
When using group based representation on pinctrl nodes, the pin
configuration properties end up being at the grand-children level, so
the `pincfg-node.yaml` file can't be used.
Having a common file that can be used for both cases would require
tooling changes, so for now a copy that operated at the grand-children
level has been created.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Initial skeleton for pinctrl drivers. This patch includes common
infrastructure and API definitions for pinctrl drivers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Move odr options from Kconfigs to Device Tree. Moreover add
in DT a power-mode option to select among 4 possible values
(PD, LP, HR, HF). The power mode cannot be currently set from
sensor APIs.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Create a common properties file that will be included by all DT
bindings (as i2c and spi) handled by lis2ds12 driver.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add a dedicated compatible for STM32MP1 clock control node.
Since, on such platform, clock configuration is done on A9
side, only the clock-frequency property is available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add dtsi file for i.MX8MP board.
This has one HiFi4 core, from Cadence, lx6 compatible
and 2 System RAM.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Add a DTS description of timer5 to: STM32G474, STM32G484, STM32G473,
STM32G483, and STM32G471
Add a DTS description of timer5 to: STM32G474, STM32G484, STM32G473,
STM32G483, STM32G491, and STM32G4A1
Signed-off-by: Pete Dietl <petedietl@gmail.com>
Add general mboxes, mbox-names to base.yaml to be utilized by any
clients that use mailboxes.
Additionally add mailbox-controller.yaml for common properties shared
by all mailbox controller devices.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add devicetree nodes for the NEORV32 GPIO device.
The GPIO port is 64 bits wide, but Zephyr only supports up to 32 bit
wide GPIO ports. The GPIO device is therefore handled as two Zephyr GPIO
devices with a nexus devicetree node mapping pins 0 to 31 to the device
handling the lower half, and pins 32 to 63 to the device handling the
upper half.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Currently all the *-names and *-cells properties are derived from the
name of the base <name>s property. This is a limitation because:
- It forces the base property name to be plural ending in -s
- It doesn't allow the english exception of plural words ending in -es
With this patch we add one additional property 'specifier-space' that
can be used to explicitly specify the base property name.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Suggested-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
1) Allow use of interrup driven instance.
ROM implementation could be selected via dts compatiable.
2) Use UART rx fifo and timeout interrupt for end of message detection.
Added to decrease interrupts count on data reception
3) Use ESP_LL api.
Signed-off-by: Pavlo Hamov <p.hamov@venstar.com>
Adds SPI support on LPSPI1 to the RT1010. LPSPI1 is available on pins
6, 8, 10, and 12 of J57 on the evaluation board
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit enables the LPSPI1 peripheral on the RT1015 EVK. LPSPI pins
are not populated by default, but headers can be added to J19 on the EVK
to access these signals
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add device tree for Intel SoC FPGA Agilex initial bring up. This is the
first version of device tree which enable single CPU core and basic
drivers that needed by hello_world example.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
The shared multi-heap memory pool manager uses the multi-heap allocator
to manage a set of reserved memory regions with different capabilities /
attributes (cacheable, non-cacheable, etc...) defined in the DT.
The user can request allocation from the shared pool specifying the
capability / attribute of interest for the memory (cacheable /
non-cacheable memory, etc...)
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add specific properties to enable remap for PA11/PA12, which is a
possibility on STM32G0/F0 SoCs.
These properties only have effect when defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This name should be the same as cpus node in dtsi. After the power
policy is added, the cpu-power-states in the CPU properties can
be used.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
AHB prescaler is a value which divides the SYSCLOCK
to provide the HCLK. The HCLK supplies the core, AHB bus, memory.
On the stm32wb and stm32wl, the HCLK for CPU1 is HCLK1
with cpu1-prescaler.
By default the value is 1, else the HCLK must be correctly set.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
interrupt controller, also places its relevant
peripheral sources allowing drivers to use the
DT macros instead of espressif headers.
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
This reverts commit d3a558591f.
We shouldn't be adding vendor prefixes for things we don't have
upstream bindings for unless we've inherited them from Linux.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
If supported by the SPI instance and soc, this property will
configure the frame-format to be compliant with the TI mode.
By default, if supported, the frame-format is Motorola mode.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The maximum supported speed according to the SX126x datasheet (I have
not found that information in the STM32WL datasheet or reference
manual). Increase the Sub-GHz SPI frequency from 1 Mhz to to 12 MHz,
which corresponds to a baud rate prescaler of 4 with a 48 MHz clock. It
also matches what is done the the STM32CubeWL package.
This reduces the time the MCU is kept running, thus reducing the global
power consumption.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This adds the uart4 device to the stm32f3_disco board
based on the stm32f303 device from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds stm32f103xd series dts file that was missing.
Also, changed stm32f103xe.dts for highlighting the differences between
f103xd and f103xe series.
Signed-off-by: Deimantas Aukštkalnis <deimantas.aukstkalnis@teltonika.lt>
Add DT bindings for the optional Interrupt Translation Service module
of the ARM GICv3 Interrupt Controller.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Implements a shim layer driver using st hal for
I3G4250D gyro, mounted for example on stm32f3_disco_E.
No support for triggers included yet.
Signed-off-by: Jonathan Hahn <Jonathan.Hahn@t-online.de>
1. Add support for multiple syscon entries (as a side effect, this also
fixed syscon.c implementations which weren't being linked to their
syscon.h counterparts).
2. Add support for different width registers in syscon.
3. Add tests for syscon
Signed-off-by: Yuval Peress <peress@chromium.org>
Since version 1.11.0, Full stack M0 binary requires 216K of flash
being available, while previously 212K were required.
Review flash partitioning to take it into account.
Additionally:
- update value in board yaml file.
- align value in package .dtsi file
Fixes#38735
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The NPCX I2C implementation contains two modules, an I2C port and an
I2C controller. Disable the I2C controller nodes by default and require
the user to enable both the I2C port and controller in the devicetree.
Signed-off-by: Keith Short <keithshort@google.com>
Fix a typo bug where sercom5 pinctrl has pad2 and pad3
has duplicated pads for pb0/pb2 and pb1/pb3.
Per the datasheet, pb2 and pb3 should be pad0 and pad1 respectively.
Signed-off-by: Ron Smith <rockyowl171@gmail.com>
TWIM peripherals cannot perform write transactions from buffers
located in flash. The content of such buffers needs to be copied
to RAM before the actual transfer can be requested.
This commits adds a new property (zephyr,flash-buf-max-size) that
informs the driver how much space in RAM needs to be reserved for
such copying and adds proper handling of buffers located in flash.
This fixes an issue that caused that e.g. the DPS310 sensor driver
did not work on nRF SoCs that only have TWIM, not TWI peripherals.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Issue an error logging message when the i2c_nrfx_twim driver lacks
a concatenation buffer big enough to properly handle a call to
i2c_burst_write() function, to give the user a hint what is wrong.
Also use by default a 16-bytes long concatenation buffer for every
instance of the i2c_nrfx_twim driver. Such value should cover most
of the simple uses of the i2c_burst_write() function, like those
in the stmemsc sensor drivers, and when a longer buffer is needed,
the user will be provided with the above message pointing to the
property that should be adjusted.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Remove the HL7800 DTR device tree binding because the
DTR IO is not needed for operation of the HL7800
modem.
Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
This patch fixes wrong PLIC irq number of UART and SPI for SiFive
FU740 on HiFive Unmatched. Use samples/subsys/console/echo for
testing.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
The priority of the LPTim interrupt on each stm32 soc
is put at the same level as the SysTick. This priority
level is given by the system Handler priority reg
(SHPR3) when the PM is not configured.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
stm32f411 includes stm32f401 which do already correctly define spi4
The definition in stm32f411 was missing a clock attribute
Signed-off-by: Kim Bøndergaard <kim.boendergaard@escoglobal.com>
stm32f410, stm32f411 and stm32f412 enable the SPI5 device with
bit 20 on the APB2 clock
Signed-off-by: Kim Bøndergaard <kim.boendergaard@escoglobal.com>
This patch adds support for SiFive Freedom U740 SoC.
First version is minimum only using UART, SPI and L2-LIM area.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch adds support for SiFive Freedom U540 SoC.
First version is minimum only using UART, SPI and DDR memory area.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Add a shim that allows using the nrfx PDM driver via the Zephyr API.
Add also missing devicetree nodes representing the PDM peripherals
in the nRF52 Series SoCs.
Extend the "nordic,nrf-pdm" binding with a new property that allows
specifying the clock source to be used by the PDM peripheral (so that
it is possible to use HFXO for better accuracy of the peripheral clock
or, in the nRF53 Series SoCs, to use the dedicated audio oscillator).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
add correct binding, fix size to 32MBit, add erase and write
block size to support mcuboot and rename to reflect the actual
flash model.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Atmel sam0 adc peripheral have multiple interrupt vectors for same5x
devices. This configure interrupt vector by name to ensure that proper
interrupt handle will be executed.
Fixes#37779
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Compatible "soc-nv-flash" was removed as part as #38077,
while it should have been kept, similarly to what was done
on other SoCs.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The max-erase-time property was introduced for the STM32 flash driver,
but it was inserted as an optional property in the generic
soc-nv-flash binding which is used by other SoCs.
Make it a required property in a new st,stm32-nv-flash binding
instead, since it is at present a vendor specific property.
Update the DTS files accordingly. Keep the existing "soc-nv-flash"
value in the compatible list in each case, so that DT_HAS_COMPAT(...
soc_nv_flash) tests on these nodes will still succeed, but put it
after a newly added "st,stm32-nv-flash" compatible, so that the
SoC-specific binding will be used as it is discovered first by the DT
tooling.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Note that the it8xxx2 does not support a status register so that
functionality is omitted.
This change also adds driver tests that build both the npcx and it8xxx2
drivers.
Signed-off-by: Yuval Peress <peress@chromium.org>
Change IPM_STM32_HSEM Kconfig definition so that it picks the correct
default automatically depending on which cpu node is enabled in the
device tree, rather than relying on board specific Kconfig overrides.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Add dtsi file for i.MX8QM and i.MX8QXP boards.
These two have the same board-level definitions,
so we call it, generically, imx8.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
This commit adds support for Ethernet PHY drivers via a PHY API.
It also includes a driver for a generic MII compliant PHY
which supports most PHYs on the market.
Separating PHY driver from the SoC specific Ethernet driver
simplifies the Ethernet driver code and enables code re-use.
Drivers for specific PHYs with more advanced features, such as
RGMII delay in PHY can be developed independent of the Ethernet
MAC driver.
Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
Add Digital-to-Analog Converter driver (based on DACC module) for Atmel
SAM MCU family. Only SAME70, SAMV71 series devices are supported in
this version.
Tested on Atmel SMART SAM E70 Xplained board.
Origin: Original
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Microchip MEC172x series I2C driver implementing controller
and target modes. The driver implemenents its own I2C port
pin control functions and does not depended upon pinmux. Future
updates will make use of PINCTRL when that subystem is finalized.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This adds basic support for the Silabs Si7210 hall effect magnetic
position and temperature sensor. It is able to get magnetic field and
temperature in the default scale of the sensor (depending on the
variant). It also supports going into sleep mode without measurements
through the device power management infrastructure.
It is most notably missing support for scale change, measurement
averaging and filtering, and alert pin configuration (threshold,
hysteris, tamper).
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Following change of HSE clock binding, remove hse-bypass
which is no longer an option and replace it with hse-tcxo
which is the configuration closest to previous status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32WL features a specific HSE clock with dedicated properties.
Add a dedicated binding and update STM32 clock control driver
header to take it into account.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add hidden Kconfig option to Kconfig.cdc and allow
to configure CDC ACM UART device from devicetree.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Current USB device controller drivers (drivers/usb/device)
do not use DEVICE_DT_GET but the properties from devicetree,
and USB device controller node is parent for CDC ACM UART and
AUDIO children nodes.
Add USB device controller binding and node to keep the samples
building for native_posix driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This adds support for the TI INA219 Zero-Drift, Bidirectional
Current/Power Monitor with I2C Interface
Signed-off-by: Leonard Pollak <leonardp@tr-host.de>
Like the first instance of the dma in the stm32l3xx soc,
the second DMA instance of the stm32f373 is of the same type
V2bis (dma request is fixed (no dma-slot).
The dma-cell has channel and config.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add missing RADIO and EGU nodes. We already have compatibles for
these defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing EGU nodes. We already have a compatible for
these defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing RADIO and EGU nodes. We already have compatibles for
these defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing EGU and TIMER nodes. We already have compatibles for these
defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing RADIO and EGU nodes. We already have compatibles for these
defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing RADIO and EGU nodes. We already have compatibles for these
defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing FICR, UICR, RADIO, and EGU nodes. We already have
compatibles for these defined, and the peripherals are present, so
define them for consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add missing FICR, UICR, RADIO nodes. We already have compatibles for
these defined, and the peripherals are present, so define them for
consistency across SoCs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The way we currently handle direction finding extension (DFE) support
on Nordic nRF5 controllers relies on required devicetree properties
related to DFE in the "nordic,nrf-radio" node.
That doesn't make sense on radios without DFE support, though.
Any .dtsi for an SoC without DFE support which has such a node would
require extraneous DFE related properties like dfe-antenna-num.
Instead of making the properties required, mark them optional. We
indicate the presence of DFE support via a new 'dfe-supported' boolean
property which the SoC .dtsi files can set (or not) depending on
support.
This gives us the opportunity to do some cleanup in the Kconfig,
removing CONFIG_HAS_HW_NRF_RADIO_BLE_DF since we know from the
devicetree whether DFE support is available.
Handle that change appropriately in radio_df.c. This gives us an
opportunity to improve readability in the devicetree-related macro
magic in that file.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The documentation for Bluetooth Direction Finding Extension (DFE)
samples has various issues:
- references to 'child' images, which do not exist in mainline zephyr
- invalid RST syntax: there are missing ` characters to end arguments
to :zephyr_file: roles, creating unintelligible output
- incorrect RST usage:
- using :zephyr_file: instead of :file: when referring to a file
that the user must create, creating broken links to nonexistent
files in the zephyr tree
- using :code: instead of :kconfig: to refer to kconfig options,
creating output without links to the help for those options
- redundant or duplicated information
- grammar, typos, various bits and pieces
Clean this up. As part of that, move various common bits and pieces of
information to the devicetree bindings index so they can just be
linked to from the sample docs.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Sort by unit address. This involves multiple files since there are
includes and secure/non-secure files to deal with.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This has an unrecognized vendor prefix which does not seem to serve
any purpose. Removing it is a way forward to turning warnings into
errors on unrecognized vendor prefixes.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The Linux vendor prefixes list uses 'cdns'. Match it, especially since
we have that prefix in our own list as well.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
These IP blocks' vendor is Cadence, whose proper vendor prefix is
'cdns' if we are going to match the Linux vendor prefixes list.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
As far as I can tell, 'vexriscv' does not name a vendor:
https://github.com/SpinalHDL/VexRiscv
It also doesn't seem entrenched enough to merit a special case
exception to the de factor rule 'the "vnd,foo" namespace is for
vendors'. This is open to debate and we can revise as needed in the
future, but for now let's just rename the compatible to avoid
triggering warnings/errors about unknown vendors.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The original NIOS-II developer and former vendor is Altera, which is
now part of Intel. Let's not add a new vendor prefix for something
that already exists and has been acquired; move it to use the existing
'altr,' prefix instead.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Rename:
- grove,light to seeed,grove-light
- grove,temperature to seeed,grove-temperature
The "grove" brand applies to a family of products by Seeed (sic):
https://www.seeedstudio.com/category/Grove-c-1003.html
Therefore we should use the existing vendor seeed.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
I can't find any reference anywhere showing that the manufacturer of
the LPD8803 or LPD8806 LED scripts is a company called 'colorway'.
Use 'greeled' instead; these seem to actually be manufactured by
GreeLed corporation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
It should be "maxim,max30101", because the vendor prefix for this
company is "maxim", not "max".
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
It should be "u-blox,sara-r4", because the vendor prefix for this
company is "u-blox", not "ublox".
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
We have a ftdi,ft800 binding, and it's easy to imagine additional
bindings coming in the future since their USB/UART chips are very
commonly used.
I didn't find anything in Linux for this vendor.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This is used for microbit,edge-connector. I couldn't find anything in
Linux, which is not surprising given these boards have constrained
Cortex-M chips.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
We have various compatibles matching this in a DTSI file.
Linux tracks this vendor too:
4071883fd8
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
We have a binding for apa,apa102 in zephyr.
I can't find any bindings for this vendor in Linux.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
We have a binding for compatible "quectel,bg9x".
I can't find any bindings for this vendor in Linux.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
We have a binding for wiznet,w5500 in zephyr.
Linux has a binding for this device, too:
d5ad8ec3cf/Documentation/devicetree/bindings/net/wiznet,w5x00.txt
But 'wiznet' is not present in the Linux vendor prefixes file for some
reason.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This PR will change accessing the related pinctrl macro from soc_dt.h
And the pinctrl of SCL and SDA were got from pinctrl-0 and pinctrl-1,
respectively. Change it to get from pinctrl-0 only.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This adds the driver for Omnivision OV2640 image sensor.
The driver provides support for 10 different resolutions in range from
160x120 to 1600x1200 in both JPEG and RGB565 pixel formats. There are
also mutliple configuration options, e.g. hflip, vflip, saturation and
brightness control.
Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>
Add sifive-e24 cpu binding. This introduce riscv,cpu binding to
be used as riscv cpu base and riscv,sifive, which define specific
properties for this vendor. Both are necessary to create the e24
core.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add missing dts binding for sensor, this was causing build errors with
CONFIG_PM set on bt510/bt6x0 boards.
Fixes#37675
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Renames stm32g0 tim1 brk interrupt to brk_up_trg_com, such that the
naming aligns with stm32f0 series and drivers can find the interrupt
with a common name.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add ADC driver version 2 for MEC172x using new in-tree headers
and device tree properties. Update the ADC shell for the new driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Introduce a new API to allow devices capable of wake up the system
register themselves was wake up sources. This permits applications to
select the most appropriate way to wake up the system when it is
suspended.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The psoc6 SoC has 2 cores, each with different allowed priority ranges:
CM0: 0-3 (2 bits of NVIC prio, no prio reserved by the kernel)
CM4: 0-6 (3 bits of NVIC prio, one level reserved by the kernel)
Since some of the peripherals are only available to the CM4, those
should be set to a priority that is actually valid for it. In this case
the lowest possible one is 6, so transition from 7 to 6.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Microchip XEC has been using the standard NS16550 driver.
Using the standard NS16550 driver requires extra HW programming
for XEC UART in board level and did not support XEC GIRQ interrupt
programming. We add an XEC specific driver and remove UART specific
register programming from the board level and implement interrupt
support. Also, by implementing a SoC specific driver we can add
driver PM in the future.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Microchip XEC two custom DT properies girqs and pcrs cell sizes
are defined as constants. There is no need to replicate these
is the chip DTSI since the value cannot be changes. Fix the syntax
of the cell size constant to match the naming convention used
thoughout DT.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
based on uart rom functions, also enable console driver
on top of this driver, which enables logging
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Add optional support for the DRDY/INT pin. This avoids waiting a fixed
time for the temperature and humidity conversion to finish.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The ipm_stm32_hsem driver is a virtual mailbox based on STM32 HSEM.
Since we already have LL_HSEM(low-level HSEM) API on the hal_stm32
module, looks there is no need to implement a new HSEM driver.
But there are still have some limitations, the HSEMx interrupt is
not shareable. If another HSEM user wants to use the HSEMx interrupt,
the ipm_stm32_hsem mailbox needs to be disabled.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
We try to reduce the ambiguity between 'soc/nuvoton/' and
'soc/nuvoton_npcx' folders. Most if soc vendors name their soc folder by
the company name with SOC_FAMILY suffix instead of the company name
directly. It is clearer if the soc company has different product lines
that aim to specific markets.
In this CL, the 'numicro' suffix is used for Nuvoton Microcontroller
production line. It distinguishes the 'npcx' suffix that used for
Nuvoton Embedded Controller (EC) of Notebook PC product line.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This is a follow-up to commit 3656ba5ae9.
Do not enforce pull-up resistors to be enabled on RXD and CTS pins
in nRF UART drivers, as in certain hardware designs this may be
undesirable or may even make certain hardware not working.
Instead, provide devicetree properties that allow enabling of those
resistors when it is actually needed.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The driver only support use case where the channels are used in mutual
exclusion.
Origin: Original
Signed-off-by: Guillaume Lager <g.lager@innoseis.com>
Update the Microchip XEC pinmux driver to use system I/O
routine for read/write of registers instead of direct use
of volatile and CMSIS defines. Add GPIO port number to
bindings instead of using hard coded value from chip headers.
Modify SoC DTSI pinmux syntax, requires "pinmux: pinumx {..."
or the DT macros will not work. Since pinmux is used by MEC152x
we update its chip pinmux DT.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add support for TI TLC59108 an I2C 8-bit LED driver.
Supported blinkink period: 41ms to 10730ms
Supported brightness value: 0 to 100%
This driver supports the following APIs:
1. led_blink
2. led_set_brightness
3. led_on
4. led_off
This is a modified version of the NXP PCA9633 driver.
Signed-off-by: John Kjellberg <kjellberg.john@gmail.com>
Use a comment syntax instead of a separator. This is a bit cleaner
and is prep work for moving the parsing code to a more generic place,
namely edtlib.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Update our vendor-prefixes.txt file to match the data in upstream
Linux's vendor-prefixes.yaml file as of Linux commit
8ac91e6c6033ebc12c5c1e4aa171b81a662bd70f.
(We can't easily switch to using the Linux YAML file directly because
our documentation tooling depends on this plain text format.)
The changes were done using a script and then cleaned up by hand in
order to not throw away any Zephyr-only prefixes, and to manually
override Linux in some cases.
List of Zephyr-only prefixes, all of which were kept:
asmedia
cadence
gaisler
lairdconnect
ovti
openisa
particle
quicklogic
ruuvi
segger
vnd
weact
zephyr
Other things to note:
- keep Espressif as 'espressif', overriding Linux's 'esp'
- 'gw' is deprecated in Linux and is unused here; just remove it
- ROCKTECH DISPLAYS LIMITED SHOULD HAVE BEEN ALL CAPS;
HOW COULD WE POSSIBLY HAVE MISSED THIS BEFORE?
- Did not include '70mai' from upstream, as that violates the legal
compatible regexp
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
based on uart rom functions, also enable console driver
on top if this driver enabling logging
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
The booter (bootloader) behavior may be different in different NPCX
chip series. One example is that the booter sets host interface type in
NPCX7 series but leave the firmware to set it in NPCX9 series.
This commit adds a new DT node to record variants in its properties.
NPCX drivers can understand if they need to configure the related
setting by checking the node's properties.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
dtc v1.6.1 produces an error without specifying #address-cells
on an interrupt-controller node.
Fixes#36495
Signed-off-by: Eric Johnson <eric@liveathos.com>
Add watchdog support to the mimxrt685 platform.
The mimxrt685 platform is excluded from the watchdog
test case because the test case uses variables in the
noinit section that need to be retained through a reset
but the rt685 does not retain this memory through a
reset.
Signed-off-by: David Leach <david.leach@nxp.com>
The Texas Instruments TCA9538 is an 8 pin GPIO port expander.
It operates on an I2C bus with 2 configurable address pins. The
device has an interrupt output pin that is asserted when any pin
configured as an input changes state.
Added under the PCA953X name to allow other similar parts to
use the same driver.
Signed-off-by: Kieran Mackey <kieran.mackey@lairdconnect.com>
Microchip MCP7940N is a Real-Time Clock/Calendar. It operates on a I2C
bus. It can be used to set a calendar time and has two alarm channels.
When an alarm is asserted the state of the MPF pin of the MCP7940N will
change (depending on gpio active high/active low setting) to trigger an
interrupt.
Signed-off-by: Kieran Mackey <kieran.mackey@lairdconnect.com>
Add Atmel sam0 sercom[uart] pinctrl bindings and implements pinctrl at
driver level. It changes all sam0 boards to use new feature and remove
pinmux driver dependency for sercom[uart]. The samples that require a
binding were update to keep consistency and avoid errors.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Busy simulator is using counter device and entropy device to
generate random cpu load. Counter device cofiguration can be
used to set cpu load interrupt priority and optional pin that
can be set during the load.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add initial basic description for Cortex-M33 based
stm32u5 soc series.
This encompass description for base nodes, such as:
- cpu
- flash
- clocks
- sram
Additionally, provide description for variant stm32u575Xi.
Related to clocks nodes, added bindings for stm32u5 specific
rcc node as well as msi and pll clocks.
Header file stm32_clock_control.h was also updated to support
these new bindings.
Note that for compatibility with existing definitions, clock
node describing main pll clock, known as "PLL1", was given two
labels: "pll" and "pll1".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The type of DMA for the stm32f0 devices was wrong
Its DMA is of type V2bis where the peripheral request is fixed.
The corresponding DMA cell has 2 elements.
The stm32f091 has two DMA instances.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a shim that allows using the nrfx I2S driver via the Zephyr API.
Add also missing devicetree nodes representing the I2S peripherals
in the nRF52 Series SoCs.
Extend the "nordic,nrf-i2s" binding with a new property that allows
specifying the clock source to be used by the I2S peripheral (so that
it is possible to use HFXO for better accurracy of the peripheral clock
or, in the nRF53 Series SoCs, to use the dedicated audio oscillator).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Create version 2 of the MEC GPIO driver to support MEC172x to not
interfere with MEC152x. When the MEC172x ECIA interrupt aggregator
driver is ready, this driver will use ECIA for registering GPIO
interrupt callbacks instead of maintaining its own interrupt table.
Add V2 DT binding.
Add the Kconfig configuration settings for the MEC172x GPIO
V2 driver at the SoC and board level.
Add port id to DT allowing use of DT FOR EACH macro in the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This driver supports the TI INA230 and INA231 Bidirectional Current
and Power Monitors. The devices work on the I2C interface and are
created from DT nodes with a compatible property matching "ti,ina23x".
The following datasheets were referenced while developing the driver:
https://www.ti.com/product/INA230https://www.ti.com/product/INA231
Twister passed:
twister -T tests/drivers/build_all/sensor/
Testing was performed on the stm32g071b_disco board with the following:
Load: ~170 ohms
Voltage: 5V
Measured Values:
Voltage: 5.1 V
Current: 0.032 A
Power: 0.157 W
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
This CL moves the phandles which don't contain 'reg' prop. from 'soc' to
'soc-if' node since they are the interface phandles only. It also
prevents "missing or empty reg/ranges property" warning messages.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
In the eeprom read operation, when rambuf was available
mutex was not unlocked after the read. Consequence of that is
that device was blocked after that read for incoming operations.
This commit fixes the issue
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add basic counter driver based on Timer Counter (TC) module for Atmel
SAM family.
Remarks:
- The driver is not thread safe.
- The driver does not implement guard periods.
- The driver does not guarantee that short relative alarm will trigger
the interrupt immediately and not after the full cycle / counter
overflow.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit adds dt definitions for the hw aes accelerator
on stm32g0 Series.
The accelertor is available on the following socs:
stm32g041, stm32g061, stm32g081, and stm32g0c1.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds a dt node for the hw aes accelerator of the
stm32l5 series.
The stm32l562Xe.dtsi file now includes the newly created
stm32l562Xe.dtsi with the additional aes definitions instead of the
stm32l552Xe.dtsi file.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds bindings for the STM32 AES accelerator.
Common properties of st,stm32-cryp are moved into
st,stm32-crypto-common.yaml.
The accelerator supports ECB, CBC, CTR, GCM, GMAC, and CCM
chaining modes.
128 bit bit data blocks with cipher key lengths of 128 and 256 bit are
supported.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add support for power management and the shutdown mode for bq274xx fuel
gauge sensor. This now allows boards that have any kind of low power
mode to turn on or off the sensor.
Tested on a Company's custom board with bq27421 sensor on it.
Signed-off-by: Luka Lopotar <luka.lopotar@greyp.com>
Each stm32 dma can be of V1 or V2 or V2bis type. Each type
has a dma-cell with specific nb of element. The feature and slot
properties are not required depending on the stm32 family.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This will define a new bindings for any stm32 dma feature
Depending on the soc family, the DMA is of V1 or V2 or Vbis type
And give a factored definition for feature
The difference is on the dma-cell structure.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This adds the dts to PASS the tests/drivers/dac/dac_loopback
on the nucleo_f429zi board, when PA0 and PA4 are connected.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds a driver implementation for the LM75 I2C temperature
sensor.
Signed-off-by: Alexander Wachter <alexander.wachter@leica-geosystems.com>
reuse the lpc's lpadc driver for rt1170, modify the dts and add
some macro to shield some code of LPC series. Also add the
board support inside the tests/drivers/adc/adc_api/src/test_adc.c,
and a dts node:zephyr,user inside
samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay
Signed-off-by: Crist Xu <crist.xu@nxp.com>
This patch states that the Everlight B1414 LED controller is compatible
with the Worldsemi WS2812. Some information about it is added to the
WS2812 DT binding and driver Kconfig files.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Some devices compatibles with the WS2812 IC have a different reset/latch
delay.
This patch introduces the "reset-delay" optional property for the WS2812
DT binding and adds support to the ws2812_spi driver. This new property
allows to configure the reset/latch delay of a WS2812 compatible LED
strip controller from its DT node.
If omitted the driver uses 8 microseconds by default (which is good for
the WS2812 IC).
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Some devices compatibles with the WS2812 IC have a different channel to
color mappings (e.g. RGB, BGR, RGBW, etc).
This patch introduces the "color-mapping" required property for the
WS2812 DT binding and adds support to the ws2812_gpio and ws2812_spi
drivers. This new property allows to configure the color to channel
mapping of a WS2812 compatible LED strip controller from its DT node.
Since this property also allows to know if a white channel is available,
then this patch removes the "has-white-channel" property.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Add a new property to the "nordic,nrf-clock" binding to allow
configuration of the HFCLKAUDIO frequency.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Adding support for the stm32l051 devices.
Signed-off-by: Even Falch-Larsen <even.falch.larsen@nomono.co>
Co-authored-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added minimal device tree and board files to build Microchip
MEC172x. SOC layer stripped down to allow build for checking
compilation only.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The zephyr sam gmac driver don't get register address and, in some
cases, peripheral id from devicetree. This replace headers constants
in favor of devicetree values.
This fix wrong Atmel SAME7x/SAMV7x gmac register address and add
missing peripheral id property for SAM family.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current GMAC compatible not allow especialize properties by SoC
family. Split current generic Atmel GMAC compatible into two new
compatibles which are defined by SoC families. This increase the
freedom and avoid odd situations.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This fixes properties documentation and two devicetree styles:
- properties with wrong code identation and
- property description tag style
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
A syscon device is a device managing a memory region containing a set of
registers that are not cohesive enough to represent as any specific type
of device. We need a driver for that because several other drivers could
use the same region at the same time and we need to io-map the region at
boot for MMU enabled platforms.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Define the subghz radio node in the module dtsi file, with the internal
RF switch connection and TCXO setting, and point at it from the
corresponding dev board file.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Add a device node for the subghz radio in stm32wl.dtsi. The radio is
present in all chips of the series, so having the node there with the
common properties simplifies the board dts files.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
This adds support for controlling the SUBGHZSPI NSS line in STM32WL
devices. This is a special dedicated SPI port only connected to the
radio device internally, chip select happens through a bit in the PWR
module. Adding a special dt-property to identify the port, it all gets
built out on non-WL devices.
Deduplicate the existing dts bindings in the process, and add the new
one for the special spi with the new property.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Add a dts node for st,stm32wl-subghz-radio. The device is integrated in
STM32WL series SoCs, and based on the sx1262, but it does not use any
gpio as all the necessary signals are internally connected to various
SoC units.
To account for that, make the redundant gpio optional in the template
files, but mark them as required in the sx1261 and sx1262 definitions,
to match with what's used in the driver.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The STMPE1600 is an I2C based GPIO expander. This initial patch
only supports reading from/writing to the pins on the STMPE1600,
and there is currently no support for interrupts.
Signed-off-by: Titouan Christophe <moiandme@gmail.com>
Introduce a set of header files to be able to define and declare
sections and regions in the linker script. Introduce also DT helpers to
retrieve data back.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add driver for sensirion consumer humidity sensor line.
Supports shtc1 and shtc3, but only shtc3 is tested.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add I2C bus initial support to Renesas R-Car SoC series.
Both I2C2 & I2C4 buses are supported on R-Car H3 board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Third generation R-Car series products have up to
seven I2C bus interfaces conformant with the
Philips Semiconductors (now NXP Semiconductors) I2C bus
(Inter-IC bus) specification.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Use GPIO output high and low to simulate I2C start and stop
conditions to restore i2c to normal.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Create the pinmux phandle to the I2C driver node in the
devicetree. When the pinmux_pin_set function in
i2c_it8xxx2_init can refer to the setting of this phandle.
It is more flexible to use.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add single-register MMIO GPIO driver for complex cases where
only several fields in register belong to GPIO lines and each GPIO
line owns a field with different length and on/off value.
Such CREG GPIOs are used in Synopsys em_starterkit and HSDK boards.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
This commit adds the dt node for rng to the stm32wl series
and sets it as chosen zephyr,entropy source.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds support for stm32g0 socs with integrated rng and hw aes
acceleratior, which are stm32g041, stm32g061, stm32g081, and stm32g0c1.
It also adds the definitions for the rng peripheral
and sets it as chosen zephyr,entropy source.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds the dts definitons for the seeed lora-e5 module.
Additionally I add myself as codeowner for the new dts/arm/seeed
directory.
This module packages a stm32wle5jc Sub-GHz Wireless Soc,
together with a 32MHz TCXO, a 32.768KHz crystal oscillator, and
power and RF circuitry.
With the introduction of lora support definitions for the radio
will be added in a future commit.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds dt support for stm32wle4, and stm32wle5 single core,
as well as stm32wl54 dual core socs.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This property has been marked as deprecated in 2.5.0 and was not
actually used for even longer time.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This commit adds dma1, dma2, dmamux support in dtsi for stm32l5
series. This commit also fixes a compilation warning due to the
usage of upper case in "reg = <0x4000F400 0x400>".
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
The nRF QSPI has a configurable delay from the rising
clock signal to the actual sample point measured in
clock cycles. This commit exposes that delay as a DTS
parameter without modifying existing behavior.
Signed-off-by: Abram Early <abram.early@gmail.com>
add devicetree node for usart4 and usart5. usart4 and 5
shares the same interrupt line (14), hence both can't be enabled
at the same time.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add basic support for TI HDC20XX series (e.g. HDC2010, HDC2021, HDC2022,
HDC2080). It is able to get temperature and humidity in the default
14-bit resolution. Triggers, resolution selection, interrupt line, auto
measurement mode are currently not supported.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Nuvoton provides different series MCU. The NPCX series has a specific
id, which can identify the real chip part number. This CL adds soc id
for the NPCX series.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
And removes the odd esp32c3 competible from it
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
hal_espressif repository was updated from esp-idf v4.2
to esp-idf v4.3 to allow latest Espressif chips integration.
As a consequence, it added a few changes in drivers
and peripherals. To maintain bisectability, changes in this
PR cannot be split. Here are some details:
wifi: update linker script by adding libphy and new attributes.
spi: update some APIs and fixed missing wait_idle check
west.yml: esp32: update hal to new version
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit adds max-erase-time element which holds the
maximum erase time of a sector or page or half-page for
all the series of stm32.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This commit defines max-erase-time element inside flash-controller
to be part of device tree.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Add the lptim1 device node definition and enable the corresponding
exti interrupt in sys_clock_driver_init().
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The PS/2 module in npcx provides a hardware accelerator mechanism
including an 8-bit shift register, a state machine, and control logic
that handle both the incoming and outgoing data. The hardware
accelerator mechanism is shared by 4 PS/2 channels. To support it,
this CL separates the PS/2 driver into channel and controller drivers.
The controller driver is in charge of the PS/2 transaction. The channel
driver is in charge of the connection between the Zehpyr PS/2 API
interface and controller driver.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Move lis2dw12 trigger pulse configurations from Kconfigs to Device Tree.
Moreover the dts properties have been renamed as 'tap', which sounds a
better name to immediately catch the feature behind it. Since tap
threshold cannot be zero, this value (which is the default in dts
binding) is used to enable/disable the device feature per each axis.
The event can be generated on INT1 only.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Take the int-pin information (i.e. what pin between INT1
and INT2 the drdy is attached to) directly from DT.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Create a common binding file that will be included by all bindings
handled by lis2dw12 driver.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add a device node for the FMC controller found in stm32f427, f437 and
f446 devices, works fine with the current memc_stm32_sdram driver.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
bits property indicates the number of in-use slots of available slots
for GPIOS. We have a similar property ngpios in gpio-controller.yaml,
we will use ngpios to calculate port_pin_mask. Let's remove bits and
only use ngpios.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
The NXP LPC syscon driver failed to build on several platforms for
various reasons. We need dts support on LPC55s1x and LPC55s2x, the
driver doesn't seem like it will work on LPC54114 so we exclude it
there for now.
Additionally, fix a dtc warning on LPC55s6x based on unit-address in
the node naming needing to be lowercase.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add flash driver for it8xxx2. The driver can implement
flash read, write and erase that will be mapped to the
ram section for executing.
TEST="flash write 0x80000 0x10 0x20 0x30 0x40 ..."
"flash read 0x80000 0x100"
"flash erase 0x80000 0x1000"
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
The atmel pwm driver doesn't have a easy way to test and show
functionality to users. This re-assign led-0 function from
gpio-leds to pwm-leds. The current led-0 entry at gpio-leds
was keep with status disabled, as refence. It allows test pwm
driver for SAM Cortex-M7 MCUs. The led-1 assume Zephyr sample
default led0 alias.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add the device tree data for the 4 Ethernet controllers integrated into
the ZynqMP SoC, GEM0 to GEM3.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add support for the Xilinx GEM Ethernet controller, which is integrated
in both the Xilinx Zynq and ZynqMP (UltraScale) SoC families. The driver
supports the management of a PHY attached to the respective GEM's MDIO
interface.
This driver was developed with ultimately the Zynq-7000 series in mind,
but at the time being, it is limited to use in conjunction with the
ZynqMP RPU (Cortex-R5) cores. The differences are minor when it comes
to the adjustment of the TX clock frequency derived from the current
link speed reported by the PHY, but for use in conjunction with the
Zynq-7000, some larger adjustments will have to be made when it comes
to the placement of the DMA memory area, as this involves the confi-
guration of the MMU in Cortex-A CPUs.
The driver was developed under the qemu_cortex_r5 target. The Marvell
88E1111 PHY simulated by QEMU is supported by the driver.
Limitations currently exist when it comes to timestamping or VLAN
support and other minor things. Those haven't been implemented yet,
although they are supported by the hardware. In order to be fully
supported by the ZynqMP APU, 64-bit DMA address descriptor format
support will be added.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
This CL introduces six properties, clock-frequency, core-prescaler,
apb1/2/3/4-prescaler in pcc (Power and Clock Controller) node to
configure clock settings. It also removed the original Kconfig options
used for the same purpose.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit fixes the compilation warning occurred due
to usage of upper case in "interrupt-controller@4000F400".
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This commit adds PWM support in dtsi for stm32l5 series. Adding
other timer nodes for different stm32l5 series PWM capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Convert the keyscan portion of the Holtek HT16K33 driver to adhere to
the kscan API instead of the GPIO API.
When this driver was introduced the kscan API was not present. The
keyscan driver was therefore implemented as a GPIO interrupt driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
GPIOTE1 on the nRF5340 SoC is always accessible as a non-secure
peripheral. However, it is only defined in the non-secure DTSI file.
This is therefore a missing node in the secure DTSI file, since
non-secure addresses are accessible by secure software.
Move the node definition to a common include file and pull it into the
app core DTSI as well. To keep things clean, adjust the node labels so
that:
- 'gpiote0' and 'gpiote1' are defined in the secure DTSI
- 'gpiote0' is not defined in the non-secure DTSI
- 'gpiote' is defined in both secure and non-secure DTSIs
- 'gpiote' refers to the same node as 'gpiote0' in the secure DTSI
- 'gpiote' refers to the same node as 'gpiote1' in the non-secure DTSI
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The sram1 node in nrf5340_cpuapp.dtsi represents the SRAM accessible
to the network core on the SoC.
However, while the network core can access the app core's SRAM, the
app core cannot access the net core's SRAM. Therefore, the sram1 node
should only appear in DTSI files for the net core, and not the app
core.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The RAM of can instances starts directly after it's predecessor.
This commit fixes can2 and can3 support for stm32g4 series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Property "st,prescaler" of binding "st,stm32-pwm" was set to 2
different default values 0 or 10000 in *.dtsi files.
Since this property rather depends on application than hardware
description, there is no reason to have 2 different default values
in use. Besides, it is a trap for pwm users that should take into
consideration this random default value.
Fix this by defaulting the property systematically to 0.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add radio peripheral to nrf5340_cpunet DTS. The peripheral
description includes antenna matrix congiuration for Direction
Finding extennsion.
Appropriate binding file for nRF radio peripheral already egxists.
There is no default antenna matrix configuration. Antennas number
and GPIOS mapping to DFEGPIOS is project specific.
Complete configuration must be provided by end user as overaly.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Moved can, spi, usb, usb_fs_phy nodes to f103X8 dts.
Adds CAN for f103X8 series.
Tested on stm32f103c8 soc.
Tested on stm32f103vb soc.
Signed-off-by: Bhavesh Bhojwani <bhaavesh.bhojwaani@gmail.com>
Add radio peripheral to nrf52820 DTS. The peripheral description
includes antenna matrix congiuration for Direction Finding extennsion.
Appropriate binding file for nRF radio peripheral already egxists.
There is no default antenna matrix configuration. Antennas number
and GPIOS mapping to DFEGPIOS is project specific.
Complete configuration must be provided by end user as overaly.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Create the pinmux phandle to the ADC driver node in the
devicetree. When the pinmux_pin_set function in
adc_it8xxx2_channel_setup can refer to the setting of
this phandle. It is more flexible to use.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit adds DAC1 support in dtsi for stm32f3 series. Some
stm32f3 series has DAC2 so adding the same where applicable.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This commit adds a closing parenthesis for soc model of stm32g050.
Resolves issue #36014
Signed-off-by: Bhavesh Bhojwani <bhaavesh.bhojwaani@gmail.com>
Since the valid bit-depth of RAM_PDn registers are different, this CL
introduces a 'ram-pd-depth' property in 'nuvoton,npcx-pcc' node if the
application needs to turn off the partial ram blocks for better power
consumption.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add multi-instance support and make use of the stmemsc i2c/spi
read/write routine that has been introduced to simplify the ST
sensor drivers code.
Moreover, move spi-full-duplex property from Kconfig inside Device
Tree, so that each LIS2MDL instance can be configured selectively
in accordance to how it is used in h/w.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
LiteX GPIOIn module provides possibility to change IRQ mode
and edge via CSRs. This commit adds support for that feature.
Signed-off-by: Robert Szczepanski <rszczepanski@internships.antmicro.com>
This adds missing option to disable IRQs.
Devicetree is modified to match previous commit with custom IRQ CSR
addresses.
Signed-off-by: Robert Szczepanski <rszczepanski@internships.antmicro.com>
This commit adds support for GPIO interrupts in GPIO driver for Litex
SoC Builder.
Signed-off-by: Robert Szczepanski <rszczepanski@internships.antmicro.com>
Arrange device-tree files of npcx7 series by following steps:
1. Move device-tree declarations of npcx family to npcx.dtsi.
2. Leave specific device declarations of npcx7 series to npcx7.dtsi.
3. Move chip series related mapping tables such as
npcx7-miwus-wui-map.dtsi and so on to npcx/npcx7 folder.
4. Move common device-tree declarations used in each npcx series to
npcx-miwus-wui-map.dtsi and so on to npcx folder.
Then, the npcx device-tree folders are arranged to:
dts/arm/nuvoton
|--npcx
| |--npcx7
| | |--npcx7-miwus-wui-map.dtsi
| | |--npcx7-alts-map.dtsi
| | |--.....
| |--npcx-miwus-wui-map.dtsi
| |--npcx-alts-map.dtsi
| |--.....
|
|--npcx.dtsi
|--npcx7.dtsi
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces series-prefix "npcx7-" with family-"npcx-" for npcx dts
nodes such as 'espi-vws-map' and 'miwus-int-map'. Since we plan to
introduce the npcx9 and later series, adding a new node such as
npcx9-espi-vws-map for each series is more complicated and not
necessary.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add a port property to describe which hardware port a GPIO device node
is describing since we can't tell from the registers (as the registers
are interleaved in the same MMIO space).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove (disabled) MPU support for the NXP Kinetis K2x. At least the
MK22F51212, which is the only K2x supported by Zephyr so far, does not
contain an MPU.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Change the drivers's compatible from atmel,sam-tc to atmel,sam-tc-qdec.
The atmel,sam-tc should be reserved for the future counter driver.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
The change removes the following warning:
Warning: /soc/tc@4000C000: simple-bus unit address format error,
expected "4000c000"
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
These compatibles don't match the dt-schema regular expression for
compatible properties that we'd like to support in Zephyr because they
do not begin with a letter.
Use linaro, as a vendor prefix to make them compliant. Update the
release notes since out of tree users will need to keep up.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This patch adds a label property to the GPIO LED parent node and fixes
the label property description of the child node. Indeed it is the label
of a parent node which can be used as device_get_binding() parameter to
retrieve the LED device, and not the one of a child node.
In addition, this patch sets both this properties as not required
because they are not.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This patch adds a label property to the PWM LED parent node and fixes
the label property description of the child node. Indeed it is the label
of a parent node which can be used as device_get_binding() parameter to
retrieve the LED device, and not the one of a child node.
Fixes#34275
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Device Tree address mixup between
SAI2 <-> SPI2 and SAI3 <-> SPI3
Add functionality to SPI2/3
Tested on SPI2
Signed-off-by: Rico Ganahl <rico.ganahl@bytesatwork.ch>
Switch the interrupt controller address to lower case to avoid this
warning:
stm32f723e_disco.dts.pre.tmp:97.39-102.5: Warning (simple_bus_reg):
/soc/interrupt-controller@40013C00: simple-bus unit address format
error, expected "40013c00"
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The default status of UART should set disabled.
If UART needs to enable, it will be set in the
dts of board level.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
STM32 internal temperature sensor driver.
This sensor can be used to measure the temperature of the CPU
and its surroundings.
Signed-off-by: Eug Krashtan <eug.krashtan@gmail.com>
Enable FlexSPI NOR flash driver with XIP build options.
Configure FlexSPI pins, update board documentation.
Add FlexSPI NOR flash dts node for mimxrt685_evk.
Enable flash storage by adding partition to dts file.
Using last 1MB for storage, and reserving 63MB for code.
Signed-off-by: Saurabh Jagdhane <saurabh.jagdhane@nxp.com>
Adding Reset and Write-protect pins initialization during AT45 driver
start-up. Usually these pins are driven high when not used.
The AT45 device incorporates an internal power-on reset circuit, so
there is no initial on-off reset sequence.
Signed-off-by: Eug Krashtan <eug.krashtan@gmail.com>
Implementation of the Bosch M_CAN IP driver.
This driver is just the base for a specific SoC implementation.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
Added support for GPIO driver for Intel Elkhart Lake
board.
The GPIO driver will support pin value read/write operations,
pin direction and interrupt configuration. ACPI enumeration
support and support for different GPIO communities is also
present.
Verified on ehl_crb.
Signed-off-by: U Divya <u.divya@intel.com>
ADC emulator is designed to be used in tests on native_posix board. It
supports 1-16 bit resolution range and all GAINs from enum adc_gain.
Reference voltages and number of emulated channels are set through dts.
Using special API from drivers/adc/adc_emul.h it is possible to set
constant voltage value returned by given ADC channel or set custom
function which allows to simulate complex output.
Also reference voltages can be changed in runtime using the API.
The CL also includes:
- Add adc definitions of ADC emulator in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
- Add test for ADC emulator API in tests/drivers/adc/adc_emul/
Signed-off-by: Tomasz Michalec <tm@semihalf.com>
add dts bingings for dma usage
add dts support for adc with edma and hwtrigger
add a periodic_trigger feature to dts
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Add SCIF bus initial support to Renesas R-Car SOC series.
SCIF1 is used as main serial and shell output on R-Car H3 board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Renesas has Serial Communication Interface with
FIFO (SCIF) hardware block which allow asynchronous and
synchronous serial communication. The SCIF has 16-stage FIFO
buffers separately for transmissions and reception.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Commit 233149eec5 moved flash sram nodes
under /soc for various nordic ICs, but the indentation isn't right for
52811. Fix it.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Recently WiFi ESP32 driver (utilizing WiFi radio in ESP32 SoC) was
introduced into drivers/wifi/esp32/ and it already caused confusion as
there was existing drivers/wifi/esp/ directory for ESP-AT
driver (utilizing external WiFi chip, by communicating using AT commands
from any serial capable platform). So question has arisen whether it is
good to merge both, while they are totally different drivers.
Rename ESP-AT driver to be placed in drivers/wifi/esp_at/, so that it is
easier to figure out difference between "esp32" and "esp_at" just by
looking at driver name. Rename also DT compatible and all Kconfig
options for the same reason.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Remove reset pin requirement from devicetree as this
is not required for modem functionality, and is not
used in the driver anyways.
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
For dmamux nodes the dma-requests property specifies the number of
peripheral request inputs(not nr. of request trigger inputs).
This commit fixes this for g4 series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The MAX17262 is an ultra-low power fuel-gauge IC which implements the
Maxim ModelGauge m5 algorithm. The IC monitors a single-cell battery
pack and supports internal current sensing for up to 3.1A pulse
current. The IC provides best performance for batteries with 100mAhr
to 6Ahr capacity.
Signed-off-by: Matija Tudan <mtudan@mobilisis.hr>
reg value should match value provided within node name (as in pll@2).
Fix this to avoid warning.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add pinctrl-0 as being required on NXP Kinetis DTS bindings for I2C,
FTM, UART, and DSPI related devices.
Other devices like ethernet and CAN are utilized outside of just the
Kinetis family and thus we can not require pinctrl-0 property for them
at this time.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As the KW2XD is a SiP (System-in-package) the SPI1 controller on the MCU
is connected to the modem. As the pinctrl details for this in the
SoC dtsi file as these pins are not exposed in the pindata XMLs from
NXP.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Set SPI0 controller to default to being disabled in SoC dtsi files and
having the board dtsi files enable it. The only board that wasn't doing
this already was the frdm_kw41z.dts.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add specific binding for stm32f100 pll which differs from existing
stm32f1 and stm32f105 specific pll binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Automatic collision detection for half-duplex mode can be enabled
by setting `collision-detection` proprety for uart hardware
in the dts file. If the transmitted bit does not match the received
bit an error is raised. This is useful in RS-485 half-duplex mode.
Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
Add binding fro stm32wl-rcc.yaml that derivates from stm32wb-rcc.
Additionally update stm32wb-pll-clock.yaml to be used as well
for stm32wl series and add missing div-m property.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clocks node and clocks to stm32l5 series.
PLL binding is reused from stm32l4 series.
Matching binding is updated to document that.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clocks nodes for F0/F3/G0/G4 series.
For F0 and G0 series, update compatible for rcc node
to specify use of dedicated "st,stm32f0-rcc" compatible.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add bindings for F0/F3/G0/G4 clocks.
Introduce new rcc binding "st,stm32f0-rcc" binding
that describes RCC hardware blocks that don't have
"apb2-prescaler".
This binding also applies to G0.
Binding "st,stm32f0-pll-clock" is used for both F0
and F3 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add PLL bindings for STM32F1 devices.
- Main PLL binding for STM32F1 non connectivity lines
- Main and PLL2 binding for Connectivity lines (F105/F107)
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove default pll settings to ensure pll users are correctly
configuring all prescalers on purpose and avoid surprises.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds flash clock settings in device tree for stm32h7
series such that the stm32h7 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The current serial driver uses hard code configuration. Rework driver
to use pinctrl and enable full configuration from device tree.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Add a function that uses the JESD216 SFDP BFP DW16 Enter 4-Byte
Addressing parameter to put the device into 4-byte addressing mode if
one of the entry modes that's supported by the driver is available on
the device.
Perform the transition if SFDP data is provided (either by devicetree
or at runtime), or if a special devicetree property provides the entry
mode descriptor.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Provided nodes reflect the clock tree of each series.
Clock nodes are disabled by default but populated with default
start up configuration. Main reason is the we don't want to
impact boards using Kconfig based clock configuration for now.
Exception to these rules:
- syslck: Default enabled, clock frequency and clock source not
provided
- pll: clock source not provided
This is made on purpose so that errors are triggered if parameters
essential to the board configuration are not provided.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This CL adds a override mechanism for pwm module's input clock source
assignment. If the 'clock-bus' property exists, the NPCX_DT_PROP_ENUM_OR
macro function will return an enum upper token value. Otherwise, it
expands to default value in 'clocks' property.
For example, if the users want to select LFCLK as pwm0's input clock,
ths node can be overridden by adding 'clock-bus' property with an enum
string, "NPCX_CLOCK_BUS_LFCLK".
&pwm0 {
status = "okay";
clock-bus = "NPCX_CLOCK_BUS_LFCLK";
};
Signed-off-by: Keith Short <keithshort@google.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
i2s1 is not present in all stm32f4 series. So moving the i2s1 node
from the top level stm32f4 dtsi file to the stm32fxx specific dtsi
files. Also in stm32f429zi, the sequence starts from i2s2, this commit
helps in having the right channel number.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
STM32G0 is supported by the st,stm32-dma-v2 driver.
This commit adds dma1 and dmamux dts bindings
for stm32g03x, stm32g05x and stm32g07x.
For stm32g0bx additionally dma2 is added.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Exit latency is the maximum time required by a CPU to transition from
a specific idle state to active state. This information is going to be
used to properly configure the wake up event in order to the system be
able to execute the next scheduled task.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This patch adds flash clock settings in device tree for stm32wb
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32l4
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32l1
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32g4
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32g0
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This change enables A, C, D, E, G, H, I, J, K, and L groups,
and fix gpio interrupt function.
This change also pull (and rename) dt-bindings/irq.h to
dt-bindings/interrupt-controller/ite-intc.h, because it is
chip-specific.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
NPCX PWM supports output buffet select to push-pull or open-drain. Add
output buffer select option 'drive-open-drain' in devicetree for NPCX
PWM. If set, the PWM output will be configured as open-drain. If not
set, defaults to push-pull.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
The binding-template.yaml file has grown organically into something
that's out of control.
It makes too many 'see above' and 'see below' references to be read
comfortably, and we can't cross reference from YAML.
There are also many example DTS and YAML fragments scattered about in
comments, which cannot be syntax highlighted properly.
Fix that by overhauling the documentation into bindings.rst in the DT
guide. This will let us link to individual sections when answering
questions, allows us to cross-reference and use '.. code-block::',
etc.
A couple of things need to go to other pages.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
1. add a seperate 2 cores SMP board configuration to run in Jailhouse
inmate Cell, root Cell Linux will use Core0 and Core1, Zephyr will
run on Core2 and Core3.
2. Refine the code of dts, move SoC common dts nodes into dtsi fiel in
dts/arm64/nxp/ directory.
3. Add myself to be code owner of directory dts/arm64/nxp/.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Enabling pwm on timer3 for stm32l1 series in dtsi.
Adding other timer nodes for pwm capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Renesas RCar Gen3 series have up to 8 GPIOs
bank.
Add bank 5 and bank 6, that is used to manage user led and
switches on different demo board.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The Compare match timer can be found on Renesas
RCar Gen3 soc series.
It depends on clock controller to supply clock to the
CMT module.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7
processor.
This processor has access to the same memory mapped devices than
the Cortex-A5x cores.
- CPU operates upto 800MHz
- Can use ram area from 0x40040000 to 0x42000000
- Has 512 interrupts on GIC-400 compliant with Arm GICv2
Add support for r8a77951 as first SoC of this series which is also
known as H3 ES2.0 and is present present on different boards such as
Salvator and R-Car Starter Kit(H3ulcb).
This first SoC definition is just enough to print Hello World in a
ram console.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
These changes turn out to have been incompatible with the way pinctrl
drivers are going to work, so we need to go back to what we had before
until we can agree on a better approach.
Squash of the following reverts:
Revert "boards: nrf: fix deprecated I2C properties"
This reverts commit 2a4ac9ac02.
Revert "samples: switch nrf overlays to sda-gpios, scl-gpios"
This reverts commit 01bb08e7d8.
Revert "boards: nrf: switch to sda-gpios, scl-gpios"
This reverts commit 17a66304c4.
Revert "i2c: nordic: switch to phandle arrays for pinmux"
This reverts commit 821c03a14a.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
When 1.8V is disabled, sdhc can only
communicate at low speed. But this can
save the external circuit for switching
between 3.3V and 1.8V, which is very
practical in costdown scenarios.
Signed-off-by: Frank Li <lgl88911@163.com>
Enabling PWM on timer1 for STM32F2 platform in dtsi.
Adding other timers nodes for PWM capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Some SPI NOR devices, particularly Atmel and SST, power-up with block
protect bits set in the status register. These bits must be cleared
before any erase or program operation can succeed. However, blindly
clearing bits in SR is wrong as some of these are non-volatile and
control chip behavior, including quad-enable.
Add a devicetree flag to identify device-specific BP bits in the status
register that should be cleared on startup only for devices that need
them, and when set do the clear during initialization.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Define the FLASH_CCFG memory region from a devicetree partition instead
of from math in the linker file. Removing the special math case results
in the FLASH_CCFG region overlapping the FLASH region, but the linker
accepts this until the FLASH region actually starts placing variables
in the FLASH_CCFG region.
As a result, applications that don't fit in (FLASH_SIZE - 88) bytes will
still fail to link, just with an overlapping memory region error instead
of an overflow error.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Move the definition of the two IPC RAM blocks from `#define`'s in family
linker scripts to proper devicetree nodes. Use the devicetree nodes to
generate the memory regions.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Currently the SRAM location is fixed for all the boards derived from
qemu_cortex_a53. While this is acceptable when the image is directly
loaded in SRAM by QEMU, in some cases Zephyr can be loaded in RAM by
another piece of software or by semihosting at a different address
before jumping into it.
When for example TF-A is used and Zephyr is run as BL33 payload using
QEMU, in this case the default location in RAM is at a different
address (when preloaded BL33 base address is not used).
To address these cases, move the SRAM location into the board-specific
DTS so that it can be adjusted on a board by board basis.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is about the it8xxx2 analog to digital converter
driver. Support 8 channels ch0~ch7 and 10-bit resolution.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fixed the name of nodes in in espi-vw, miwu-wui, and miwu-int
device-tree node. This CL fixed missing nodes in CL d3a94fa8ab.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The following is the interrupt priority plan for ec application.
The original IRQ priority map in Chromium EC is:
- IRQ priority 0:
|-ITIM IRQ for Warning watchdog.
-IRQ priority 1:
|-UART IRQ for signle byte FIFO in npcx5 series.
(Ignore it since UART has 16 bytes FIFO in npcx7 and later series.)
-IRQ priority 2:
|-SHI IRQ for FIFO FULL and Half FULL event.
|-MIWU IRQ for SHI CS. (Wake-Up ASAP for handling data from SPI bus.)
-IRQ priority 3:
|-All MIWU IRQs for GPIO, MTC and eSPI VW events.
|-ITIM IRQ for task scheduling.
|-ITIM IRQ for time-out.
(No need in Zephyr since 64-bit timer support.)
IRQ priority 4:
|-All UART FIFO IRQs
|-All I2C controller IRQs
|-ADC IRQ for conversion event.
|-ESPI IRQ for generic eSPI bus events.
|-Host KBC IBF/OBE IRQs
|-Host PM IBF/OBE IRQs
|-Host port80 IRQ
|-PECI IRQ
IRQ priority 5:
|-Keyboard RAW IRQ
|-PS2 IRQ
Then, this CL arranges the priority of npcx interrupts in Zephyr as:
IRQ priority 0:
|-Reserved it for further requirements.
IRQ priority 1:
|-SHI IRQ for FIFO FULL and Half FULL event.
| (Will modify it in ec repo.)
|-MIWU IRQ for SHI CS (Will modify it in ec repo.)
IRQ priority 2:
|-MIWU IRQ for GPIO, MTC, T0 timer and eSPI VW events.
|-ITIM IRQ for task scheduling.
IRQ priority 3:
|-All UART FIFO IRQs
|-All I2C controller IRQs
|-ADC IRQ for conversion event.
|-ESPI IRQ for generic eSPI bus events.
|-Host KBC IBF/OBE IRQs
|-Host PM IBF/OBE IRQs
|-Host port80 IRQ
IRQ priority 4:
|-Keyboard RAW IRQ. (Will modify it in ec repo.)
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
For i2c-devices, reg is the address. This took me way to long to
discover and I wanted to leave a breadcrumb for the next Zephyr newbie.
Signed-off-by: Jeremy Bettis <jbettis@chromium.org>
First version of a driver for the st773r LCD controller.
Based on st7789v
Signed-off-by: Kim Bøndergaard <kim@fam-boendergaard.dk>
Signed-off-by: Kim Bøndergaard <kibo@prevas.dk>
Cortex M0 Series only have two interrupt priority bits,
nevertheless all series set the priority per default to the invalid
value of 7.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Update the binding for how we represent pin data to support child
nodes with a nxp,kinetis-pins property that has the pin data.
For example:
UART0_CTS_PTA0: uart0_cts_pta0 {
nxp,kinetis-port-pins = < 0 2 >;
};
Also pull in pincfg-node.yaml to get various common pin flags like
"bias-pull-up", "drive-open-drain", etc.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixed the name of nodes in device-tree files by following rules:
If object is 'phandles', use underscores for object name.
If not, such as 'node' or 'property', use hyphens for object name.
This CL also applies normal style for all nodes in npcx device-tree
files.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add the ability to filter which properties get imported when we do an
include. We add a new YAML form for this:
include:
- name: other.yaml
property-blocklist:
- prop-to-block
or
include:
- name: other.yaml
property-allowlist:
- prop-to-allow
These lists can intermix simple file names with maps, like:
include:
- foo.yaml
- name: bar.yaml
property-allowlist:
- prop-to-allow
And you can filter from child bindings like this:
include:
- name: bar.yaml
child-binding:
property-allowlist:
- child-prop-to-allow
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Take the int-pin information (i.e. what pin between INT1
and INT2 the drdy is attached to) directly from DT.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Create a common properties file that will be included by all bindings
(as i2c and spi) handled by lsm6dso driver.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Currently the MAX17055 driver assumes that a battery matching the
default characteristics is used.
This change allows battery characteristics to be specified in device
tree and writes them to the MAX17055 on initialization.
Existing default values are maintained for backwards compatibility.
Initialization routine taken from MAX17055 Software Implementation
Guide, document UG6365.
Signed-off-by: Hayden Ball <hayden@playerdata.co.uk>
The adc1 of the stm32f373 uses an address space and a bus that are
different from the other microncontrollers of the f3 family. So, let's
remove the adc1 node from the stm32f3.dtsi and add it directly, with
respective correct values, in each of the SoC variant files.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
STM32L011 and STM32L031 do not support USART1.
This commit moves the definition of the node to only
be present for MCUs which support the peripheral.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
TIM7 peripheral was defined for all STM32L4 chips
in the device tree when not every chip supports it.
This commit moves the node so that only chips
which support the peripheral have the node defined.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
The device tree includes CAN node can1 for all
STM32L4 chips when in fact they don't all support it.
This affects STM32L412xx and STM32L422xx.
Fixes#33896
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
Use a combination of fixed-clock and fixed-factor-clock devicetree
nodes for describing the clock dividers/multipliers of the NXP Kinetis
System Clock Generator (SCG) present in the KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Split ARM and ARM64 architectures.
Details:
- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
(arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
boards/bcm_vk/viper directory
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Support single mode operation by enabling it and
making the driver to use the interrupt to findout
when the data is ready for fetch. The sample fetch
will be blocked for a specified maximum time untill
the interrupt happens.
* Make operation mode configurable in DTS file
* Make offset cancellation configurable in DTS file
* Use single common .yaml file for both i2c and spi
* Store above configurations in dev->config_info
Signed-off-by: Masoud Shiroei <masoud.shiroei@assaabloy.com>
This commit creates two new files in the device tree
1. stm32l412X8.dtsi
2. stm32l412XB.dtsi
This will specifcally add stm32l412X8 to the device tree
which was not supported before. Also the memory
for stm32l412XB was not defined specifically before.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
Add remaining NXP KE1xF SoC dtsi files to support out-of-tree boards
using other variants of the KE1xF than the single in-tree board.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add dts files for the specific chip instances that are used on the
boards in prep of having pin data in devicetree. The pin data will
be specific to the given chip instance so we need to distinguish
unique chips for the same SoC as the pin mux will differ.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch introduces the support of the Low Power Timer
for the STM32L5xx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enabling I2C-1,2,3 support for STM32F2 platforms in dtsi.
This has been tested with mpu6050 sample application on I2C-1.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Enabling SPI support for STM32F2 platforms in dtsi.
This has been tested with test_spi_loopback on SPI-1.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This CL introduces the Power Switch Logic (PSL) pads which detect the
wake-up events and turn on/off core power supply (VCC1) for ultra-low
-power consumption in npcx device-tree file.
By adding PSL input-pad objects, psl_in1, psl_in2, and so on, into
'psl-in-pads' property and configuring their 'flag' properties, the
related driver will configure them via soc specific functions later.
For example, if PSL input 1 pad that is plan to detect a 'falling edge'
event, this property should be:
vsby-psl-in-list {
psl-in-pads = <&psl_in1>;
};
And the flag property in psl_in1 should change to
&psl_in1 {
flag = <NPCX_PSL_FALLING_EDGE>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Make sure that child bindings with their own compatibles are treated
as first-class bindings. Do this by making sure that nodes whose
bindings are defined via 'child-binding:' are picked up as bus nodes,
instead of a parent bus node of the same type.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add dmamux1 dts bindings for stm32h7
series. Note that there is no dedicated
clock to enable for dmamux1 so we set the
clock of dma1. This is the way linux handle
this.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
Fix the clocks bindings of dma1 and dma2
for stm32h7 series. This is wrong probably
due to copy and paste.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
In the change to DTS driven clock divider values wrong values
were used in the dts file.
Fixes: #33559
Signed-off-by: David Leach <david.leach@nxp.com>
The AN547 is a Soft Macro Model implementation of the SSE-300 subsystem
with Ethos-U55 and Cortex-M55 components targeting the MPS3 board.
The SoC support is based on the AN521 MPS2+ support that already exists
in Zephyr.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add initial support for the Cortex-M55 Core which is an implementation
of the Armv8.1-M mainline architecture and includes support for the
M‑profile Vector Extension (MVE).
The support is based on the Cortex-M33 support that already exists in
Zephyr.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
UARTs in Nordic devices only support a specified list of baud rates.
Choosing a different baud rate without this patch will cause a runtime
error, whereas with the constraint, this mistake is already found in
dts construction with a useful error message.
Signed-off-by: Peter Niebert <peter.niebert@univ-amu.fr>
This patch includes initial support for FT800 display driver.
It includes basic features. It can be easily extended with more
FT800 display list and co-processor features.
Signed-off-by: Hubert Miś <hubert.mis@gmail.com>
Add support to control DE/nRE RS-485 transceiver signals
over GPIO pins. Useful if the UART controller does not
support RS-485 mode.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add MODBUS RTU (over serial line) subsystem.
MODBUS RTU implementation supports booth server and
client roles. Some components of the implementation are based
on the uC/Modbus stack, which was published under Apache license,
(https://github.com/SiliconLabs/uC-Modbus
fdd1218a28e313c1212fed5ed42e5c65d3056a2c).
Resolves: #2854
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
In NPCX chips, System Configuration module can configure not only
pinctrl but also misc. functionality such as glue and flash write
protection. This change moves the scfg driver from the pinctrl folder
to soc/arm/nuvoton_npcx/common and renames it to avoid confusion.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Adds support for the Texas Instruments FDC2X1X Capacitance-to-Digital
Converter for Proximity and Level Sensing Applications.
Signed-off-by: Igor Knippenberg <igor.knippenberg@gmail.com>
Restructures dts files(value line definitions are no longer included by
others), and adds additional devices(g05x and g0bx).
All newly added timer pwm prescalers are set to 0.
lpuart1 is moved from stm32g0.dtsi to stm32g031.dtsi, as it is not
available on stm32g0x0 soc.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
"interrupt-names: combined" propterty is only used for stm32 i2c driver,
remove all other existing occurences for stm32g0(adc, lpuart, usart).
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add optional maximum-speed parameter to USB nodes. This affects all
defined stm32l4xx, except stm32l4rx and stm32l4sx
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
This parameter is defined for stm32f405 which and is included into
stm32f469. The include order is as follows:
st/f4/stm32f4.dtsi
st/f4/stm32f401.dtsi
st/f4/stm32f405.dtsi <-- ram_size defined here
st/f4/stm32f407.dtsi
st/f4/stm32f427.dtsi
st/f4/stm32f429.dtsi
st/f4/stm32f469.dtsi
Refer to Application Note AN4879 from ST to view ram size for each MCU.
Signed-off-by: Guðni Már Gilbert <gudni.m.g@gmail.com>
Introduce PSoC-6 pinctrl infraestructure and definitions. This add
files to handle devicetree entries and following modifications:
- add pinctrl bindings
- update gpio bindings with pin-cells
- add pinctrl node and move gpio nodes inside
- declare pinctrl for current uart entries
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Added file with common properties for cortex-m cores.
Added optional swo-ref-frequency property.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add GPIO definitions to QuickLogic EOS S3 devicetree.
Co-authored-by: Jan Kowalewski <jkowalewski@antmicro.com>
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
In some stm32 series systick was disabled in order to
allow alternate use of lptim timer as kernel low power ticker.
Doing this, dts based definition of CORTEX_M_SYSTICK Kconfig symbol
is disabled and CORTEX_M_SYSTICK was redefined with 'default y'
in stm32 soc files which makes things more complex to handle to
alternate with LPTIM activation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To keep the generic DMA device name as defined
in the dma framework config, renamed paxdma device
label to "DMA_1".
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Use kinetis SIM clock divider options set in device tree
instead of hardcoded values.
The kl25z device tree did not previously define a MCG node.
This has now been added with the general "nxp,kinetis-mcg"
binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
The kv5x device tree originally used the undefined
"nxp,kv58-mcg" binding for the MCG node. This has been
replaced by the general "nxp,kinetis-mcg" binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
Both the kw40z and kw41z device tree originally used an
undefined "nxp,kw41z-mcg" binding for the MCG node.
This has been replaced with the general "nxp,kinetis-mcg"
binding instead.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
