boards: arm: mimxrt595_evk: Plumbs RT595 USDHC
- Adds the pin controls and ushdc settings in device tree - Attaches clock to USDHC in soc.c - Adds binding for mmc Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
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4 changed files with 76 additions and 0 deletions
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@ -149,4 +149,43 @@
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nxp,analog-mode;
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};
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};
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pinmux_usdhc: pinmux_usdhc {
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group0 {
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pinmux = <SD0_CMD_PIO1_31>,
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<USDHC0_USDHC_DATA0_PIO2_0>,
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<USDHC0_USDHC_DATA1_PIO2_1>,
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<USDHC0_USDHC_DATA2_PIO2_2>,
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<USDHC0_USDHC_DATA3_PIO2_3>,
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<USDHC0_USDHC_DATA4_PIO2_5>,
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<USDHC0_USDHC_DATA5_PIO2_6>,
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<USDHC0_USDHC_DATA6_PIO2_7>,
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<USDHC0_USDHC_DATA7_PIO2_8>,
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<SD0_CARD_DET_N_PIO2_9>;
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bias-pull-up;
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input-enable;
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slew-rate = "normal";
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drive-strength = "normal";
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};
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group1 {
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pinmux = <SD0_CLK_PIO1_30>;
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bias-pull-down;
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input-enable;
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slew-rate = "normal";
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drive-strength = "normal";
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};
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group2 {
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pinmux = <GPIO_PIO210_PIO2_10>;
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bias-pull-down;
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slew-rate = "normal";
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drive-strength = "normal";
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};
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group3 {
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pinmux = <SD0_DS_PIO2_4>;
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bias-pull-down;
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input-enable;
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slew-rate = "slow";
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drive-strength = "normal";
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};
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};
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};
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@ -24,6 +24,7 @@
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watchdog0 = &wwdt0;
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magn0 = &fxos8700;
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accel0 = &fxos8700;
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sdhc0 = &usdhc1;
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};
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chosen {
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@ -319,6 +320,18 @@ zephyr_udc0: &usbhs {
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status = "okay";
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};
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&usdhc1 {
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status = "okay";
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pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
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cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
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mmc {
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compatible = "zephyr,mmc-disk";
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status = "okay";
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};
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pinctrl-0 = <&pinmux_usdhc>;
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pinctrl-names = "default";
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};
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&wwdt0 {
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status = "okay";
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};
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9
dts/bindings/sd/zephyr,mmc-disk.yaml
Normal file
9
dts/bindings/sd/zephyr,mmc-disk.yaml
Normal file
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@ -0,0 +1,9 @@
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description: |
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Zephyr MMC disk node. A binding with this compatible present within an SD
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host controller device node indicates that an MMC chip is attached to that
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SD bus. This binding will enable that to be used with the disk driver
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API and any subsystems that utilize it.
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compatible: "zephyr,mmc-disk"
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include: [sd-device.yaml]
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@ -289,6 +289,21 @@ static void clock_init(void)
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/* Switch CLKOUT to FRO_DIV2 */
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CLOCK_AttachClk(kFRO_DIV2_to_CLKOUT);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC
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/* Make sure USDHC ram buffer has been power up*/
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POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM);
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POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM);
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POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
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POWER_ApplyPD();
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/* usdhc depend on 32K clock also */
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CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK);
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CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK);
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CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1);
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CLOCK_EnableClock(kCLOCK_Sdio0);
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RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn);
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#endif
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DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
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/* Set up dividers. */
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