drivers: wdt: esp32: code refactor to use hal calls
Update WDT driver to use hal calls, which brings proper unification among socs. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is contained in:
Sylvio Alves
Anas Nashif
parent
8671fa683e
commit
6ba6894580
5 changed files with 72 additions and 133 deletions
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@ -109,3 +109,7 @@
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};
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};
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};
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&wdt0 {
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status = "okay";
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};
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@ -9,9 +9,12 @@
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include <soc/rtc_cntl_reg.h>
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#include <soc/timer_group_reg.h>
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#include <hal/mwdt_ll.h>
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#include <hal/wdt_hal.h>
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#include <string.h>
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#include <drivers/watchdog.h>
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#include <drivers/clock_control.h>
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#ifndef CONFIG_SOC_ESP32C3
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#include <drivers/interrupt_controller/intc_esp32.h>
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#else
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@ -19,174 +22,90 @@
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#endif
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#include <device.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(wdt_esp32, CONFIG_WDT_LOG_LEVEL);
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#ifdef CONFIG_SOC_ESP32C3
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#define ISR_HANDLER isr_handler_t
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#else
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#define ISR_HANDLER intr_handler_t
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#endif
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/* FIXME: This struct shall be removed from here, when esp32 timer driver got
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* implemented.
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* That's why the type name starts with `timer` not `wdt`
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*/
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struct timer_esp32_irq_regs_t {
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uint32_t *timer_int_ena;
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uint32_t *timer_int_clr;
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};
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struct wdt_esp32_regs_t {
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uint32_t config0;
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uint32_t config1;
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uint32_t config2;
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uint32_t config3;
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uint32_t config4;
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uint32_t config5;
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uint32_t feed;
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uint32_t wprotect;
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};
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enum wdt_mode {
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WDT_MODE_RESET = 0,
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WDT_MODE_INTERRUPT_RESET
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};
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#define MWDT_TICK_PRESCALER 40000
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#define MWDT_TICKS_PER_US 500
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struct wdt_esp32_data {
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wdt_hal_context_t hal;
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uint32_t timeout;
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enum wdt_mode mode;
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wdt_stage_action_t mode;
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wdt_callback_t callback;
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int irq_line;
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};
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struct wdt_esp32_config {
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wdt_inst_t wdt_inst;
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const struct device *clock_dev;
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const clock_control_subsys_t clock_subsys;
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void (*connect_irq)(void);
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const struct wdt_esp32_regs_t *base;
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const struct timer_esp32_irq_regs_t irq_regs;
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int irq_source;
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};
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#define DEV_BASE(dev) \
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((volatile struct wdt_esp32_regs_t *) \
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((const struct wdt_esp32_config *const)(dev)->config)->base)
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/* ESP32 ignores writes to any register if WDTWPROTECT doesn't contain the
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* magic value of TIMG_WDT_WKEY_VALUE. The datasheet recommends unsealing,
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* making modifications, and sealing for every watchdog modification.
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*/
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static inline void wdt_esp32_seal(const struct device *dev)
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{
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DEV_BASE(dev)->wprotect = 0U;
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struct wdt_esp32_data *data = dev->data;
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wdt_hal_write_protect_enable(&data->hal);
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}
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static inline void wdt_esp32_unseal(const struct device *dev)
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{
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DEV_BASE(dev)->wprotect = TIMG_WDT_WKEY_VALUE;
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struct wdt_esp32_data *data = dev->data;
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wdt_hal_write_protect_disable(&data->hal);
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}
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static void wdt_esp32_enable(const struct device *dev)
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{
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struct wdt_esp32_data *data = dev->data;
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wdt_esp32_unseal(dev);
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DEV_BASE(dev)->config0 |= BIT(TIMG_WDT_EN_S);
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wdt_hal_enable(&data->hal);
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wdt_esp32_seal(dev);
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}
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static int wdt_esp32_disable(const struct device *dev)
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{
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struct wdt_esp32_data *data = dev->data;
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wdt_esp32_unseal(dev);
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DEV_BASE(dev)->config0 &= ~BIT(TIMG_WDT_EN_S);
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wdt_hal_disable(&data->hal);
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wdt_esp32_seal(dev);
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return 0;
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}
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static void adjust_timeout(const struct device *dev, uint32_t timeout)
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{
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/* MWDT ticks every 12.5ns. Set the prescaler to 40000, so the
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* counter for each watchdog stage is decremented every 0.5ms.
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*/
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DEV_BASE(dev)->config1 = 40000U;
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DEV_BASE(dev)->config2 = timeout;
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DEV_BASE(dev)->config3 = timeout;
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}
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static void wdt_esp32_isr(void *arg);
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static int wdt_esp32_feed(const struct device *dev, int channel_id)
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{
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struct wdt_esp32_data *data = dev->data;
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wdt_esp32_unseal(dev);
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DEV_BASE(dev)->feed = 0xABAD1DEA; /* Writing any value to WDTFEED will reload it. */
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wdt_hal_feed(&data->hal);
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wdt_esp32_seal(dev);
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return 0;
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}
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static void set_interrupt_enabled(const struct device *dev, bool setting)
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{
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const struct wdt_esp32_config *config = dev->config;
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struct wdt_esp32_data *data = dev->data;
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*config->irq_regs.timer_int_clr |= TIMG_WDT_INT_CLR;
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if (setting) {
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*config->irq_regs.timer_int_ena |= TIMG_WDT_INT_ENA;
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irq_enable(data->irq_line);
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} else {
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*config->irq_regs.timer_int_ena &= ~TIMG_WDT_INT_ENA;
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irq_disable(data->irq_line);
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}
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}
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static int wdt_esp32_set_config(const struct device *dev, uint8_t options)
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{
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struct wdt_esp32_data *data = dev->data;
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uint32_t v = DEV_BASE(dev)->config0;
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if (!data) {
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return -EINVAL;
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}
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/* Stages 3 and 4 are not used: disable them. */
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v |= TIMG_WDT_STG_SEL_OFF << TIMG_WDT_STG2_S;
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v |= TIMG_WDT_STG_SEL_OFF << TIMG_WDT_STG3_S;
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/* Wait for 3.2us before booting again. */
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v |= 7 << TIMG_WDT_SYS_RESET_LENGTH_S;
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v |= 7 << TIMG_WDT_CPU_RESET_LENGTH_S;
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if (data->mode == WDT_MODE_RESET) {
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/* Warm reset on timeout */
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v |= TIMG_WDT_STG_SEL_RESET_SYSTEM << TIMG_WDT_STG0_S;
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v |= TIMG_WDT_STG_SEL_OFF << TIMG_WDT_STG1_S;
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/* Disable interrupts for this mode. */
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#ifndef CONFIG_SOC_ESP32C3
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v &= ~(TIMG_WDT_LEVEL_INT_EN | TIMG_WDT_EDGE_INT_EN);
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#else
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v &= ~(TIMG_WDT_INT_ENA);
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#endif
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} else if (data->mode == WDT_MODE_INTERRUPT_RESET) {
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/* Interrupt first, and warm reset if not reloaded */
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v |= TIMG_WDT_STG_SEL_INT << TIMG_WDT_STG0_S;
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v |= TIMG_WDT_STG_SEL_RESET_SYSTEM << TIMG_WDT_STG1_S;
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/* Use level-triggered interrupts. */
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#ifndef CONFIG_SOC_ESP32C3
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v |= TIMG_WDT_LEVEL_INT_EN;
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v &= ~TIMG_WDT_EDGE_INT_EN;
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#else
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v |= TIMG_WDT_INT_ENA;
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#endif
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} else {
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return -EINVAL;
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}
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wdt_esp32_unseal(dev);
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DEV_BASE(dev)->config0 = v;
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adjust_timeout(dev, data->timeout);
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set_interrupt_enabled(dev, data->mode == WDT_MODE_INTERRUPT_RESET);
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wdt_hal_config_stage(&data->hal, WDT_STAGE0, data->timeout, WDT_STAGE_ACTION_INT);
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wdt_hal_config_stage(&data->hal, WDT_STAGE1, data->timeout, data->mode);
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wdt_esp32_enable(dev);
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wdt_esp32_seal(dev);
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wdt_esp32_feed(dev, 0);
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return 0;
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@ -197,21 +116,35 @@ static int wdt_esp32_install_timeout(const struct device *dev,
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{
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struct wdt_esp32_data *data = dev->data;
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if (cfg->flags != WDT_FLAG_RESET_SOC) {
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return -ENOTSUP;
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}
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if (cfg->window.min != 0U || cfg->window.max == 0U) {
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return -EINVAL;
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}
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data->timeout = cfg->window.max;
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data->mode = (cfg->callback == NULL) ?
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WDT_MODE_RESET : WDT_MODE_INTERRUPT_RESET;
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data->callback = cfg->callback;
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/* Set mode of watchdog and callback */
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switch (cfg->flags) {
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case WDT_FLAG_RESET_SOC:
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data->mode = WDT_STAGE_ACTION_RESET_SYSTEM;
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LOG_DBG("Configuring reset SOC mode");
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break;
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case WDT_FLAG_RESET_CPU_CORE:
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data->mode = WDT_STAGE_ACTION_RESET_CPU;
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LOG_DBG("Configuring reset CPU mode");
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break;
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case WDT_FLAG_RESET_NONE:
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data->mode = WDT_STAGE_ACTION_OFF;
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LOG_DBG("Configuring non-reset mode");
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break;
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default:
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LOG_ERR("Unsupported watchdog config flag");
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return -EINVAL;
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}
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return 0;
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}
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@ -220,21 +153,19 @@ static int wdt_esp32_init(const struct device *dev)
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const struct wdt_esp32_config *const config = dev->config;
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struct wdt_esp32_data *data = dev->data;
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#ifdef CONFIG_WDT_DISABLE_AT_BOOT
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wdt_esp32_disable(dev);
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#endif
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clock_control_on(config->clock_dev, config->clock_subsys);
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/* For xtensa esp32 chips, this is a level 4 interrupt,
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* which is handled by _Level4Vector,
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* located in xtensa_vectors.S.
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*/
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data->irq_line = esp_intr_alloc(config->irq_source,
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wdt_hal_init(&data->hal, config->wdt_inst, MWDT_TICK_PRESCALER, true);
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esp_intr_alloc(config->irq_source,
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0,
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(ISR_HANDLER)wdt_esp32_isr,
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(void *)dev,
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NULL);
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#ifndef CONFIG_WDT_DISABLE_AT_BOOT
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wdt_esp32_enable(dev);
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#endif
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return 0;
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}
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@ -249,12 +180,10 @@ static const struct wdt_driver_api wdt_api = {
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#define ESP32_WDT_INIT(idx) \
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static struct wdt_esp32_data wdt##idx##_data; \
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static struct wdt_esp32_config wdt_esp32_config##idx = { \
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.base = (struct wdt_esp32_regs_t *) DT_INST_REG_ADDR(idx), \
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.irq_regs = { \
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.timer_int_ena = (uint32_t *)TIMG_INT_ENA_TIMERS_REG(idx), \
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.timer_int_clr = (uint32_t *)TIMG_INT_CLR_TIMERS_REG(idx), \
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}, \
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.wdt_inst = WDT_MWDT##idx, \
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.irq_source = DT_IRQN(DT_NODELABEL(wdt##idx)), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
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.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(idx, offset), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(idx, \
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@ -275,7 +204,7 @@ static void wdt_esp32_isr(void *arg)
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data->callback(dev, 0);
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}
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*config->irq_regs.timer_int_clr |= TIMG_WDT_INT_CLR;
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wdt_hal_handle_intr(&data->hal);
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}
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@ -176,6 +176,7 @@
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reg = <0x6001f048 0x20>;
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interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TIMG0_MODULE>;
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label = "WDT_0";
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status = "disabled";
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};
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@ -185,6 +186,7 @@
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reg = <0x60020048 0x20>;
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interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TIMG1_MODULE>;
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label = "WDT_1";
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status = "disabled";
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};
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@ -203,6 +203,7 @@
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reg = <0x3ff5f048 0x20>;
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interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TIMG0_MODULE>;
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label = "WDT_0";
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status = "okay";
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};
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@ -212,6 +213,7 @@
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reg = <0x3ff60048 0x20>;
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interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TIMG1_MODULE>;
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label = "WDT_1";
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status = "disabled";
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};
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@ -223,6 +223,7 @@
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reg = <0x3f41f048 0x20>;
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interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TIMG0_MODULE>;
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label = "WDT_0";
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status = "disabled";
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};
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@ -232,6 +233,7 @@
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reg = <0x3f42f048 0x20>;
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interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TIMG1_MODULE>;
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label = "WDT_1";
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status = "disabled";
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};
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