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ITE drivers/pinctrl/it8xxx2: extend pinctrl driver for kscan pins

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Extend pinctrl driver for kscan pins.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit is contained in:
Ruibin Chang 2022-12-28 13:57:13 +08:00 • committed by Carles Cufí
commit 344c9c67f9
6 changed files with 424 additions and 98 deletions
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297
drivers/pinctrl/pinctrl_ite_it8xxx2.c
View file

@ -17,7 +17,7 @@ LOG_MODULE_REGISTER(pinctrl_ite_it8xxx2, LOG_LEVEL_ERR);
((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
#define GPIO_GROUP_MEMBERS 8
struct pinctrl_it8xxx2_config {
struct pinctrl_it8xxx2_gpio {
/* gpio port control register (byte mapping to pin) */
uint8_t *reg_gpcr;
/* function 3 general control register */
@ -34,13 +34,42 @@ struct pinctrl_it8xxx2_config {
uint8_t volt_sel_mask[GPIO_GROUP_MEMBERS];
};
struct pinctrl_it8xxx2_ksi_kso {
/*
* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register
* (bit mapping to pin)
*/
uint8_t *reg_gctrl;
/* KSI[7:0]/KSO[15:8]/KSO[7:0] port control register */
uint8_t *reg_ctrl;
/*
* KSO push-pull/open-drain bit of KSO[15:0] control register
* (this bit apply to all pins)
*/
int pp_od_mask;
/*
* KSI/KSO pullup bit of KSI[7:0]/KSO[15:0] control register
* (this bit apply to all pins)
*/
int pullup_mask;
};
struct pinctrl_it8xxx2_config {
bool gpio_group;
union {
struct pinctrl_it8xxx2_gpio gpio;
struct pinctrl_it8xxx2_ksi_kso ksi_kso;
};
};
static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins)
{
const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);
uint32_t pincfg = pins->pincfg;
uint8_t pin = pins->pin;
volatile uint8_t *reg_gpcr = (uint8_t *)pinctrl_config->reg_gpcr + pin;
volatile uint8_t *reg_volt_sel = (uint8_t *)(pinctrl_config->volt_sel[pin]);
volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;
volatile uint8_t *reg_volt_sel = (uint8_t *)(gpio->volt_sel[pin]);
/* Setting pull-up or pull-down. */
switch (IT8XXX2_DT_PINCFG_PUPDR(pincfg)) {
@ -66,14 +95,14 @@ static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins)
switch (IT8XXX2_DT_PINCFG_VOLTAGE(pincfg)) {
case IT8XXX2_VOLTAGE_3V3:
/* Input voltage selection 3.3V. */
*reg_volt_sel &= ~pinctrl_config->volt_sel_mask[pin];
*reg_volt_sel &= ~gpio->volt_sel_mask[pin];
break;
case IT8XXX2_VOLTAGE_1V8:
__ASSERT(!(IT8XXX2_DT_PINCFG_PUPDR(pincfg)
== IT8XXX2_PULL_UP),
"Don't enable internal pullup if 1.8V voltage is used");
/* Input voltage selection 1.8V. */
*reg_volt_sel |= pinctrl_config->volt_sel_mask[pin];
*reg_volt_sel |= gpio->volt_sel_mask[pin];
break;
default:
LOG_ERR("The voltage selection is not supported");
@ -89,79 +118,164 @@ static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins)
return 0;
}
static int pinctrl_gpio_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
{
const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);
uint8_t pin = pins->pin;
volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;
volatile uint8_t *reg_func3_gcr = (uint8_t *)(gpio->func3_gcr[pin]);
volatile uint8_t *reg_func4_gcr = (uint8_t *)(gpio->func4_gcr[pin]);
/* Handle PIN configuration. */
if (pinctrl_it8xxx2_set(pins)) {
LOG_ERR("Pin configuration is invalid.");
return -EINVAL;
}
/*
* If pincfg is input, we don't need to handle
* alternate function.
*/
if (IT8XXX2_DT_PINCFG_INPUT(pins->pincfg)) {
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
~GPCR_PORT_PIN_MODE_OUTPUT;
return 0;
}
/*
* Handle alternate function.
*/
/* Common settings for alternate function. */
*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
GPCR_PORT_PIN_MODE_OUTPUT);
switch (pins->alt_func) {
case IT8XXX2_ALT_FUNC_1:
/* Func1: Alternate function has been set above. */
break;
case IT8XXX2_ALT_FUNC_2:
/* Func2: WUI function: turn the pin into an input */
*reg_gpcr |= GPCR_PORT_PIN_MODE_INPUT;
break;
case IT8XXX2_ALT_FUNC_3:
/*
* Func3: In addition to the alternate setting above,
* Func3 also need to set the general control.
*/
*reg_func3_gcr |= gpio->func3_en_mask[pin];
break;
case IT8XXX2_ALT_FUNC_4:
/*
* Func4: In addition to the alternate setting above,
* Func4 also need to set the general control.
*/
*reg_func4_gcr |= gpio->func4_en_mask[pin];
break;
case IT8XXX2_ALT_DEFAULT:
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
~GPCR_PORT_PIN_MODE_OUTPUT;
*reg_func3_gcr &= ~gpio->func3_en_mask[pin];
*reg_func4_gcr &= ~gpio->func4_en_mask[pin];
break;
default:
LOG_ERR("This function is not supported.");
return -EINVAL;
}
return 0;
}
static int pinctrl_kscan_it8xxx2_set(const pinctrl_soc_pin_t *pins)
{
const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);
volatile uint8_t *reg_ctrl = ksi_kso->reg_ctrl;
uint8_t pullup_mask = ksi_kso->pullup_mask;
uint8_t pp_od_mask = ksi_kso->pp_od_mask;
uint32_t pincfg = pins->pincfg;
/*
* Enable or disable internal pull-up (this bit apply to all pins):
* If KSI[7:0]/KSO[15:0] is in KBS mode , setting 1 enables the internal
* pull-up (KSO[17:16] setting internal pull-up by GPIO port GPCR register).
* If KSI[7:0]/KSO[15:0] is in GPIO mode, then this bit is always disabled.
*/
switch (IT8XXX2_DT_PINCFG_PULLUP(pincfg)) {
case IT8XXX2_PULL_PIN_DEFAULT:
/* Disable internal pulll-up */
*reg_ctrl &= ~pullup_mask;
break;
case IT8XXX2_PULL_UP:
*reg_ctrl |= pullup_mask;
break;
default:
LOG_ERR("This pull level is not supported.");
return -EINVAL;
}
/*
* Set push-pull or open-drain mode (this bit apply to all pins):
* KSI[7:0] doesn't support push-pull and open-drain settings in kbs mode.
* If KSO[17:0] is in KBS mode, setting 1 selects open-drain mode,
* setting 0 selects push-pull mode.
* If KSO[15:0] is in GPIO mode, then this bit is always disabled.
*/
if (pp_od_mask != NO_FUNC) {
switch (IT8XXX2_DT_PINCFG_PP_OD(pincfg)) {
case IT8XXX2_PUSH_PULL:
*reg_ctrl &= ~pp_od_mask;
break;
case IT8XXX2_OPEN_DRAIN:
*reg_ctrl |= pp_od_mask;
break;
default:
LOG_ERR("This pull mode is not supported.");
return -EINVAL;
}
}
return 0;
}
static int pinctrl_kscan_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
{
const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);
volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl;
uint8_t pin_mask = BIT(pins->pin);
/* Set a pin of KSI[7:0]/KSO[15:0] to pullup, push-pull/open-drain */
if (pinctrl_kscan_it8xxx2_set(pins)) {
return -EINVAL;
}
/* Set a pin of KSI[7:0]/KSO[15:0] to kbs mode */
*reg_gctrl &= ~pin_mask;
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
const struct pinctrl_it8xxx2_config *pinctrl_config;
volatile uint8_t *reg_gpcr;
volatile uint8_t *reg_func3_gcr;
volatile uint8_t *reg_func4_gcr;
uint8_t pin;
int status;
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_config = pins[i].pinctrls->config;
pin = pins[i].pin;
reg_gpcr = (uint8_t *)pinctrl_config->reg_gpcr + pin;
reg_func3_gcr = (uint8_t *)(pinctrl_config->func3_gcr[pin]);
reg_func4_gcr = (uint8_t *)(pinctrl_config->func4_gcr[pin]);
/* Handle PIN configuration. */
if (pinctrl_it8xxx2_set(&pins[i])) {
LOG_ERR("Pin configuration is invalid.");
return -EINVAL;
if (pinctrl_config->gpio_group) {
status = pinctrl_gpio_it8xxx2_configure_pins(&pins[i]);
} else {
status = pinctrl_kscan_it8xxx2_configure_pins(&pins[i]);
}
/*
* If pincfg is input, we don't need to handle
* alternate function.
*/
if (IT8XXX2_DT_PINCFG_INPUT(pins[i].pincfg)) {
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
~GPCR_PORT_PIN_MODE_OUTPUT;
continue;
if (status < 0) {
LOG_ERR("%s pin%d configuration is invalid.",
pins[i].pinctrls->name, pins[i].pin);
return status;
}
/*
* Handle alternate function.
*/
/* Common settings for alternate function. */
*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
GPCR_PORT_PIN_MODE_OUTPUT);
switch (pins[i].alt_func) {
case IT8XXX2_ALT_FUNC_1:
/* Func1: Alternate function has been set above. */
break;
case IT8XXX2_ALT_FUNC_2:
/* Func2: WUI function: turn the pin into an input */
*reg_gpcr |= GPCR_PORT_PIN_MODE_INPUT;
break;
case IT8XXX2_ALT_FUNC_3:
/*
* Func3: In addition to the alternate setting above,
* Func3 also need to set the general control.
*/
*reg_func3_gcr |= pinctrl_config->func3_en_mask[pin];
break;
case IT8XXX2_ALT_FUNC_4:
/*
* Func4: In addition to the alternate setting above,
* Func4 also need to set the general control.
*/
*reg_func4_gcr |= pinctrl_config->func4_en_mask[pin];
break;
case IT8XXX2_ALT_DEFAULT:
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
~GPCR_PORT_PIN_MODE_OUTPUT;
*reg_func3_gcr &= ~pinctrl_config->func3_en_mask[pin];
*reg_func4_gcr &= ~pinctrl_config->func4_en_mask[pin];
break;
default:
LOG_ERR("This function is not supported.");
return -EINVAL;
}
}
return 0;
@ -186,23 +300,38 @@ static int pinctrl_it8xxx2_init(const struct device *dev)
return 0;
}
#define PINCTRL_ITE_INIT(inst) \
static const struct pinctrl_it8xxx2_config pinctrl_it8xxx2_cfg_##inst = { \
.reg_gpcr = (uint8_t *)DT_INST_REG_ADDR(inst), \
.func3_gcr = DT_INST_PROP(inst, func3_gcr), \
.func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
.func4_gcr = DT_INST_PROP(inst, func4_gcr), \
.func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
.volt_sel = DT_INST_PROP(inst, volt_sel), \
.volt_sel_mask = DT_INST_PROP(inst, volt_sel_mask), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, &pinctrl_it8xxx2_init, \
NULL, \
NULL, \
&pinctrl_it8xxx2_cfg_##inst, \
PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
NULL);
#define INIT_UNION_CONFIG(inst) \
COND_CODE_1(DT_INST_PROP(inst, gpio_group), \
(.gpio = { \
.reg_gpcr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
.func3_gcr = DT_INST_PROP(inst, func3_gcr), \
.func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
.func4_gcr = DT_INST_PROP(inst, func4_gcr), \
.func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
.volt_sel = DT_INST_PROP(inst, volt_sel), \
.volt_sel_mask = DT_INST_PROP(inst, volt_sel_mask), \
}), \
(.ksi_kso = { \
.reg_gctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
.reg_ctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
.pp_od_mask = (uint8_t)DT_INST_PROP(inst, pp_od_mask), \
.pullup_mask = (uint8_t)DT_INST_PROP(inst, pullup_mask), \
}) \
)
#define PINCTRL_ITE_INIT(inst) \
static const struct pinctrl_it8xxx2_config pinctrl_it8xxx2_cfg_##inst = { \
.gpio_group = DT_INST_PROP(inst, gpio_group), \
{ \
INIT_UNION_CONFIG(inst) \
} \
}; \
\
DEVICE_DT_INST_DEFINE(inst, &pinctrl_it8xxx2_init, \
NULL, \
NULL, \
&pinctrl_it8xxx2_cfg_##inst, \
PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(PINCTRL_ITE_INIT)

28
dts/bindings/pinctrl/ite,it8xxx2-pinctrl-func.yaml
View file

@ -10,27 +10,43 @@ include: base.yaml
properties:
func3-gcr:
type: array
required: true
func3-en-mask:
type: array
required: true
func4-gcr:
type: array
required: true
func4-en-mask:
type: array
required: true
volt-sel:
type: array
required: true
volt-sel-mask:
type: array
required: true
pp-od-mask:
type: int
description: |
KSI[7:0] does not support push-pull and open-drain mode.
If KSO[17:0] is in KBS mode, setting 1 selects open-drain mode,
setting 0 selects push-pull mode.
If KSO[15:0] is in GPIO mode, then this bit is always disabled.
pullup-mask:
type: int
description: |
If KSI[7:0]/KSO[15:0] is in KBS mode , setting 1 enables the internal
pull-up (KSO[17:16] setting internal pull-up by GPIO port GPCR register).
If KSI[7:0]/KSO[15:0] is in GPIO mode, then this bit is always disabled.
gpio-group:
type: boolean
description: |
Default setting pin configure to alternate mode for all GPIO group pins
(include KSO[17:16]), otherwise setting pin configure to keyboard scan
mode for KSI[7:0] and KSO[15:0] pins.
pinmux-cells:
- pin

5
dts/bindings/pinctrl/ite,it8xxx2-pinctrl.yaml
View file

@ -75,6 +75,8 @@ child-binding:
- bias-pull-up
- bias-pull-down
- input-enable
- drive-push-pull
- drive-open-drain
properties:
pinmuxs:
@ -88,7 +90,8 @@ child-binding:
description: |
Pin input voltage selection 3.3V or 1.8V. All gpio pins support 3.3V.
This property only needs to be configured if the board specifies a
pin as 1.8V. So the default is 3.3V
pin as 1.8V. So the default is 3.3V.
kSI[7:0] and KSO[15:0] pins only support 3.3V.
default: "3v3"
enum:
- "3v3"

40
dts/riscv/ite/it81xx2.dtsi
View file

@ -74,6 +74,7 @@
volt-sel-mask = <0 0 0 0
0x1 0x02 0x20 0x40 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrlb: pinctrl@f01618 {
@ -92,6 +93,7 @@
volt-sel-mask = <0 0 0 0x02
0x01 0x80 0x40 0x10 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrlc: pinctrl@f01620 {
@ -110,6 +112,7 @@
volt-sel-mask = <0x80 0x20 0x10 0
0x04 0 0x08 0x08 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrld: pinctrl@f01628 {
@ -128,6 +131,7 @@
volt-sel-mask = <0x04 0x02 0x01 0x80
0x40 0x10 0x20 0x40 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrle: pinctrl@f01630 {
@ -146,6 +150,7 @@
volt-sel-mask = <0x20 0x40 0x80 0
0x04 0x08 0x10 0x08 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrlf: pinctrl@f01638 {
@ -164,6 +169,7 @@
volt-sel-mask = <0x10 0x20 0x04 0x02
0x01 0x80 0x40 0x20 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrlg: pinctrl@f01640 {
@ -182,6 +188,7 @@
volt-sel-mask = <0x04 0x10 0x08 0
0 0 0x08 0 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrlh: pinctrl@f01648 {
@ -200,6 +207,7 @@
volt-sel-mask = <0x04 0x02 0x01 0
0 0x80 0x01 0 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrli: pinctrl@f01650 {
@ -218,6 +226,7 @@
volt-sel-mask = <0x08 0x10 0x20 0x40
0x80 0x10 0x20 0x40 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrlj: pinctrl@f01658 {
@ -236,6 +245,7 @@
volt-sel-mask = <0x01 0x02 0x04 0x08
0x01 0x02 0x04 0x04 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrlk: pinctrl@f01690 {
@ -254,6 +264,7 @@
volt-sel-mask = <0x01 0x02 0x04 0x08
0x10 0x20 0x40 0x80 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrll: pinctrl@f01698 {
@ -272,6 +283,7 @@
volt-sel-mask = <0x01 0x02 0x04 0x08
0x10 0x20 0x40 0x80 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrlm: pinctrl@f016a0 {
@ -290,6 +302,34 @@
volt-sel-mask = <0x10 0x10 0x10 0x10
0x10 0x10 0x10 0 >;
#pinmux-cells = <2>;
gpio-group;
};
pinctrlksi: pinctrl@f01d06 {
compatible = "ite,it8xxx2-pinctrl-func";
reg = <0x00f01d06 1 /* KSIGCTRL */
0x00f01d05 1>; /* KSICTRL */
pp-od-mask = <NO_FUNC>;
pullup-mask = <BIT(2)>;
#pinmux-cells = <2>;
};
pinctrlksoh: pinctrl@f01d0a {
compatible = "ite,it8xxx2-pinctrl-func";
reg = <0x00f01d0a 1 /* KSOHGCTRL */
0x00f01d02 1>; /* KSOCTRL */
pp-od-mask = <BIT(0)>;
pullup-mask = <BIT(2)>;
#pinmux-cells = <2>;
};
pinctrlksol: pinctrl@f01d0d {
compatible = "ite,it8xxx2-pinctrl-func";
reg = <0x00f01d0d 1 /* KSOLGCTRL */
0x00f01d02 1>; /* KSOCTRL */
pp-od-mask = <BIT(0)>;
pullup-mask = <BIT(2)>;
#pinmux-cells = <2>;
};
};

112
dts/riscv/ite/it8xxx2-pinctrl-map.dtsi
View file

@ -90,6 +90,118 @@
};
/* Keyboard alternate function */
ksi0_default: ksi0_default {
pinmuxs = <&pinctrlksi 0 IT8XXX2_ALT_FUNC_1>;
bias-pull-up;
};
ksi1_default: ksi1_default {
pinmuxs = <&pinctrlksi 1 IT8XXX2_ALT_FUNC_1>;
bias-pull-up;
};
ksi2_default: ksi2_default {
pinmuxs = <&pinctrlksi 2 IT8XXX2_ALT_FUNC_1>;
bias-pull-up;
};
ksi3_default: ksi3_default {
pinmuxs = <&pinctrlksi 3 IT8XXX2_ALT_FUNC_1>;
bias-pull-up;
};
ksi4_default: ksi4_default {
pinmuxs = <&pinctrlksi 4 IT8XXX2_ALT_FUNC_1>;
bias-pull-up;
};
ksi5_default: ksi5_default {
pinmuxs = <&pinctrlksi 5 IT8XXX2_ALT_FUNC_1>;
bias-pull-up;
};
ksi6_default: ksi6_default {
pinmuxs = <&pinctrlksi 6 IT8XXX2_ALT_FUNC_1>;
bias-pull-up;
};
ksi7_default: ksi7_default {
pinmuxs = <&pinctrlksi 7 IT8XXX2_ALT_FUNC_1>;
bias-pull-up;
};
kso0_default: kso0_default {
pinmuxs = <&pinctrlksol 0 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso1_default: kso1_default {
pinmuxs = <&pinctrlksol 1 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso2_default: kso2_default {
pinmuxs = <&pinctrlksol 2 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso3_default: kso3_default {
pinmuxs = <&pinctrlksol 3 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso4_default: kso4_default {
pinmuxs = <&pinctrlksol 4 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso5_default: kso5_default {
pinmuxs = <&pinctrlksol 5 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso6_default: kso6_default {
pinmuxs = <&pinctrlksol 6 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso7_default: kso7_default {
pinmuxs = <&pinctrlksol 7 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso8_default: kso8_default {
pinmuxs = <&pinctrlksoh 0 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso9_default: kso9_default {
pinmuxs = <&pinctrlksoh 1 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso10_default: kso10_default {
pinmuxs = <&pinctrlksoh 2 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso11_default: kso11_default {
pinmuxs = <&pinctrlksoh 3 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso12_default: kso12_default {
pinmuxs = <&pinctrlksoh 4 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso13_default: kso13_default {
pinmuxs = <&pinctrlksoh 5 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso14_default: kso14_default {
pinmuxs = <&pinctrlksoh 6 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso15_default: kso15_default {
pinmuxs = <&pinctrlksoh 7 IT8XXX2_ALT_FUNC_1>;
drive-open-drain;
bias-pull-up;
};
kso16_gpc3_default: kso16_gpc3_default {
pinmuxs = <&pinctrlc 3 IT8XXX2_ALT_FUNC_1>;
bias-pull-up;

40
soc/riscv/riscv-ite/common/pinctrl_soc.h
View file

@ -17,7 +17,12 @@
struct pinctrl_soc_pin {
/* Pinmux control group */
const struct device *pinctrls;
/* Pin configuration (impedance, pullup/down, voltate selection, input). */
/*
* Pin configuration
* kSI[7:0] and KSO[15:0] pins only support pull-up, push-pull/open-drain.
* GPIO group pinctrl pins (include KSO[17:16]) support impedance,
* pull-up/down, voltage selection, input.
*/
uint32_t pincfg;
/* GPIO pin */
uint8_t pin;
@ -31,11 +36,12 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
* @brief PIN configuration bitfield.
*
* Pin configuration is coded with the following
* fields.
* Pin impedance config [ 0 ]
* Pin pull-up/down config [ 4 : 5 ]
* Pin voltage selection [ 8 ]
* Pin input enable config [ 12 ]
* bit fields.
* Pin impedance config [ 0 ]
* Pin pull-up/down config [ 4 : 5 ]
* Pin voltage selection [ 8 ]
* Pin input enable config [ 12 ]
* Pin push-pull/open-drain [ 16 ]
*/
#define IT8XXX2_HIGH_IMPEDANCE 0x1U
#define IT8XXX2_PULL_PIN_DEFAULT 0x0U
@ -44,6 +50,8 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
#define IT8XXX2_VOLTAGE_3V3 0x0U
#define IT8XXX2_VOLTAGE_1V8 0x1U
#define IT8XXX2_INPUT_ENABLE 0x1U
#define IT8XXX2_PUSH_PULL 0x0U
#define IT8XXX2_OPEN_DRAIN 0x1U
/* Pin tri-state mode. */
#define IT8XXX2_IMPEDANCE_SHIFT 0U
@ -51,12 +59,16 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
/* Pin pull-up or pull-down */
#define IT8XXX2_PUPDR_SHIFT 4U
#define IT8XXX2_PUPDR_MASK 0x3U
#define IT8XXX2_PULL_UP_MASK BIT_MASK(1)
/* Pin 3.3V or 1.8V */
#define IT8XXX2_VOLTAGE_SHIFT 8U
#define IT8XXX2_VOLTAGE_MASK 0x1U
/* Pin INPUT enable or disable */
#define IT8XXX2_INPUT_SHIFT 12U
#define IT8XXX2_INPUT_MASK 0x1U
/* Pin push-pull/open-drain mode */
#define IT8XXX2_PP_OD_SHIFT 16U
#define IT8XXX2_PP_OD_MASK BIT_MASK(1)
/**
* @brief Utility macro to obtain configuration of tri-state.
@ -82,6 +94,18 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
#define IT8XXX2_DT_PINCFG_INPUT(__mode) \
(((__mode) >> IT8XXX2_INPUT_SHIFT) & IT8XXX2_INPUT_MASK)
/**
* @brief Utility macro to obtain configuration of pull-up or not.
*/
#define IT8XXX2_DT_PINCFG_PULLUP(__mode) \
(((__mode) >> IT8XXX2_PUPDR_SHIFT) & IT8XXX2_PULL_UP_MASK)
/**
* @brief Utility macro to obtain configuration of push-pull/open-drain mode.
*/
#define IT8XXX2_DT_PINCFG_PP_OD(__mode) \
(((__mode) >> IT8XXX2_PP_OD_SHIFT) & IT8XXX2_PP_OD_MASK)
/**
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
*
@ -99,7 +123,9 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
((IT8XXX2_VOLTAGE_1V8 * DT_ENUM_IDX(node_id, gpio_voltage)) \
<< IT8XXX2_VOLTAGE_SHIFT) | \
((IT8XXX2_INPUT_ENABLE * DT_PROP(node_id, input_enable)) \
<< IT8XXX2_INPUT_SHIFT))
<< IT8XXX2_INPUT_SHIFT) | \
((IT8XXX2_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) \
<< IT8XXX2_PP_OD_SHIFT))
/**
* @brief Utility macro to initialize pinctrls of pinmuxs field in #pinctrl_pin_t.