ITE drivers/pinctrl/it8xxx2: extend pinctrl driver for kscan pins
Extend pinctrl driver for kscan pins. Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit is contained in:
parent
d7f482a022
commit
344c9c67f9
6 changed files with 424 additions and 98 deletions
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@ -17,7 +17,7 @@ LOG_MODULE_REGISTER(pinctrl_ite_it8xxx2, LOG_LEVEL_ERR);
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((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
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#define GPIO_GROUP_MEMBERS 8
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struct pinctrl_it8xxx2_config {
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struct pinctrl_it8xxx2_gpio {
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/* gpio port control register (byte mapping to pin) */
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uint8_t *reg_gpcr;
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/* function 3 general control register */
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@ -34,13 +34,42 @@ struct pinctrl_it8xxx2_config {
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uint8_t volt_sel_mask[GPIO_GROUP_MEMBERS];
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};
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struct pinctrl_it8xxx2_ksi_kso {
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/*
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* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register
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* (bit mapping to pin)
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*/
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uint8_t *reg_gctrl;
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/* KSI[7:0]/KSO[15:8]/KSO[7:0] port control register */
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uint8_t *reg_ctrl;
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/*
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* KSO push-pull/open-drain bit of KSO[15:0] control register
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* (this bit apply to all pins)
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*/
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int pp_od_mask;
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/*
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* KSI/KSO pullup bit of KSI[7:0]/KSO[15:0] control register
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* (this bit apply to all pins)
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*/
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int pullup_mask;
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};
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struct pinctrl_it8xxx2_config {
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bool gpio_group;
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union {
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struct pinctrl_it8xxx2_gpio gpio;
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struct pinctrl_it8xxx2_ksi_kso ksi_kso;
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};
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};
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static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins)
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{
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const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
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const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);
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uint32_t pincfg = pins->pincfg;
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uint8_t pin = pins->pin;
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volatile uint8_t *reg_gpcr = (uint8_t *)pinctrl_config->reg_gpcr + pin;
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volatile uint8_t *reg_volt_sel = (uint8_t *)(pinctrl_config->volt_sel[pin]);
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volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;
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volatile uint8_t *reg_volt_sel = (uint8_t *)(gpio->volt_sel[pin]);
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/* Setting pull-up or pull-down. */
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switch (IT8XXX2_DT_PINCFG_PUPDR(pincfg)) {
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@ -66,14 +95,14 @@ static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins)
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switch (IT8XXX2_DT_PINCFG_VOLTAGE(pincfg)) {
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case IT8XXX2_VOLTAGE_3V3:
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/* Input voltage selection 3.3V. */
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*reg_volt_sel &= ~pinctrl_config->volt_sel_mask[pin];
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*reg_volt_sel &= ~gpio->volt_sel_mask[pin];
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break;
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case IT8XXX2_VOLTAGE_1V8:
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__ASSERT(!(IT8XXX2_DT_PINCFG_PUPDR(pincfg)
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== IT8XXX2_PULL_UP),
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"Don't enable internal pullup if 1.8V voltage is used");
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/* Input voltage selection 1.8V. */
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*reg_volt_sel |= pinctrl_config->volt_sel_mask[pin];
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*reg_volt_sel |= gpio->volt_sel_mask[pin];
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break;
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default:
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LOG_ERR("The voltage selection is not supported");
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@ -89,79 +118,164 @@ static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins)
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return 0;
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}
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static int pinctrl_gpio_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
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{
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const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
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const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);
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uint8_t pin = pins->pin;
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volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;
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volatile uint8_t *reg_func3_gcr = (uint8_t *)(gpio->func3_gcr[pin]);
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volatile uint8_t *reg_func4_gcr = (uint8_t *)(gpio->func4_gcr[pin]);
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/* Handle PIN configuration. */
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if (pinctrl_it8xxx2_set(pins)) {
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LOG_ERR("Pin configuration is invalid.");
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return -EINVAL;
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}
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/*
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* If pincfg is input, we don't need to handle
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* alternate function.
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*/
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if (IT8XXX2_DT_PINCFG_INPUT(pins->pincfg)) {
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
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~GPCR_PORT_PIN_MODE_OUTPUT;
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return 0;
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}
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/*
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* Handle alternate function.
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*/
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/* Common settings for alternate function. */
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*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
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GPCR_PORT_PIN_MODE_OUTPUT);
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switch (pins->alt_func) {
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case IT8XXX2_ALT_FUNC_1:
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/* Func1: Alternate function has been set above. */
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break;
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case IT8XXX2_ALT_FUNC_2:
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/* Func2: WUI function: turn the pin into an input */
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*reg_gpcr |= GPCR_PORT_PIN_MODE_INPUT;
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break;
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case IT8XXX2_ALT_FUNC_3:
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/*
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* Func3: In addition to the alternate setting above,
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* Func3 also need to set the general control.
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*/
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*reg_func3_gcr |= gpio->func3_en_mask[pin];
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break;
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case IT8XXX2_ALT_FUNC_4:
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/*
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* Func4: In addition to the alternate setting above,
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* Func4 also need to set the general control.
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*/
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*reg_func4_gcr |= gpio->func4_en_mask[pin];
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break;
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case IT8XXX2_ALT_DEFAULT:
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
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~GPCR_PORT_PIN_MODE_OUTPUT;
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*reg_func3_gcr &= ~gpio->func3_en_mask[pin];
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*reg_func4_gcr &= ~gpio->func4_en_mask[pin];
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break;
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default:
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LOG_ERR("This function is not supported.");
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return -EINVAL;
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}
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return 0;
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}
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static int pinctrl_kscan_it8xxx2_set(const pinctrl_soc_pin_t *pins)
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{
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const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
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const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);
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volatile uint8_t *reg_ctrl = ksi_kso->reg_ctrl;
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uint8_t pullup_mask = ksi_kso->pullup_mask;
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uint8_t pp_od_mask = ksi_kso->pp_od_mask;
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uint32_t pincfg = pins->pincfg;
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/*
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* Enable or disable internal pull-up (this bit apply to all pins):
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* If KSI[7:0]/KSO[15:0] is in KBS mode , setting 1 enables the internal
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* pull-up (KSO[17:16] setting internal pull-up by GPIO port GPCR register).
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* If KSI[7:0]/KSO[15:0] is in GPIO mode, then this bit is always disabled.
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*/
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switch (IT8XXX2_DT_PINCFG_PULLUP(pincfg)) {
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case IT8XXX2_PULL_PIN_DEFAULT:
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/* Disable internal pulll-up */
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*reg_ctrl &= ~pullup_mask;
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break;
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case IT8XXX2_PULL_UP:
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*reg_ctrl |= pullup_mask;
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break;
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default:
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LOG_ERR("This pull level is not supported.");
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return -EINVAL;
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}
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/*
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* Set push-pull or open-drain mode (this bit apply to all pins):
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* KSI[7:0] doesn't support push-pull and open-drain settings in kbs mode.
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* If KSO[17:0] is in KBS mode, setting 1 selects open-drain mode,
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* setting 0 selects push-pull mode.
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* If KSO[15:0] is in GPIO mode, then this bit is always disabled.
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*/
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if (pp_od_mask != NO_FUNC) {
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switch (IT8XXX2_DT_PINCFG_PP_OD(pincfg)) {
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case IT8XXX2_PUSH_PULL:
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*reg_ctrl &= ~pp_od_mask;
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break;
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case IT8XXX2_OPEN_DRAIN:
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*reg_ctrl |= pp_od_mask;
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break;
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default:
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LOG_ERR("This pull mode is not supported.");
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return -EINVAL;
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}
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}
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return 0;
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}
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static int pinctrl_kscan_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
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{
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const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
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const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);
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volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl;
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uint8_t pin_mask = BIT(pins->pin);
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/* Set a pin of KSI[7:0]/KSO[15:0] to pullup, push-pull/open-drain */
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if (pinctrl_kscan_it8xxx2_set(pins)) {
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return -EINVAL;
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}
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/* Set a pin of KSI[7:0]/KSO[15:0] to kbs mode */
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*reg_gctrl &= ~pin_mask;
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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ARG_UNUSED(reg);
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const struct pinctrl_it8xxx2_config *pinctrl_config;
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volatile uint8_t *reg_gpcr;
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volatile uint8_t *reg_func3_gcr;
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volatile uint8_t *reg_func4_gcr;
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uint8_t pin;
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int status;
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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pinctrl_config = pins[i].pinctrls->config;
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pin = pins[i].pin;
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reg_gpcr = (uint8_t *)pinctrl_config->reg_gpcr + pin;
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reg_func3_gcr = (uint8_t *)(pinctrl_config->func3_gcr[pin]);
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reg_func4_gcr = (uint8_t *)(pinctrl_config->func4_gcr[pin]);
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/* Handle PIN configuration. */
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if (pinctrl_it8xxx2_set(&pins[i])) {
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LOG_ERR("Pin configuration is invalid.");
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return -EINVAL;
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if (pinctrl_config->gpio_group) {
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status = pinctrl_gpio_it8xxx2_configure_pins(&pins[i]);
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} else {
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status = pinctrl_kscan_it8xxx2_configure_pins(&pins[i]);
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}
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/*
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* If pincfg is input, we don't need to handle
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* alternate function.
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*/
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if (IT8XXX2_DT_PINCFG_INPUT(pins[i].pincfg)) {
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
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~GPCR_PORT_PIN_MODE_OUTPUT;
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continue;
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if (status < 0) {
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LOG_ERR("%s pin%d configuration is invalid.",
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pins[i].pinctrls->name, pins[i].pin);
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return status;
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}
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/*
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* Handle alternate function.
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*/
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/* Common settings for alternate function. */
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*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
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GPCR_PORT_PIN_MODE_OUTPUT);
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switch (pins[i].alt_func) {
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case IT8XXX2_ALT_FUNC_1:
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/* Func1: Alternate function has been set above. */
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break;
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case IT8XXX2_ALT_FUNC_2:
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/* Func2: WUI function: turn the pin into an input */
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*reg_gpcr |= GPCR_PORT_PIN_MODE_INPUT;
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break;
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case IT8XXX2_ALT_FUNC_3:
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/*
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* Func3: In addition to the alternate setting above,
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* Func3 also need to set the general control.
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*/
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*reg_func3_gcr |= pinctrl_config->func3_en_mask[pin];
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break;
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case IT8XXX2_ALT_FUNC_4:
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/*
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* Func4: In addition to the alternate setting above,
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* Func4 also need to set the general control.
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*/
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*reg_func4_gcr |= pinctrl_config->func4_en_mask[pin];
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break;
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case IT8XXX2_ALT_DEFAULT:
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
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~GPCR_PORT_PIN_MODE_OUTPUT;
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*reg_func3_gcr &= ~pinctrl_config->func3_en_mask[pin];
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*reg_func4_gcr &= ~pinctrl_config->func4_en_mask[pin];
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break;
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default:
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LOG_ERR("This function is not supported.");
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return -EINVAL;
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}
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}
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return 0;
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@ -186,23 +300,38 @@ static int pinctrl_it8xxx2_init(const struct device *dev)
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return 0;
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}
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#define PINCTRL_ITE_INIT(inst) \
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static const struct pinctrl_it8xxx2_config pinctrl_it8xxx2_cfg_##inst = { \
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.reg_gpcr = (uint8_t *)DT_INST_REG_ADDR(inst), \
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.func3_gcr = DT_INST_PROP(inst, func3_gcr), \
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.func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
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.func4_gcr = DT_INST_PROP(inst, func4_gcr), \
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.func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
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.volt_sel = DT_INST_PROP(inst, volt_sel), \
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.volt_sel_mask = DT_INST_PROP(inst, volt_sel_mask), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, &pinctrl_it8xxx2_init, \
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NULL, \
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NULL, \
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&pinctrl_it8xxx2_cfg_##inst, \
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PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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NULL);
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#define INIT_UNION_CONFIG(inst) \
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COND_CODE_1(DT_INST_PROP(inst, gpio_group), \
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(.gpio = { \
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.reg_gpcr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
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.func3_gcr = DT_INST_PROP(inst, func3_gcr), \
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.func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
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.func4_gcr = DT_INST_PROP(inst, func4_gcr), \
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.func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
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.volt_sel = DT_INST_PROP(inst, volt_sel), \
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.volt_sel_mask = DT_INST_PROP(inst, volt_sel_mask), \
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}), \
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(.ksi_kso = { \
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.reg_gctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
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.reg_ctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
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.pp_od_mask = (uint8_t)DT_INST_PROP(inst, pp_od_mask), \
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.pullup_mask = (uint8_t)DT_INST_PROP(inst, pullup_mask), \
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}) \
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)
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#define PINCTRL_ITE_INIT(inst) \
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static const struct pinctrl_it8xxx2_config pinctrl_it8xxx2_cfg_##inst = { \
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.gpio_group = DT_INST_PROP(inst, gpio_group), \
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{ \
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INIT_UNION_CONFIG(inst) \
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} \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, &pinctrl_it8xxx2_init, \
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NULL, \
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NULL, \
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&pinctrl_it8xxx2_cfg_##inst, \
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PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(PINCTRL_ITE_INIT)
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@ -10,27 +10,43 @@ include: base.yaml
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properties:
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func3-gcr:
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type: array
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required: true
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func3-en-mask:
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type: array
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required: true
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func4-gcr:
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type: array
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required: true
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func4-en-mask:
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type: array
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required: true
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volt-sel:
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type: array
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required: true
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volt-sel-mask:
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type: array
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required: true
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pp-od-mask:
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type: int
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description: |
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KSI[7:0] does not support push-pull and open-drain mode.
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If KSO[17:0] is in KBS mode, setting 1 selects open-drain mode,
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setting 0 selects push-pull mode.
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If KSO[15:0] is in GPIO mode, then this bit is always disabled.
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pullup-mask:
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type: int
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description: |
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If KSI[7:0]/KSO[15:0] is in KBS mode , setting 1 enables the internal
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pull-up (KSO[17:16] setting internal pull-up by GPIO port GPCR register).
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If KSI[7:0]/KSO[15:0] is in GPIO mode, then this bit is always disabled.
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gpio-group:
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type: boolean
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description: |
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Default setting pin configure to alternate mode for all GPIO group pins
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(include KSO[17:16]), otherwise setting pin configure to keyboard scan
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mode for KSI[7:0] and KSO[15:0] pins.
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pinmux-cells:
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- pin
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@ -75,6 +75,8 @@ child-binding:
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- bias-pull-up
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- bias-pull-down
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- input-enable
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- drive-push-pull
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- drive-open-drain
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properties:
|
||||
pinmuxs:
|
||||
|
@ -88,7 +90,8 @@ child-binding:
|
|||
description: |
|
||||
Pin input voltage selection 3.3V or 1.8V. All gpio pins support 3.3V.
|
||||
This property only needs to be configured if the board specifies a
|
||||
pin as 1.8V. So the default is 3.3V
|
||||
pin as 1.8V. So the default is 3.3V.
|
||||
kSI[7:0] and KSO[15:0] pins only support 3.3V.
|
||||
default: "3v3"
|
||||
enum:
|
||||
- "3v3"
|
||||
|
|
|
@ -74,6 +74,7 @@
|
|||
volt-sel-mask = <0 0 0 0
|
||||
0x1 0x02 0x20 0x40 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrlb: pinctrl@f01618 {
|
||||
|
@ -92,6 +93,7 @@
|
|||
volt-sel-mask = <0 0 0 0x02
|
||||
0x01 0x80 0x40 0x10 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrlc: pinctrl@f01620 {
|
||||
|
@ -110,6 +112,7 @@
|
|||
volt-sel-mask = <0x80 0x20 0x10 0
|
||||
0x04 0 0x08 0x08 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrld: pinctrl@f01628 {
|
||||
|
@ -128,6 +131,7 @@
|
|||
volt-sel-mask = <0x04 0x02 0x01 0x80
|
||||
0x40 0x10 0x20 0x40 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrle: pinctrl@f01630 {
|
||||
|
@ -146,6 +150,7 @@
|
|||
volt-sel-mask = <0x20 0x40 0x80 0
|
||||
0x04 0x08 0x10 0x08 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrlf: pinctrl@f01638 {
|
||||
|
@ -164,6 +169,7 @@
|
|||
volt-sel-mask = <0x10 0x20 0x04 0x02
|
||||
0x01 0x80 0x40 0x20 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrlg: pinctrl@f01640 {
|
||||
|
@ -182,6 +188,7 @@
|
|||
volt-sel-mask = <0x04 0x10 0x08 0
|
||||
0 0 0x08 0 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrlh: pinctrl@f01648 {
|
||||
|
@ -200,6 +207,7 @@
|
|||
volt-sel-mask = <0x04 0x02 0x01 0
|
||||
0 0x80 0x01 0 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrli: pinctrl@f01650 {
|
||||
|
@ -218,6 +226,7 @@
|
|||
volt-sel-mask = <0x08 0x10 0x20 0x40
|
||||
0x80 0x10 0x20 0x40 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrlj: pinctrl@f01658 {
|
||||
|
@ -236,6 +245,7 @@
|
|||
volt-sel-mask = <0x01 0x02 0x04 0x08
|
||||
0x01 0x02 0x04 0x04 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrlk: pinctrl@f01690 {
|
||||
|
@ -254,6 +264,7 @@
|
|||
volt-sel-mask = <0x01 0x02 0x04 0x08
|
||||
0x10 0x20 0x40 0x80 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrll: pinctrl@f01698 {
|
||||
|
@ -272,6 +283,7 @@
|
|||
volt-sel-mask = <0x01 0x02 0x04 0x08
|
||||
0x10 0x20 0x40 0x80 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrlm: pinctrl@f016a0 {
|
||||
|
@ -290,6 +302,34 @@
|
|||
volt-sel-mask = <0x10 0x10 0x10 0x10
|
||||
0x10 0x10 0x10 0 >;
|
||||
#pinmux-cells = <2>;
|
||||
gpio-group;
|
||||
};
|
||||
|
||||
pinctrlksi: pinctrl@f01d06 {
|
||||
compatible = "ite,it8xxx2-pinctrl-func";
|
||||
reg = <0x00f01d06 1 /* KSIGCTRL */
|
||||
0x00f01d05 1>; /* KSICTRL */
|
||||
pp-od-mask = <NO_FUNC>;
|
||||
pullup-mask = <BIT(2)>;
|
||||
#pinmux-cells = <2>;
|
||||
};
|
||||
|
||||
pinctrlksoh: pinctrl@f01d0a {
|
||||
compatible = "ite,it8xxx2-pinctrl-func";
|
||||
reg = <0x00f01d0a 1 /* KSOHGCTRL */
|
||||
0x00f01d02 1>; /* KSOCTRL */
|
||||
pp-od-mask = <BIT(0)>;
|
||||
pullup-mask = <BIT(2)>;
|
||||
#pinmux-cells = <2>;
|
||||
};
|
||||
|
||||
pinctrlksol: pinctrl@f01d0d {
|
||||
compatible = "ite,it8xxx2-pinctrl-func";
|
||||
reg = <0x00f01d0d 1 /* KSOLGCTRL */
|
||||
0x00f01d02 1>; /* KSOCTRL */
|
||||
pp-od-mask = <BIT(0)>;
|
||||
pullup-mask = <BIT(2)>;
|
||||
#pinmux-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -90,6 +90,118 @@
|
|||
};
|
||||
|
||||
/* Keyboard alternate function */
|
||||
ksi0_default: ksi0_default {
|
||||
pinmuxs = <&pinctrlksi 0 IT8XXX2_ALT_FUNC_1>;
|
||||
bias-pull-up;
|
||||
};
|
||||
ksi1_default: ksi1_default {
|
||||
pinmuxs = <&pinctrlksi 1 IT8XXX2_ALT_FUNC_1>;
|
||||
bias-pull-up;
|
||||
};
|
||||
ksi2_default: ksi2_default {
|
||||
pinmuxs = <&pinctrlksi 2 IT8XXX2_ALT_FUNC_1>;
|
||||
bias-pull-up;
|
||||
};
|
||||
ksi3_default: ksi3_default {
|
||||
pinmuxs = <&pinctrlksi 3 IT8XXX2_ALT_FUNC_1>;
|
||||
bias-pull-up;
|
||||
};
|
||||
ksi4_default: ksi4_default {
|
||||
pinmuxs = <&pinctrlksi 4 IT8XXX2_ALT_FUNC_1>;
|
||||
bias-pull-up;
|
||||
};
|
||||
ksi5_default: ksi5_default {
|
||||
pinmuxs = <&pinctrlksi 5 IT8XXX2_ALT_FUNC_1>;
|
||||
bias-pull-up;
|
||||
};
|
||||
ksi6_default: ksi6_default {
|
||||
pinmuxs = <&pinctrlksi 6 IT8XXX2_ALT_FUNC_1>;
|
||||
bias-pull-up;
|
||||
};
|
||||
ksi7_default: ksi7_default {
|
||||
pinmuxs = <&pinctrlksi 7 IT8XXX2_ALT_FUNC_1>;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso0_default: kso0_default {
|
||||
pinmuxs = <&pinctrlksol 0 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso1_default: kso1_default {
|
||||
pinmuxs = <&pinctrlksol 1 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso2_default: kso2_default {
|
||||
pinmuxs = <&pinctrlksol 2 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso3_default: kso3_default {
|
||||
pinmuxs = <&pinctrlksol 3 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso4_default: kso4_default {
|
||||
pinmuxs = <&pinctrlksol 4 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso5_default: kso5_default {
|
||||
pinmuxs = <&pinctrlksol 5 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso6_default: kso6_default {
|
||||
pinmuxs = <&pinctrlksol 6 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso7_default: kso7_default {
|
||||
pinmuxs = <&pinctrlksol 7 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso8_default: kso8_default {
|
||||
pinmuxs = <&pinctrlksoh 0 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso9_default: kso9_default {
|
||||
pinmuxs = <&pinctrlksoh 1 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso10_default: kso10_default {
|
||||
pinmuxs = <&pinctrlksoh 2 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso11_default: kso11_default {
|
||||
pinmuxs = <&pinctrlksoh 3 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso12_default: kso12_default {
|
||||
pinmuxs = <&pinctrlksoh 4 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso13_default: kso13_default {
|
||||
pinmuxs = <&pinctrlksoh 5 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso14_default: kso14_default {
|
||||
pinmuxs = <&pinctrlksoh 6 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso15_default: kso15_default {
|
||||
pinmuxs = <&pinctrlksoh 7 IT8XXX2_ALT_FUNC_1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
kso16_gpc3_default: kso16_gpc3_default {
|
||||
pinmuxs = <&pinctrlc 3 IT8XXX2_ALT_FUNC_1>;
|
||||
bias-pull-up;
|
||||
|
|
|
@ -17,7 +17,12 @@
|
|||
struct pinctrl_soc_pin {
|
||||
/* Pinmux control group */
|
||||
const struct device *pinctrls;
|
||||
/* Pin configuration (impedance, pullup/down, voltate selection, input). */
|
||||
/*
|
||||
* Pin configuration
|
||||
* kSI[7:0] and KSO[15:0] pins only support pull-up, push-pull/open-drain.
|
||||
* GPIO group pinctrl pins (include KSO[17:16]) support impedance,
|
||||
* pull-up/down, voltage selection, input.
|
||||
*/
|
||||
uint32_t pincfg;
|
||||
/* GPIO pin */
|
||||
uint8_t pin;
|
||||
|
@ -31,11 +36,12 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
|||
* @brief PIN configuration bitfield.
|
||||
*
|
||||
* Pin configuration is coded with the following
|
||||
* fields.
|
||||
* Pin impedance config [ 0 ]
|
||||
* Pin pull-up/down config [ 4 : 5 ]
|
||||
* Pin voltage selection [ 8 ]
|
||||
* Pin input enable config [ 12 ]
|
||||
* bit fields.
|
||||
* Pin impedance config [ 0 ]
|
||||
* Pin pull-up/down config [ 4 : 5 ]
|
||||
* Pin voltage selection [ 8 ]
|
||||
* Pin input enable config [ 12 ]
|
||||
* Pin push-pull/open-drain [ 16 ]
|
||||
*/
|
||||
#define IT8XXX2_HIGH_IMPEDANCE 0x1U
|
||||
#define IT8XXX2_PULL_PIN_DEFAULT 0x0U
|
||||
|
@ -44,6 +50,8 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
|||
#define IT8XXX2_VOLTAGE_3V3 0x0U
|
||||
#define IT8XXX2_VOLTAGE_1V8 0x1U
|
||||
#define IT8XXX2_INPUT_ENABLE 0x1U
|
||||
#define IT8XXX2_PUSH_PULL 0x0U
|
||||
#define IT8XXX2_OPEN_DRAIN 0x1U
|
||||
|
||||
/* Pin tri-state mode. */
|
||||
#define IT8XXX2_IMPEDANCE_SHIFT 0U
|
||||
|
@ -51,12 +59,16 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
|||
/* Pin pull-up or pull-down */
|
||||
#define IT8XXX2_PUPDR_SHIFT 4U
|
||||
#define IT8XXX2_PUPDR_MASK 0x3U
|
||||
#define IT8XXX2_PULL_UP_MASK BIT_MASK(1)
|
||||
/* Pin 3.3V or 1.8V */
|
||||
#define IT8XXX2_VOLTAGE_SHIFT 8U
|
||||
#define IT8XXX2_VOLTAGE_MASK 0x1U
|
||||
/* Pin INPUT enable or disable */
|
||||
#define IT8XXX2_INPUT_SHIFT 12U
|
||||
#define IT8XXX2_INPUT_MASK 0x1U
|
||||
/* Pin push-pull/open-drain mode */
|
||||
#define IT8XXX2_PP_OD_SHIFT 16U
|
||||
#define IT8XXX2_PP_OD_MASK BIT_MASK(1)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to obtain configuration of tri-state.
|
||||
|
@ -82,6 +94,18 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
|||
#define IT8XXX2_DT_PINCFG_INPUT(__mode) \
|
||||
(((__mode) >> IT8XXX2_INPUT_SHIFT) & IT8XXX2_INPUT_MASK)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to obtain configuration of pull-up or not.
|
||||
*/
|
||||
#define IT8XXX2_DT_PINCFG_PULLUP(__mode) \
|
||||
(((__mode) >> IT8XXX2_PUPDR_SHIFT) & IT8XXX2_PULL_UP_MASK)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to obtain configuration of push-pull/open-drain mode.
|
||||
*/
|
||||
#define IT8XXX2_DT_PINCFG_PP_OD(__mode) \
|
||||
(((__mode) >> IT8XXX2_PP_OD_SHIFT) & IT8XXX2_PP_OD_MASK)
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
|
||||
*
|
||||
|
@ -99,7 +123,9 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
|||
((IT8XXX2_VOLTAGE_1V8 * DT_ENUM_IDX(node_id, gpio_voltage)) \
|
||||
<< IT8XXX2_VOLTAGE_SHIFT) | \
|
||||
((IT8XXX2_INPUT_ENABLE * DT_PROP(node_id, input_enable)) \
|
||||
<< IT8XXX2_INPUT_SHIFT))
|
||||
<< IT8XXX2_INPUT_SHIFT) | \
|
||||
((IT8XXX2_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) \
|
||||
<< IT8XXX2_PP_OD_SHIFT))
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize pinctrls of pinmuxs field in #pinctrl_pin_t.
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue