drivers: timer: riscv_machine_timer: Add support for OpenTitan
OpenTitan uses a timer compliant with the RISC-V privileged specification. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
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3 changed files with 28 additions and 1 deletions
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@ -10,7 +10,8 @@ config RISCV_MACHINE_TIMER
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DT_HAS_NEORV32_MACHINE_TIMER_ENABLED || \
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DT_HAS_NUCLEI_SYSTIMER_ENABLED || \
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DT_HAS_SIFIVE_CLINT0_ENABLED || \
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DT_HAS_TELINK_MACHINE_TIMER_ENABLED
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DT_HAS_TELINK_MACHINE_TIMER_ENABLED || \
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DT_HAS_LOWRISC_MACHINE_TIMER_ENABLED
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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@ -48,6 +48,13 @@
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#define MTIME_REG DT_INST_REG_ADDR(0)
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#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8)
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#define TIMER_IRQN DT_INST_IRQN(0)
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/* lowrisc,machine-timer */
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#elif DT_HAS_COMPAT_STATUS_OKAY(lowrisc_machine_timer)
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#define DT_DRV_COMPAT lowrisc_machine_timer
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#define MTIME_REG (DT_INST_REG_ADDR(0) + 0x110)
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#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 0x118)
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#define TIMER_IRQN DT_INST_IRQN(0)
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#endif
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#define CYC_PER_TICK ((uint32_t)((uint64_t) (sys_clock_hw_cycles_per_sec() \
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19
dts/bindings/timer/lowrisc,machine-timer.yaml
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19
dts/bindings/timer/lowrisc,machine-timer.yaml
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@ -0,0 +1,19 @@
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# Copyright (c) 2023 Rivos Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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OpenTitan Machine Timer
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The OpenTitan machine timer provides RISC-V privileged mtime and mtimecmp
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registers.
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compatible: "lowrisc,machine-timer"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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