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power_domain: Intel ADSP: Add power gating mechanism for Intel ADSP devices

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This adds power domain gating mechanisms for Intel ADSP devices.

Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
This commit is contained in:
Krzysztof Frydryk 2022-05-06 16:36:32 +02:00 • committed by Carles Cufí
commit 078de4e021
5 changed files with 159 additions and 0 deletions
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1
drivers/power_domain/CMakeLists.txt
View file

@ -4,3 +4,4 @@
zephyr_library()
zephyr_library_sources_ifdef(CONFIG_POWER_DOMAIN_GPIO power_domain_gpio.c)
zephyr_library_sources_ifdef(CONFIG_POWER_DOMAIN_INTEL_ADSP power_domain_intel_adsp.c)

5
drivers/power_domain/Kconfig
View file

@ -17,4 +17,9 @@ config POWER_DOMAIN_GPIO
depends on GPIO
depends on TIMEOUT_64BIT
config POWER_DOMAIN_INTEL_ADSP
bool "Use Intel ADSP power gating mechanisms"
help
Include Intel ADSP power domain control mechanisms
endif

80
drivers/power_domain/power_domain_intel_adsp.c Normal file
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@ -0,0 +1,80 @@
/*
* Copyright (c) 2022 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(power_domain_intel_adsp, LOG_LEVEL_INF);
#define PWRCTL_OFFSET 0xD0
#define PWRSTS_OFFSET 0xD2
struct pg_registers {
uint32_t wr_address;
uint32_t rd_address;
uint32_t SPA_bit;
uint32_t CPA_bit;
};
static int pd_intel_adsp_set_power_enable(struct pg_registers *reg, bool power_enable)
{
uint32_t SPA_bit_mask = BIT(reg->SPA_bit);
if (power_enable) {
sys_write32(sys_read32(reg->wr_address) | SPA_bit_mask, reg->wr_address);
} else {
sys_write32(sys_read32(reg->wr_address) & ~(SPA_bit_mask), reg->wr_address);
}
return 0;
}
static int pd_intel_adsp_pm_action(const struct device *dev, enum pm_device_action action)
{
struct pg_registers *reg_data = (struct pg_registers *)dev->data;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
pm_device_children_action_run(dev, PM_DEVICE_ACTION_TURN_ON, NULL);
pd_intel_adsp_set_power_enable(reg_data, true);
break;
case PM_DEVICE_ACTION_SUSPEND:
pm_device_children_action_run(dev, PM_DEVICE_ACTION_TURN_OFF, NULL);
pd_intel_adsp_set_power_enable(reg_data, false);
break;
case PM_DEVICE_ACTION_TURN_ON:
break;
case PM_DEVICE_ACTION_TURN_OFF:
break;
default:
return -ENOTSUP;
}
return 0;
}
static int pd_intel_adsp_init(const struct device *dev)
{
pm_device_init_suspended(dev);
pm_device_runtime_enable(dev);
return 0;
}
#define DT_DRV_COMPAT intel_adsp_power_domain
#define POWER_DOMAIN_DEVICE(id) \
static struct pg_registers pd_pg_reg##id = { \
.wr_address = DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(id), lps)) + PWRCTL_OFFSET, \
.rd_address = DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(id), lps)) + PWRSTS_OFFSET, \
.SPA_bit = DT_INST_PROP(id, bit_position), \
.CPA_bit = DT_INST_PROP(id, bit_position), \
}; \
PM_DEVICE_DT_INST_DEFINE(id, pd_intel_adsp_pm_action); \
DEVICE_DT_INST_DEFINE(id, pd_intel_adsp_init, PM_DEVICE_DT_INST_GET(id), \
&pd_pg_reg##id, NULL, POST_KERNEL, 75, NULL);
DT_INST_FOREACH_STATUS_OKAY(POWER_DOMAIN_DEVICE)

27
dts/bindings/power-domain/intel,adsp-power-domain.yaml Normal file
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@ -0,0 +1,27 @@
# Copyright (c) 2022 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
description: Power domains for intel ADSP
compatible: "intel,adsp-power-domain"
include: power-domain.yaml
properties:
lps:
type: phandle
required: true
description: |
A phandle to low power sequencer.
PWRCTL and PWRSTS registers used to write/read pwr gating
states are located there
bit-position:
type: int
required: true
description: |
Position of the bit to set in write_address (PWRCTL) or read in
read_address (PWRSTS) to set power active or confirm power active
for a desired domain.
Same for write and read addresses

46
dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
View file

@ -270,5 +270,51 @@
dma-buf-alignment = <128>;
status = "okay";
};
hub_ulp_domain: hub_ulp_domain {
compatible = "intel,adsp-power-domain";
lps = <&lps>;
bit-position = <15>;
};
hub_hp_domain: hub_hpp_domain {
compatible = "intel,adsp-power-domain";
lps = <&lps>;
bit-position = <6>;
};
io0_domain: io0_domain {
compatible = "intel,adsp-power-domain";
lps = <&lps>;
bit-position = <8>;
};
io1_domain: io1_domain {
compatible = "intel,adsp-power-domain";
lps = <&lps>;
bit-position = <9>;
};
io2_domain: io2_domain {
compatible = "intel,adsp-power-domain";
lps = <&lps>;
bit-position = <10>;
};
io3_domain: io3_domain {
compatible = "intel,adsp-power-domain";
lps = <&lps>;
bit-position = <11>;
};
hst_domain: hst_domain {
compatible = "intel,adsp-power-domain";
lps = <&lps>;
bit-position = <4>;
};
ml0_domain: ml0_domain {
compatible = "intel,adsp-power-domain";
lps = <&lps>;
bit-position = <12>;
};
ml1_domain: ml1_domain {
compatible = "intel,adsp-power-domain";
lps = <&lps>;
bit-position = <13>;
};
};
};