power_domain: Intel ADSP: Add power gating mechanism for Intel ADSP devices
This adds power domain gating mechanisms for Intel ADSP devices. Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
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5 changed files with 159 additions and 0 deletions
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@ -4,3 +4,4 @@
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_POWER_DOMAIN_GPIO power_domain_gpio.c)
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zephyr_library_sources_ifdef(CONFIG_POWER_DOMAIN_INTEL_ADSP power_domain_intel_adsp.c)
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@ -17,4 +17,9 @@ config POWER_DOMAIN_GPIO
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depends on GPIO
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depends on TIMEOUT_64BIT
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config POWER_DOMAIN_INTEL_ADSP
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bool "Use Intel ADSP power gating mechanisms"
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help
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Include Intel ADSP power domain control mechanisms
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endif
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80
drivers/power_domain/power_domain_intel_adsp.c
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80
drivers/power_domain/power_domain_intel_adsp.c
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@ -0,0 +1,80 @@
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/*
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* Copyright (c) 2022 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/pm/device_runtime.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(power_domain_intel_adsp, LOG_LEVEL_INF);
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#define PWRCTL_OFFSET 0xD0
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#define PWRSTS_OFFSET 0xD2
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struct pg_registers {
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uint32_t wr_address;
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uint32_t rd_address;
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uint32_t SPA_bit;
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uint32_t CPA_bit;
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};
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static int pd_intel_adsp_set_power_enable(struct pg_registers *reg, bool power_enable)
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{
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uint32_t SPA_bit_mask = BIT(reg->SPA_bit);
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if (power_enable) {
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sys_write32(sys_read32(reg->wr_address) | SPA_bit_mask, reg->wr_address);
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} else {
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sys_write32(sys_read32(reg->wr_address) & ~(SPA_bit_mask), reg->wr_address);
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}
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return 0;
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}
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static int pd_intel_adsp_pm_action(const struct device *dev, enum pm_device_action action)
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{
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struct pg_registers *reg_data = (struct pg_registers *)dev->data;
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switch (action) {
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case PM_DEVICE_ACTION_RESUME:
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pm_device_children_action_run(dev, PM_DEVICE_ACTION_TURN_ON, NULL);
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pd_intel_adsp_set_power_enable(reg_data, true);
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break;
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case PM_DEVICE_ACTION_SUSPEND:
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pm_device_children_action_run(dev, PM_DEVICE_ACTION_TURN_OFF, NULL);
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pd_intel_adsp_set_power_enable(reg_data, false);
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break;
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case PM_DEVICE_ACTION_TURN_ON:
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break;
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case PM_DEVICE_ACTION_TURN_OFF:
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int pd_intel_adsp_init(const struct device *dev)
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{
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pm_device_init_suspended(dev);
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pm_device_runtime_enable(dev);
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return 0;
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}
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#define DT_DRV_COMPAT intel_adsp_power_domain
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#define POWER_DOMAIN_DEVICE(id) \
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static struct pg_registers pd_pg_reg##id = { \
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.wr_address = DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(id), lps)) + PWRCTL_OFFSET, \
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.rd_address = DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(id), lps)) + PWRSTS_OFFSET, \
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.SPA_bit = DT_INST_PROP(id, bit_position), \
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.CPA_bit = DT_INST_PROP(id, bit_position), \
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}; \
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PM_DEVICE_DT_INST_DEFINE(id, pd_intel_adsp_pm_action); \
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DEVICE_DT_INST_DEFINE(id, pd_intel_adsp_init, PM_DEVICE_DT_INST_GET(id), \
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&pd_pg_reg##id, NULL, POST_KERNEL, 75, NULL);
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DT_INST_FOREACH_STATUS_OKAY(POWER_DOMAIN_DEVICE)
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27
dts/bindings/power-domain/intel,adsp-power-domain.yaml
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27
dts/bindings/power-domain/intel,adsp-power-domain.yaml
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# Copyright (c) 2022 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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description: Power domains for intel ADSP
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compatible: "intel,adsp-power-domain"
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include: power-domain.yaml
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properties:
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lps:
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type: phandle
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required: true
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description: |
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A phandle to low power sequencer.
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PWRCTL and PWRSTS registers used to write/read pwr gating
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states are located there
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bit-position:
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type: int
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required: true
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description: |
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Position of the bit to set in write_address (PWRCTL) or read in
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read_address (PWRSTS) to set power active or confirm power active
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for a desired domain.
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Same for write and read addresses
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@ -270,5 +270,51 @@
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dma-buf-alignment = <128>;
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status = "okay";
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};
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hub_ulp_domain: hub_ulp_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <15>;
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};
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hub_hp_domain: hub_hpp_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <6>;
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};
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io0_domain: io0_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <8>;
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};
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io1_domain: io1_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <9>;
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};
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io2_domain: io2_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <10>;
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};
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io3_domain: io3_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <11>;
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};
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hst_domain: hst_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <4>;
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};
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ml0_domain: ml0_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <12>;
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};
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ml1_domain: ml1_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <13>;
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};
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};
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};
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