drivers/ipm: Remove intel_adsp_mailbox driver
This is dead code. It's based on the cAVS "IPC" mechanism to allow communication to and from the host CPU. But there is no test rig in the Zephyr tree for the protocol defined. And in fact the only Zephyr-based user of the IPC mechanism (Sound Open Firmware) has its own IPC driver and speaks its own protocol with the host kernel. That driver needs to migrate into Zephyr soon and this legacy bit is just confusing. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross
Anas Nashif
parent
4652d6534e
commit
ab1baca03f
7 changed files with 0 additions and 250 deletions
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@ -277,7 +277,6 @@
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/drivers/ipm/ipm_mhu* @karl-zh
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/drivers/ipm/Kconfig.nrfx @masz-nordic
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/drivers/ipm/Kconfig.nrfx_ipc_channel @masz-nordic
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/drivers/ipm/ipm_intel_adsp.c @finikorg
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/drivers/ipm/ipm_cavs_idc* @dcpleung
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/drivers/ipm/ipm_nrfx_ipc.c @masz-nordic
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/drivers/ipm/ipm_nrfx_ipc.h @masz-nordic
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@ -8,7 +8,6 @@ zephyr_library_sources_ifdef(CONFIG_IPM_MHU ipm_mhu.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_STM32_IPCC ipm_stm32_ipcc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_NRFX ipm_nrfx_ipc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_CAVS_IDC ipm_cavs_idc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_INTEL_ADSP ipm_intel_adsp.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_STM32_HSEM ipm_stm32_hsem.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE ipm_handlers.c)
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@ -107,11 +107,6 @@ config IPM_CAVS_IDC
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Driver for the Intra-DSP Communication (IDC) channel for
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cross SoC communications.
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config IPM_INTEL_ADSP
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bool "IPM ADSP Host-DSP Communication driver"
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help
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Driver for the Host-DSP Mailbox Communication channel.
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config IPM_STM32_HSEM
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bool "STM32 HSEM controller"
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depends on STM32H7_DUAL_CORE
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@ -1,222 +0,0 @@
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/*
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* Copyright (c) 2020, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT intel_adsp_mailbox
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#include <device.h>
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#include <soc.h>
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#include <drivers/ipm.h>
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#include <platform/mailbox.h>
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#include <platform/shim.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(ipm_adsp, CONFIG_IPM_LOG_LEVEL);
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/*
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* With IPM data might be transferred by using ID field for simple
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* messages or via shared memory. Following parameters specify maximum
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* values for ID and DATA.
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*/
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#define IPM_INTEL_ADSP_MAX_DATA_SIZE 256
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#define IPM_INTEL_ADSP_MAX_ID_VAL IPC_DIPCI_MSG_MASK
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/* Mailbox ADSP -> Host */
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#define IPM_INTEL_ADSP_MAILBOX_OUT MAILBOX_DSPBOX_BASE
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#define IPM_INTEL_ADSP_MAILBOX_OUT_SIZE MAILBOX_DSPBOX_SIZE
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BUILD_ASSERT(IPM_INTEL_ADSP_MAILBOX_OUT_SIZE >= IPM_INTEL_ADSP_MAX_DATA_SIZE);
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/* Mailbox Host -> ADSP */
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#define IPM_INTEL_ADSP_MAILBOX_IN MAILBOX_HOSTBOX_BASE
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#define IPM_INTEL_ADSP_MAILBOX_IN_SIZE MAILBOX_HOSTBOX_SIZE
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BUILD_ASSERT(IPM_INTEL_ADSP_MAILBOX_IN_SIZE >= IPM_INTEL_ADSP_MAX_DATA_SIZE);
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struct ipm_adsp_config {
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void (*irq_config_func)(const struct device *dev);
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};
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struct ipm_adsp_data {
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ipm_callback_t callback;
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void *user_data;
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};
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static void ipm_adsp_isr(const struct device *dev)
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{
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const struct ipm_adsp_data *data = dev->data;
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uint32_t dipcctl, dipcie, dipct;
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dipct = ipc_read(IPC_DIPCT);
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dipcie = ipc_read(IPC_DIPCIE);
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dipcctl = ipc_read(IPC_DIPCCTL);
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LOG_DBG("dipct 0x%x dipcie 0x%x dipcctl 0x%x", dipct, dipcie, dipcctl);
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/*
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* DSP core has received a message from IPC initiator (HOST).
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* Initiator set Doorbel mechanism (HIPCI_BUSY bit).
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*/
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if (dipct & IPC_DIPCT_BUSY && dipcctl & IPC_DIPCCTL_IPCTBIE) {
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/* Mask BUSY interrupt */
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ipc_write(IPC_DIPCCTL, dipcctl & ~IPC_DIPCCTL_IPCTBIE);
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if (data->callback) {
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SOC_DCACHE_INVALIDATE((void *)IPM_INTEL_ADSP_MAILBOX_IN,
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IPM_INTEL_ADSP_MAILBOX_IN_SIZE);
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/* Use zero copy */
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data->callback(dev, data->user_data,
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dipct & IPC_DIPCI_MSG_MASK,
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(void *)IPM_INTEL_ADSP_MAILBOX_IN);
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}
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/*
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* Clear BUSY indicating to the Host that the message is
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* received, and DSP is ready to accept another message
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*/
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ipc_write(IPC_DIPCT, ipc_read(IPC_DIPCT) | IPC_DIPCT_BUSY);
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/* Unmask BUSY interrupts */
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ipc_write(IPC_DIPCCTL,
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ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCTBIE);
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}
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/*
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* DSP Initiator DONE indicates that we got reply from HOST that message
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* is received and we can send another message.
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*/
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if (dipcie & IPC_DIPCIE_DONE && dipcctl & IPC_DIPCCTL_IPCIDIE) {
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/* Mask DONE interrupt */
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ipc_write(IPC_DIPCCTL,
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ipc_read(IPC_DIPCCTL) & ~IPC_DIPCCTL_IPCIDIE);
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/* Clear DONE bit, Notify HOST that operation is completed */
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ipc_write(IPC_DIPCIE,
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ipc_read(IPC_DIPCIE) | IPC_DIPCIE_DONE);
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/* Unmask DONE interrupt */
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ipc_write(IPC_DIPCCTL,
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ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCIDIE);
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LOG_DBG("Not handled: IPC_DIPCCTL_IPCIDIE");
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/* TODO: implement queued message sending if needed */
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}
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}
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static int ipm_adsp_send(const struct device *dev, int wait, uint32_t id,
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const void *data, int size)
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{
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LOG_DBG("Send: id %d data %p size %d", id, data, size);
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LOG_HEXDUMP_DBG(data, size, "send");
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if (id > IPM_INTEL_ADSP_MAX_ID_VAL) {
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return -EINVAL;
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}
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if (size > IPM_INTEL_ADSP_MAX_DATA_SIZE) {
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return -EMSGSIZE;
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}
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if (wait) {
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while (ipc_read(IPC_DIPCI) & IPC_DIPCI_BUSY) {
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}
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} else {
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if (ipc_read(IPC_DIPCI) & IPC_DIPCI_BUSY) {
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LOG_DBG("Busy: previous message is not handled");
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return -EBUSY;
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}
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}
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memcpy((void *)IPM_INTEL_ADSP_MAILBOX_OUT, data, size);
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SOC_DCACHE_FLUSH((void *)IPM_INTEL_ADSP_MAILBOX_OUT, size);
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ipc_write(IPC_DIPCIE, 0);
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ipc_write(IPC_DIPCI, IPC_DIPCI_BUSY | id);
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return 0;
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}
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static void ipm_adsp_register_callback(const struct device *dev,
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ipm_callback_t cb,
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void *user_data)
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{
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struct ipm_adsp_data *data = dev->data;
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data->callback = cb;
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data->user_data = user_data;
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}
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static int ipm_adsp_max_data_size_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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LOG_DBG("dev %p", dev);
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return IPM_INTEL_ADSP_MAX_DATA_SIZE;
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}
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static uint32_t ipm_adsp_max_id_val_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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LOG_DBG("dev %p", dev);
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return IPM_INTEL_ADSP_MAX_ID_VAL;
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}
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static int ipm_adsp_set_enabled(const struct device *dev, int enable)
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{
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LOG_DBG("dev %p", dev);
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/* enable IPC interrupts from host */
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ipc_write(IPC_DIPCCTL, IPC_DIPCCTL_IPCIDIE | IPC_DIPCCTL_IPCTBIE);
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return 0;
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}
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static int ipm_adsp_init(const struct device *dev)
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{
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const struct ipm_adsp_config *config = dev->config;
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LOG_DBG("dev %p", dev);
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config->irq_config_func(dev);
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return 0;
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}
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static const struct ipm_driver_api ipm_adsp_driver_api = {
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.send = ipm_adsp_send,
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.register_callback = ipm_adsp_register_callback,
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.max_data_size_get = ipm_adsp_max_data_size_get,
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.max_id_val_get = ipm_adsp_max_id_val_get,
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.set_enabled = ipm_adsp_set_enabled,
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};
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static void ipm_adsp_config_func(const struct device *dev);
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static const struct ipm_adsp_config ipm_adsp_config = {
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.irq_config_func = ipm_adsp_config_func,
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};
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static struct ipm_adsp_data ipm_adsp_data;
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DEVICE_DT_INST_DEFINE(0,
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&ipm_adsp_init,
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NULL,
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&ipm_adsp_data, &ipm_adsp_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&ipm_adsp_driver_api);
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static void ipm_adsp_config_func(const struct device *dev)
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{
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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ipm_adsp_isr, DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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}
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@ -105,12 +105,5 @@
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interrupts = <8 0 0>;
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interrupt-parent = <&cavs0>;
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};
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mailbox: mailbox@71e00 {
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compatible = "intel,intel-adsp-mailbox";
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reg = <0x71E00 0x20>;
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interrupts = <0x7 0 3>;
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interrupt-parent = <&cavs0>;
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label = "IPM_0";
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};
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};
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};
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@ -105,12 +105,5 @@
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interrupts = <8 0 0>;
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interrupt-parent = <&cavs0>;
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};
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mailbox: mailbox@71e00 {
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compatible = "intel,intel-adsp-mailbox";
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reg = <0x71E00 0x20>;
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interrupts = <0x7 0 3>;
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interrupt-parent = <&cavs0>;
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label = "IPM_0";
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};
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};
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};
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@ -105,12 +105,5 @@
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interrupts = <8 0 0>;
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interrupt-parent = <&cavs0>;
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};
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mailbox: mailbox@71e00 {
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compatible = "intel,intel-adsp-mailbox";
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reg = <0x71E00 0x20>;
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interrupts = <0x7 0 3>;
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interrupt-parent = <&cavs0>;
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label = "IPM_0";
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};
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};
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};
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