dts: added dts binding for esp32c3
interrupt controller, also places its relevant peripheral sources allowing drivers to use the DT macros instead of espressif headers. Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
This commit is contained in:
Felipe Neves
Anas Nashif
parent
b97c2da2f2
commit
16be75b68f
4 changed files with 112 additions and 1 deletions
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@ -17,6 +17,7 @@
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#include <drivers/timer/system_timer.h>
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#include <sys_clock.h>
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#include <soc.h>
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#include <device.h>
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#define CYC_PER_TICK ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec() \
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/ (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
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@ -70,7 +71,7 @@ int sys_clock_driver_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,
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esp_intr_alloc(DT_IRQN(DT_NODELABEL(systimer0)),
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0,
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sys_timer_isr,
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NULL,
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18
dts/bindings/timer/espressif,esp32-systimer
Normal file
18
dts/bindings/timer/espressif,esp32-systimer
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@ -0,0 +1,18 @@
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# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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description: Espressif ESP32 Systimer peripheral
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compatible: "espressif,esp32-systimer"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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label:
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required: true
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@ -4,6 +4,7 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <dt-bindings/interrupt-controller/esp-esp32c3-intmux.h>
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/ {
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#address-cells = <1>;
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@ -34,6 +35,24 @@
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reg = <0x3fc7c000 0x50000>;
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};
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intc: interrupt-controller@600c2000 {
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#interrupt-cells = <1>;
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compatible = "espressif,esp32-intc";
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interrupt-controller;
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reg = <0x600c2000 0x198>;
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label = "INTC_0";
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status = "okay";
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};
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systimer0: systimer@60023000 {
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compatible = "espressif,esp32-systimer";
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reg = <0x60023000 0x80>;
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interrupts = <SYSTIMER_TARGET0_EDGE_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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label = "SYSTIMER_0";
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status = "okay";
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};
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uart0: uart@60000000 {
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compatible = "espressif,esp32c3-uart";
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reg = <0x60000000 0x400>;
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@ -0,0 +1,73 @@
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/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
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#define WIFI_MAC_INTR_SOURCE 0 /**< interrupt of WiFi MAC, level*/
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#define WIFI_MAC_NMI_SOURCE 1 /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
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#define WIFI_PWR_INTR_SOURCE 2 /**< */
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#define WIFI_BB_INTR_SOURCE 3 /**< interrupt of WiFi BB, level, we can do some calibartion*/
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#define BT_MAC_INTR_SOURCE 4 /**< will be cancelled*/
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#define BT_BB_INTR_SOURCE 5 /**< interrupt of BT BB, level*/
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#define BT_BB_NMI_SOURCE 6 /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
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#define RWBT_INTR_SOURCE 7 /**< interrupt of RWBT, level*/
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#define RWBLE_INTR_SOURCE 8 /**< interrupt of RWBLE, level*/
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#define RWBT_NMI_SOURCE 9 /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
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#define RWBLE_NMI_SOURCE 10 /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
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#define I2C_MASTER_SOURCE 11 /**< interrupt of I2C Master, level*/
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#define SLC0_INTR_SOURCE 12 /**< interrupt of SLC0, level*/
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#define SLC1_INTR_SOURCE 13 /**< interrupt of SLC1, level*/
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#define APB_CTRL_INTR_SOURCE 14 /**< interrupt of APB ctrl, ?*/
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#define UHCI0_INTR_SOURCE 15 /**< interrupt of UHCI0, level*/
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#define GPIO_INTR_SOURCE 16 /**< interrupt of GPIO, level*/
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#define GPIO_NMI_SOURCE 17 /**< interrupt of GPIO, NMI*/
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#define SPI1_INTR_SOURCE 18 /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
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#define SPI2_INTR_SOURCE 19 /**< interrupt of SPI2, level*/
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#define I2S1_INTR_SOURCE 20 /**< interrupt of I2S1, level*/
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#define UART0_INTR_SOURCE 21 /**< interrupt of UART0, level*/
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#define UART1_INTR_SOURCE 22 /**< interrupt of UART1, level*/
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#define LEDC_INTR_SOURCE 23 /**< interrupt of LED PWM, level*/
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#define EFUSE_INTR_SOURCE 24 /**< interrupt of efuse, level, not likely to use*/
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#define TWAI_INTR_SOURCE 25 /**< interrupt of can, level*/
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#define USB_INTR_SOURCE 26 /**< interrupt of USB, level*/
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#define RTC_CORE_INTR_SOURCE 27 /**< interrupt of rtc core, level, include rtc watchdog*/
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#define RMT_INTR_SOURCE 28 /**< interrupt of remote controller, level*/
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#define I2C_EXT0_INTR_SOURCE 29 /**< interrupt of I2C controller1, level*/
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#define TIMER1_INTR_SOURCE 30
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#define TIMER2_INTR_SOURCE 31
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#define TG0_T0_LEVEL_INTR_SOURCE 32 /**< interrupt of TIMER_GROUP0, TIMER0, level*/
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#define TG0_WDT_LEVEL_INTR_SOURCE 33 /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
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#define TG1_T0_LEVEL_INTR_SOURCE 34 /**< interrupt of TIMER_GROUP1, TIMER0, level*/
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#define TG1_WDT_LEVEL_INTR_SOURCE 35 /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
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#define CACHE_IA_INTR_SOURCE 36 /**< interrupt of Cache Invalied Access, LEVEL*/
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#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 37 /**< interrupt of system timer 0, EDGE*/
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#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 38 /**< interrupt of system timer 1, EDGE*/
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#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 39 /**< interrupt of system timer 2, EDGE*/
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#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 40 /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
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#define ICACHE_PRELOAD0_INTR_SOURCE 41 /**< interrupt of ICache perload operation, LEVEL*/
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#define ICACHE_SYNC0_INTR_SOURCE 42 /**< interrupt of instruction cache sync done, LEVEL*/
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#define APB_ADC_INTR_SOURCE 43 /**< interrupt of APB ADC, LEVEL*/
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#define DMA_CH0_INTR_SOURCE 44 /**< interrupt of general DMA channel 0, LEVEL*/
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#define DMA_CH1_INTR_SOURCE 45 /**< interrupt of general DMA channel 1, LEVEL*/
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#define DMA_CH2_INTR_SOURCE 46 /**< interrupt of general DMA channel 2, LEVEL*/
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#define RSA_INTR_SOURCE 47 /**< interrupt of RSA accelerator, level*/
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#define AES_INTR_SOURCE 48 /**< interrupt of AES accelerator, level*/
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#define SHA_INTR_SOURCE 49 /**< interrupt of SHA accelerator, level*/
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#define FROM_CPU_INTR0_SOURCE 50 /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
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#define FROM_CPU_INTR1_SOURCE 51 /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
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#define FROM_CPU_INTR2_SOURCE 52 /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
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#define FROM_CPU_INTR3_SOURCE 53 /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
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#define ASSIST_DEBUG_INTR_SOURCE 54 /**< interrupt of Assist debug module, LEVEL*/
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#define DMA_APBPERI_PMS_INTR_SOURCE 55
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#define CORE0_IRAM0_PMS_INTR_SOURCE 56
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#define CORE0_DRAM0_PMS_INTR_SOURCE 57
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#define CORE0_PIF_PMS_INTR_SOURCE 58
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#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 59
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#define BAK_PMS_VIOLATE_INTR_SOURCE 60
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#define CACHE_CORE0_ACS_INTR_SOURCE 61
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#endif
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