drivers: can: Add frontend for Atmel SAM M_CAN controller
This commit adds a frontend for the generic Bosch m_can driver for Atmel SAM series. Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
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5 changed files with 301 additions and 0 deletions
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@ -8,6 +8,7 @@ zephyr_library_sources_ifdef(CONFIG_CAN_LOOPBACK can_loopback.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_MCAN can_mcan.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_MCP2515 can_mcp2515.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_MCUX_FLEXCAN can_mcux_flexcan.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_SAM can_sam.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_STM32 can_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_STM32FD can_stm32fd.c)
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zephyr_library_sources_ifdef(CONFIG_CAN_RCAR can_rcar.c)
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@ -93,6 +93,7 @@ config CAN_AUTO_BUS_OFF_RECOVERY
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recessive bits). When this option is enabled, the recovery API is not
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available.
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source "drivers/can/Kconfig.sam"
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source "drivers/can/Kconfig.stm32"
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source "drivers/can/Kconfig.stm32fd"
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source "drivers/can/Kconfig.mcux"
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drivers/can/Kconfig.sam
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drivers/can/Kconfig.sam
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@ -0,0 +1,22 @@
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# SAM CAN configuration options
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# Copyright (c) 2021 Alexander Wachter
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_ATMEL_SAM_CAN := atmel,sam-can
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config CAN_SAM
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bool "Atmel SAM CAN driver"
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default $(dt_compat_enabled,$(DT_COMPAT_ATMEL_SAM_CAN))
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select CAN_MCAN
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if CAN_SAM
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config CAN_SAM_CKDIV
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int "Clock divider"
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range 0 255
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default 0
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depends on CAN_SAM
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help
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Clock divider for the MCAN core clock.
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endif #CAN_SAM
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258
drivers/can/can_sam.c
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drivers/can/can_sam.c
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@ -0,0 +1,258 @@
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/*
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* Copyright (c) 2021 Alexander Wachter
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "can_mcan.h"
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#include <drivers/can.h>
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#include <soc.h>
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#include <kernel.h>
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#include <logging/log.h>
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LOG_MODULE_DECLARE(can_driver, CONFIG_CAN_LOG_LEVEL);
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#define DT_DRV_COMPAT atmel_sam_can
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struct can_sam_config {
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struct can_mcan_config mcan_cfg;
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void (*config_irq)(void);
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struct soc_gpio_pin pin_list[2];
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uint8_t pmc_id;
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};
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struct can_sam_data {
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struct can_mcan_data mcan_data;
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struct can_mcan_msg_sram msg_ram;
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};
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static int can_sam_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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*rate = SOC_ATMEL_SAM_MCK_FREQ_HZ / (CONFIG_CAN_SAM_CKDIV + 1);
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return 0;
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}
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static void can_sam_set_state_change_callback(const struct device *dev,
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can_state_change_callback_t cb,
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void *user_data)
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{
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struct can_sam_data *data = dev->data;
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data->mcan_data.state_change_cb_data = user_data;
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data->mcan_data.state_change_cb = cb;
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}
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static void can_sam_clock_enable(const struct can_sam_config *cfg)
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{
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REG_PMC_PCK5 = PMC_PCK_CSS_PLLA_CLK | PMC_PCK_PRES(CONFIG_CAN_SAM_CKDIV);
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PMC->PMC_SCER |= PMC_SCER_PCK5;
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soc_pmc_peripheral_enable(cfg->pmc_id);
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}
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static int can_sam_init(const struct device *dev)
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{
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const struct can_sam_config *cfg = dev->config;
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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struct can_sam_data *data = dev->data;
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struct can_mcan_data *mcan_data = &data->mcan_data;
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struct can_mcan_msg_sram *msg_ram = &data->msg_ram;
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int ret;
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can_sam_clock_enable(cfg);
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soc_gpio_list_configure(cfg->pin_list, ARRAY_SIZE(cfg->pin_list));
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ret = can_mcan_init(dev, mcan_cfg, msg_ram, mcan_data);
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if (ret) {
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return ret;
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}
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cfg->config_irq();
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return ret;
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}
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static enum can_state can_sam_get_state(const struct device *dev, struct can_bus_err_cnt *err_cnt)
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{
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const struct can_sam_config *cfg = dev->config;
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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return can_mcan_get_state(mcan_cfg, err_cnt);
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}
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static int can_sam_send(const struct device *dev, const struct zcan_frame *frame,
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k_timeout_t timeout, can_tx_callback_t callback, void *user_data)
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{
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const struct can_sam_config *cfg = dev->config;
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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struct can_sam_data *data = dev->data;
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struct can_mcan_data *mcan_data = &data->mcan_data;
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struct can_mcan_msg_sram *msg_ram = &data->msg_ram;
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return can_mcan_send(mcan_cfg, mcan_data, msg_ram, frame, timeout, callback, user_data);
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}
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static int can_sam_add_rx_filter(const struct device *dev, can_rx_callback_t cb, void *cb_arg,
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const struct zcan_filter *filter)
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{
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struct can_sam_data *data = dev->data;
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struct can_mcan_data *mcan_data = &data->mcan_data;
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struct can_mcan_msg_sram *msg_ram = &data->msg_ram;
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return can_mcan_add_rx_filter(mcan_data, msg_ram, cb, cb_arg, filter);
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}
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static void can_sam_remove_rx_filter(const struct device *dev, int filter_id)
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{
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struct can_sam_data *data = dev->data;
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struct can_mcan_data *mcan_data = &data->mcan_data;
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struct can_mcan_msg_sram *msg_ram = &data->msg_ram;
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can_mcan_remove_rx_filter(mcan_data, msg_ram, filter_id);
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}
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static int can_sam_set_mode(const struct device *dev, enum can_mode mode)
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{
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const struct can_sam_config *cfg = dev->config;
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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return can_mcan_set_mode(mcan_cfg, mode);
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}
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static int can_sam_set_timing(const struct device *dev, const struct can_timing *timing,
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const struct can_timing *timing_data)
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{
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const struct can_sam_config *cfg = dev->config;
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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return can_mcan_set_timing(mcan_cfg, timing, timing_data);
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}
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static void can_sam_line_0_isr(const struct device *dev)
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{
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const struct can_sam_config *cfg = dev->config;
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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struct can_sam_data *data = dev->data;
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struct can_mcan_data *mcan_data = &data->mcan_data;
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struct can_mcan_msg_sram *msg_ram = &data->msg_ram;
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can_mcan_line_0_isr(mcan_cfg, msg_ram, mcan_data);
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}
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static void can_sam_line_1_isr(const struct device *dev)
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{
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const struct can_sam_config *cfg = dev->config;
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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struct can_sam_data *data = dev->data;
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struct can_mcan_data *mcan_data = &data->mcan_data;
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struct can_mcan_msg_sram *msg_ram = &data->msg_ram;
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can_mcan_line_1_isr(mcan_cfg, msg_ram, mcan_data);
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}
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static const struct can_driver_api can_api_funcs = {
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.set_mode = can_sam_set_mode,
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.set_timing = can_sam_set_timing,
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.send = can_sam_send,
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.add_rx_filter = can_sam_add_rx_filter,
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.remove_rx_filter = can_sam_remove_rx_filter,
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.get_state = can_sam_get_state,
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#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
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.recover = can_mcan_recover,
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#endif
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.get_core_clock = can_sam_get_core_clock,
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.set_state_change_callback = can_sam_set_state_change_callback,
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.timing_min = {
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.sjw = 0x1,
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.prop_seg = 0x00,
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.phase_seg1 = 0x01,
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.phase_seg2 = 0x01,
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.prescaler = 0x01
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},
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.timing_max = {
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.sjw = 0x7f,
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.prop_seg = 0x00,
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.phase_seg1 = 0x100,
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.phase_seg2 = 0x80,
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.prescaler = 0x200
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},
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#ifdef CONFIG_CAN_FD_MODE
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.timing_min_data = {
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.sjw = 0x01,
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.prop_seg = 0x00,
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.phase_seg1 = 0x01,
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.phase_seg2 = 0x01,
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.prescaler = 0x01
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},
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.timing_max_data = {
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.sjw = 0x10,
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.prop_seg = 0x00,
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.phase_seg1 = 0x20,
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.phase_seg2 = 0x10,
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.prescaler = 0x20
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}
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#endif
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};
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#define CAN_SAM_IRQ_CFG_FUNCTION(inst) \
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static void config_can_##inst##_irq(void) \
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{ \
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LOG_DBG("Enable CAN##inst## IRQ"); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_0, irq), \
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DT_INST_IRQ_BY_NAME(inst, line_0, priority), can_sam_line_0_isr, \
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DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(inst, line_0, irq)); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_1, irq), \
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DT_INST_IRQ_BY_NAME(inst, line_1, priority), can_sam_line_1_isr, \
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DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(inst, line_1, irq)); \
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}
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#ifdef CONFIG_CAN_FD_MODE
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#define CAN_SAM_MCAN_CFG(inst) \
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{ \
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.can = (struct can_mcan_reg *)DT_INST_REG_ADDR(inst), \
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.bus_speed = DT_INST_PROP(inst, bus_speed), .sjw = DT_INST_PROP(inst, sjw), \
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.sample_point = DT_INST_PROP_OR(inst, sample_point, 0), \
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.prop_ts1 = DT_INST_PROP_OR(inst, prop_seg, 0) + DT_INST_PROP_OR(inst, phase_seg1, 0), \
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.ts2 = DT_INST_PROP_OR(inst, phase_seg2, 0), \
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.bus_speed_data = DT_INST_PROP(inst, bus_speed_data), \
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.sjw_data = DT_INST_PROP(inst, sjw_data), \
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.sample_point_data = DT_INST_PROP_OR(inst, sample_point_data, 0), \
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.prop_ts1_data = DT_INST_PROP_OR(inst, prop_seg_data, 0) + \
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DT_INST_PROP_OR(inst, phase_seg1_data, 0), \
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.ts2_data = DT_INST_PROP_OR(inst, phase_seg2_data, 0), \
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.tx_delay_comp_offset = DT_INST_PROP(inst, tx_delay_comp_offset) \
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}
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#else /* CONFIG_CAN_FD_MODE */
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#define CAN_SAM_MCAN_CFG(inst) \
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{ \
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.can = (struct can_mcan_reg *)DT_INST_REG_ADDR(inst), \
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.bus_speed = DT_INST_PROP(inst, bus_speed), .sjw = DT_INST_PROP(inst, sjw), \
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.sample_point = DT_INST_PROP_OR(inst, sample_point, 0), \
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.prop_ts1 = DT_INST_PROP_OR(inst, prop_seg, 0) + DT_INST_PROP_OR(inst, phase_seg1, 0), \
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.ts2 = DT_INST_PROP_OR(inst, phase_seg2, 0), \
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}
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#endif /* CONFIG_CAN_FD_MODE */
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#define CAN_SAM_CFG_INST(inst) \
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static const struct can_sam_config can_sam_cfg_##inst = { \
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.pmc_id = DT_INST_PROP(inst, peripheral_id), \
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.pin_list = { ATMEL_SAM_DT_INST_PIN(inst, 0), ATMEL_SAM_DT_INST_PIN(inst, 1) }, \
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.config_irq = config_can_##inst##_irq, \
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.mcan_cfg = CAN_SAM_MCAN_CFG(inst) \
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};
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#define CAN_SAM_DATA_INST(inst) static struct can_sam_data can_sam_dev_data_##inst;
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#define CAN_SAM_DEVICE_INST(inst) \
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DEVICE_DT_INST_DEFINE(inst, &can_sam_init, NULL, &can_sam_dev_data_##inst, \
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&can_sam_cfg_##inst, POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
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&can_api_funcs);
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#define CAN_SAM_INST(inst) \
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CAN_SAM_IRQ_CFG_FUNCTION(inst) \
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CAN_SAM_CFG_INST(inst) \
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CAN_SAM_DATA_INST(inst) \
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CAN_SAM_DEVICE_INST(inst)
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DT_INST_FOREACH_STATUS_OKAY(CAN_SAM_INST)
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19
dts/bindings/can/atmel,sam-can.yaml
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dts/bindings/can/atmel,sam-can.yaml
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description: Specialization of Bosch m_can CAN-FD controller for Atmel SAM
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compatible: "atmel,sam-can"
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include: bosch,m-can.yaml
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properties:
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peripheral-id:
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type: int
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required: true
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description: peripheral ID
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pinctrl-0:
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type: phandles
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required: true
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description: |
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PIO configuration for CAN_RX and CAN_TX. We expect that the phandles will
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reference pinctrl nodes. These nodes will have a nodelabel that
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matches the Atmel SoC HAL defines and be of the form
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pinctrl-0 = <&pb3a_can0_rx0 &pb2a_can0_tx0>;
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