drivers: pwm: pwm_mcux: Reload mode option
DTS property "nxp,reload" selects how to load the buffered-registers with new values. Signed-off-by: Grixa Yrev <grixayrev@yandex.ru>
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b4fb5300da
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15a83fe0a0
2 changed files with 22 additions and 2 deletions
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@ -25,6 +25,7 @@ struct pwm_mcux_config {
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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pwm_clock_prescale_t prescale;
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pwm_register_reload_t reload;
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pwm_mode_t mode;
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bool run_wait;
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bool run_debug;
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@ -80,7 +81,7 @@ static int mcux_pwm_set_cycles(const struct device *dev, uint32_t channel,
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data->period_cycles[channel] = period_cycles;
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LOG_DBG("SETUP dutycycle to %u\n", duty_cycle);
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LOG_DBG("SETUP dutycycle to %u", duty_cycle);
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if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
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&clock_freq)) {
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@ -153,9 +154,12 @@ static int pwm_mcux_init(const struct device *dev)
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return err;
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}
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LOG_DBG("Set prescaler %d, reload mode %d",
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1 << config->prescale, config->reload);
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PWM_GetDefaultConfig(&pwm_config);
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pwm_config.prescale = config->prescale;
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pwm_config.reloadLogic = kPWM_ReloadPwmFullCycle;
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pwm_config.reloadLogic = config->reload;
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pwm_config.clockSource = kPWM_BusClock;
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pwm_config.enableDebugMode = config->run_debug;
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pwm_config.enableWait = config->run_wait;
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@ -193,6 +197,8 @@ static const struct pwm_driver_api pwm_mcux_driver_api = {
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.index = DT_INST_PROP(n, index), \
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.mode = kPWM_EdgeAligned, \
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.prescale = _CONCAT(kPWM_Prescale_Divide_, DT_INST_PROP(n, nxp_prescaler)),\
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.reload = DT_ENUM_IDX_OR(DT_DRV_INST(n), nxp_reload,\
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kPWM_ReloadPwmFullCycle),\
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
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.run_wait = DT_INST_PROP(n, run_in_wait), \
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@ -33,6 +33,20 @@ properties:
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description: |
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Clock prescaler at the input of the PWM.
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nxp,reload:
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type: string
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enum:
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- "immediate"
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- "half-cycle"
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- "full-cycle"
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- "half-and-full-cycle"
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description: |
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Select how to load the buffered-registers with new values:
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"immediate" - buffered-registers get loaded with new values as soon as LDOK bit is set;
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"half-cycle" - registers loaded on a PWM half cycle;
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"full-cycle" - registers loaded on a PWM full cycle;
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"half-and-full-cycle" - registers loaded on a PWM half & full cycle.
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"#pwm-cells":
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const: 2
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