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soc: arch: synopsys: move timer0/1 IRQ information to DT

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timer0/1 IRQ information was hardcoded in soc.h, however, Devicetree is
nowadays a better place to describe hardware. Note that I have followed
existing upstream Linux code to do these changes.

Ref.
- https://elixir.bootlin.com/linux/latest/source/arch/arc/boot/dts/
  hsdk.dts
- https://elixir.bootlin.com/linux/latest/source/Documentation/
  devicetree/bindings/timer/snps,arc-timer.txt

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas 2022-06-15 13:14:40 +02:00 • committed by Anas Nashif
commit 44250fe3d3
16 changed files with 79 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

12
boards/arc/nsim/nsim.dtsi
View file

@ -21,6 +21,18 @@
#interrupt-cells = <2>;
};
timer0: timer0 {
compatible = "snps,arc-timer";
interrupts = <16 1>;
interrupt-parent = <&intc>;
};
timer1: timer1 {
compatible = "snps,arc-timer";
interrupts = <17 1>;
interrupt-parent = <&intc>;
};
uart0: uart@f0000000 {
compatible = "ns16550";
clock-frequency = <50000000>;

12
boards/arc/qemu_arc/qemu_arc.dtsi
View file

@ -24,6 +24,18 @@
#interrupt-cells = <2>;
};
timer0: timer0 {
compatible = "snps,arc-timer";
interrupts = <16 1>;
interrupt-parent = <&intc>;
};
timer1: timer1 {
compatible = "snps,arc-timer";
interrupts = <17 1>;
interrupt-parent = <&intc>;
};
/* We are carving out of DRAM for a pseudo flash and sram region */
flash0: flash@80000000 {
compatible = "soc-nv-flash";

3
drivers/timer/arcv2_timer0.c
View file

@ -23,13 +23,14 @@
#undef _ARC_V2_TMR0_COUNT
#undef _ARC_V2_TMR0_CONTROL
#undef _ARC_V2_TMR0_LIMIT
#undef IRQ_TIMER0
#define _ARC_V2_TMR0_COUNT _ARC_V2_S_TMR0_COUNT
#define _ARC_V2_TMR0_CONTROL _ARC_V2_S_TMR0_CONTROL
#define _ARC_V2_TMR0_LIMIT _ARC_V2_S_TMR0_LIMIT
#define IRQ_TIMER0 IRQ_SEC_TIMER0
#else
#define IRQ_TIMER0 DT_IRQN(DT_NODELABEL(timer0))
#endif
#define _ARC_V2_TMR_CTRL_IE 0x1 /* interrupt enable */

12
dts/arc/synopsys/arc_hsdk.dtsi
View file

@ -54,6 +54,18 @@
interrupt-parent = <&intc>;
};
timer0: timer0 {
compatible = "snps,arc-timer";
interrupts = <16 1>;
interrupt-parent = <&intc>;
};
timer1: timer1 {
compatible = "snps,arc-timer";
interrupts = <17 1>;
interrupt-parent = <&intc>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;

6
dts/arc/synopsys/arc_iot.dtsi
View file

@ -27,6 +27,12 @@
#interrupt-cells = <2>;
};
timer0: timer0 {
compatible = "snps,arc-timer";
interrupts = <16 1>;
interrupt-parent = <&intc>;
};
iccm0: iccm@20000000 {
compatible = "arc,iccm";
reg = <0x20000000 0x40000>;

6
dts/arc/synopsys/emsdp.dtsi
View file

@ -29,6 +29,12 @@
#interrupt-cells = <2>;
};
timer0: timer0 {
compatible = "snps,arc-timer";
interrupts = <16 1>;
interrupt-parent = <&intc>;
};
iccm0: iccm@60000000 {
compatible = "arc,iccm";
reg = <0x60000000 0x20000>;

12
dts/arc/synopsys/emsk.dtsi
View file

@ -28,6 +28,18 @@
#interrupt-cells = <2>;
};
timer0: timer0 {
compatible = "snps,arc-timer";
interrupts = <16 1>;
interrupt-parent = <&intc>;
};
timer1: timer1 {
compatible = "snps,arc-timer";
interrupts = <17 1>;
interrupt-parent = <&intc>;
};
sysclk: system-clock {
compatible = "fixed-clock";
clock-frequency = <DT_APB_CLK_HZ>;

13
dts/bindings/timer/snps,arc-timer.yaml Normal file
View file

@ -0,0 +1,13 @@
# Copyright (c) 2022 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
description: |
Synopsys ARC Local Timer with Interrupt Capabilities
compatible: "snps,arc-timer"
include: base.yaml
properties:
interrupts:
required: true

6
samples/boards/arc_secure_services/src/main.c
View file

@ -6,7 +6,7 @@
#include <zephyr/zephyr.h>
#include <zephyr/sys/printk.h>
#include <soc.h>
#include <zephyr/devicetree.h>
#if defined(CONFIG_SOC_NSIM_SEM)
#define NORMAL_FIRMWARE_ENTRY 0x40000
@ -45,8 +45,8 @@ void main(void)
int32_t i = 0;
/* allocate timer 0 and timer1 to normal mode */
z_arc_v2_irq_uinit_secure_set(IRQ_TIMER0, 0);
z_arc_v2_irq_uinit_secure_set(IRQ_TIMER1, 0);
z_arc_v2_irq_uinit_secure_set(DT_IRQN(DT_NODELABEL(timer0)), 0);
z_arc_v2_irq_uinit_secure_set(DT_IRQN(DT_NODELABEL(timer1)), 0);
/* disable the secure interrupts for debug purpose*/
/* _arc_v2_irq_unit_int_disable(IRQ_S_TIMER0); */

2
soc/arc/snps_arc_hsdk/soc.h
View file

@ -18,8 +18,6 @@
/* ARC HS Core IRQs */
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#define IRQ_ICI 19
#ifndef _ASMLANGUAGE

2
soc/arc/snps_arc_iot/soc.h
View file

@ -20,8 +20,6 @@
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
/* ARC EM Core IRQs */
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#include "soc_irq.h"
#define BASE_ADDR_SYSCONFIG 0xF000A000

2
soc/arc/snps_emsdp/soc.h
View file

@ -20,8 +20,6 @@
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(100)
/* ARC EM Core IRQs */
#define IRQ_TIMER0 16
#define IRQ_SEC_TIMER0 20
#ifndef _ASMLANGUAGE

3
soc/arc/snps_emsk/soc.h
View file

@ -21,9 +21,6 @@
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
/* ARC EM Core IRQs */
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#if defined(CONFIG_BOARD_EM_STARTERKIT_R23) && defined(CONFIG_SOC_EMSK_EM7D)
#define IRQ_SEC_TIMER0 20
#endif /* CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EMSK_EM7D */

3
soc/arc/snps_nsim/soc.h
View file

@ -17,9 +17,6 @@
#include <zephyr/sys/util.h>
/* ARC EM Core IRQs */
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#define IRQ_SEC_TIMER0 20
#ifndef _ASMLANGUAGE

4
soc/arc/snps_qemu/soc.h
View file

@ -14,8 +14,4 @@
#ifndef _SOC__H_
#define _SOC__H_
/* ARC Core IRQs */
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#endif /* _SOC__H_ */

2
tests/kernel/context/src/main.c
View file

@ -27,7 +27,7 @@
#include <zephyr/irq_offload.h>
#include <zephyr/sys_clock.h>
#if defined(CONFIG_SOC_POSIX) || defined(CONFIG_ARC)
#if defined(CONFIG_SOC_POSIX)
/* TIMER_TICK_IRQ <soc.h> header for certain platforms */
#include <soc.h>
#endif